This was joint work accomplished with Marion Harmon and others at the Florida A&M University Computer Informations Systems department.
These pages were prepared for viewing in Netscape 1.1N..
This project's goals include predicting the execution time of programs and supporting the specification and analysis of timing constraints. We developed a flow analysis technique, which is similar to those used in optimizing compilers, to determine when a memory reference will or will not be in cache. This technique is being used to bound instruction and data cache performance and has been used to provide very fast instruction cache simulation. We can also model other hardware features, such as pipelines. Our analysis techniques include calculating the number of loop iterations, including loops with multiple exits and non-rectangular loop nests, and automatically detecting constraints when branches will be taken or fall through. In addition, we support extensions to the C language to allow a user to specify timing constraints. The program is analyzed to ensure that these timing constraints are not violated. Finally, a user interface has also been developed to support user-friendly analysis of timing constraints.