Journal Publications

  1. "Fast Context Switches: Compiler and Architectural Support for Preemptive Scheduling" by J. S. Snyder, D. B. Whalley, and T. P. Baker in Microprocessors and Microsystems, February 1995, pages 35-42.

  2. "Bounding Pipeline and Instruction Cache Performance" by C. A. Healy, R. D. Arnold, F. Mueller, D. B. Whalley, and M. G. Harmon in IEEE Transactions on Computers, January 1999, pages 53-70.

  3. "Timing Constraint Specification and Analysis" by L. Ko, N. Al-Yaqoubi, C. Healy, E. Ratliff, R. Arnold, D. Whalley, and M. G. Harmon in Software Practice & Experience, January 1999, pages 77-98.

  4. "Timing Analysis for Data Caches and Wrap-Around Fill Caches" by R. White, F. Mueller, C. Healy, D. Whalley, and M. Harmon, in Real-Time Systems, November 1999, pages 209-233.

  5. "Supporting Timing Analysis by Automatic Bounding of Loop Iterations" by C. Healy, M. Sjodin, V. Rustagi, D. Whalley, and R. van Engelen, in Real-Time Systems, May 2000, pages 121-148.

  6. "Automatic Detection and Exploitation of Branch Constraints for Timing Analysis" by C. Healy and D. Whalley, in IEEE Transactions on Software Engineering, to appear July, 2002.

Conference Publications

  1. "Efficient On-the-fly Analysis of Program Behavior and Static Cache Simulation" by F. Mueller and D. B. Whalley in the Proceedings of the First International Static Analysis Symposium, September 1994, pages 101-115.

  2. "Bounding Worst-Case Instruction Cache Performance" by R. D. Arnold, F. Mueller, D. B. Whalley, and M. G. Harmon in the Proceedings of the IEEE Real-Time Systems Symposium, December 1994, pages 172-181.

  3. "Fast Instruction Cache Analysis via Static Cache Simulation" by F. Mueller and D. B. Whalley in the Proceedings of the 28th Annual Simulation Symposium, April 1995, pages 105-114.

  4. "Integrating the Timing Analysis of Pipelining and Instruction Caching" by C. A. Healy, D. B. Whalley, and M. G. Harmon in the Proceedings of the IEEE Real-Time Systems Symposium, December 1995, pages 288-297.

  5. "Supporting the Specification and Analysis of Timing Constraints" by L. Ko, C. Healy, E. Ratliff, R. Arnold, D. Whalley, and M. G. Harmon in the Proceedings of the IEEE Real-Time Technology and Applications Symposium, June 1996, pages 170-178.

  6. "Timing Analysis of Data Caches and Set-Associative Caches" by R. White, F. Mueller, C. Healy, D. Whalley, and M. G. Harmon in the Proceedings of the IEEE Real-Time Technology and Applications Symposium, June 1997, pages 192-202.

  7. "Bounding Loop Iterations for Timing Analysis" by C. Healy, M. Sjodin, V. Rustagi, and D. Whalley in the Proceedings of the IEEE Real-Time Technology and Applications Symposium, June 1998, pages 12-21.

  8. "Tighter Timing Predictions by Automatic Detection and Exploitation of Value-Dep endent Constraints" by C. Healy and D. Whalley in the Proceedings of the IEEE Real-Time Technology and Applications Symposium, June 1999, pages 79-88.

  9. "A General Approach for Tight Timing Predictions of Non-Rectangular Loops" by C. Healy, R. van Engelen and D. Whalley in the WIP Proceedings of the IEEE Real-Time Technology and Applications Symposium, June 1999, pages 11-14.

Workshop Publications

  1. "Predicting Instruction Cache Behavior" by F. Mueller, D. B. Whalley, M. G. Harmon in the Proceedings of the ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, June 1994.

  2. "On Debugging Real-Time Applications" by F. Mueller and D. B. Whalley in the Proceedings of the ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, June 1994.

  3. "Real-Time Debugging by Minimal Hardware Simulation" by F. Mueller, D. B. Whalley, and M. G. Harmon in the Proceedings of the PEARL Workshop uber Realzeitsysteme, December 1994, pages 68-76.

  4. "Supporting User-Friendly Analysis of Timing Constraints" by L. Ko, D. B. Whalley, M. G. Harmon in the Proceedings of the ACM SIGPLAN Workshop on Language, Compilers, and Tools for Real-Time Systems, June 1995, pages 107-115.

  5. "Parametric Timing Analysis" by E. Vivancos, C. Healy, F. Mueller, and D. Whalley in the Proceedings of the ACM SIGPLAN Workshop on Language, Compilers, and Tools for Embedded Systems, June 2001, pages 88-93.