Chapter 7: Large and Fast: Exploiting Memory Hierarchy
1: Concepts Introduced in Chapter 7
2: Principle of Locality
3: Memory Hierarchy
4: Figure 7.1: The basic structure of a memory hierarchy.
5: Table at the Bottom of Page 541
6: Components of a Memory Hierarchy
7: Figure 7.2: Every pair of levels in the memory hierarchy can be thought of as having an upper and lower level.
8: Memory Hierarchy Terms
9: Figure 7.3: This diagram shows the structure of a memory hierarchy: as the distance from the CPU increases, so does the size.
10: Memory Hierarchy Questions
11: Cache Terms
12: Physical Address
13: Cache Organizations
14: Figure 7.5: A direct mapped cache with eight entries showing the addresses of memory words between 0 and 31 that map to the same cache locations.
15: Table at Bottom of Page 547
16: Figure 7.6: The cache contents are shown after each reference request that misses with the index and tag fields shown in binary.
17: Figure 7.7: For this cache, the lower portion of the address is used to select a cache entry consisting of a data word and a tag.
18: Steps to Be Taken on an Instruction Cache Miss
19: Cache Misses Can Be Overlapped with Other Pipeline Stalls
20: Pipelined Machines Use Separate Caches
21: Instruction Scheduling Is More Effective on Machines with Nonblocking Data Caches
22: Figure 7.9: Instruction and data miss rates for the DECStation 3100 when executing two different programs.
23: Write Policy
24: Write Miss Policy
25: Figure 7.10: A 64 KB cache using four-word (16 byte) blocks.
26: Larger Block Size Example
27: Figure 7.11: The miss rates for gcc and spice with a cache like that in the DecStation 3100 with a block size of either one word or four words.
28: Figure 7.12: Miss rate versus block size.
29: Main Memory Terms
30: Figure 7.13: The primary method of achieving higher memory bandwidth is to increase the physical or logical width of the memory system.
31: DRAM Examples
32: DRAM Organization
33: Figure 7.14: DRAM sizes increase by multiples of four approximately once every three years.
34: Cache Impact on Performance
35: Figure 7.15: The location of a memory block whose address is 12 in a cache with eight blocks varies for direct-mapped, set-associative, and fully associative placement.
36: Figure 7.16: An eight-block cache configured as direct mapped, two-way set associative, four-way set associative, and fully associative.
37: Figure 7.19: The implementation of a four-way set-associative cache requires four comparators and a 4-to-1 multiplexor.
38: Block Replacement
39: Set Associativity Example
40: Write-Through, No Write Allocate Example
41: Write-Back, Write Allocate Example
42: Secondary Caches
43: Average Memory Access Time
44: Techniques for Improving Cache Performance
45: Overlays
46: Virtual Memory
47: Virtual Memory Terms
48: Figure 7.20: In virtual memory, blocks of memory are mapped from one set of addresses, called virtual addresses, to another set called physical addresses.
49: Figure 7.21: Mapping from a virtual to a physical address.
50: Table at Bottom of Page 541 Again
51: Designing Virtual Memory Systems
52: Page Tables
53: Figure 7.22: The page table is indexed with the virtual page number to obtain the corresponding portion of the physical address.
54: Figure 7.23: The page table maps each page in virtual memory to either a page in physical memory or a page stored on disk, which is the next level in the hierarchy.
55: Translation Lookaside Buffers
56: Figure 7.24: The TLB acts as a cache on the page table for the entries that map to physical pages only.
57: Figure 7.27: The possible combinations of events in the TLB, virtual memory system, and cache.
58: TLB and Page Table Example
59: Fast Address Translation
60: Process Protection
61: Support for Multiprogramming
62: Techniques to Reduce the Number of Page Faults
63: Figure 7.28: The key quantitative design parameters that characterize the three major memory hierarchies in a machine.
64: Categorizing Misses
65: Figure 7.30: The miss rate can be broken into the three sources of misses.
66: Figure 7.31: Memory hierarchy design challenges.
67: Fallacies and Pitfalls
