Makefiles

The main purpose of the Unix make utility is is to determine automatically which pieces of a large program need to be recompiled, and issue the commands to recompile them. However, it is a very powerful tool that can also be adapted for other purposes.

These notes are not intended to fully explain the make utility. To learn more about make, you can start with the man pages, but beware they may be slightly different on each system you use. This is because there are different versions of make on different systems, with various special features. If you want to write portable code you should use only the standard features that are documented in the UNIX standard. (See the on-line UNIX 98 standard for detailed explanation of make.)

To prepare to use make, you must write a file called a makefile that describes the relationships among files in your program and the commands for updating each file. Typically the makefile describes the source files, how to compile them to produce object files, and how to link the object files to produce one or more programs. By default, the make utility looks for a makefile file called "makefile" or "Makefile", though the user may specify another name for the makefile.

Once a suitable makefile exists, each time you change some source files, the simple shell command make suffices to perform all necessary recompilations. The make program uses the information in the makefile and the last-modification times of the files to decide which of the files need to be updated.

A Simple Example

# an example of a very simple makefile

PROGRAMS=prog1 prog2
CCOPTS=-Wall -ansi -pedantic

all: $(PROGRAMS)

prog1: shared.h prog1.c
        gcc -Wall -ansi -pedantic -o prog1 prog1.c
prog2: shared.h funcs.o prog2.c
        gcc -Wall -ansi -pedantic -o prog2 funcs.o prog1.c
clean:
        rm -f $(PROGRAMS) *~ core #*#

Observe:

• [comments] lines beginning with # are comments
• [variables] the makefile may contain variable definitions
• • PROGRAMS=prog1 prog2 defines the names of two programs that the makefile specifies how to build
  • CCOPTS=-Wall -ansi -pedantic specifies a list of command-line options that are to be used with the compiler
• [all:] The line "all: $(PROGRAMS)" will cause the files whose names are given by the variable PROGRAMS to be built by default whenever the make utility is called. This is a degenerate case of a dependency rule. In general, a dependency rule tells the make utility that the file or files whose names are left of the colon -- called the targets -- depend on the files whose names appear to the right. Normally, it is followed by instructions that will create or update the dependent file(s). By default, the make utility will try to make the targets of the first dependency rule -- in this case, all. Because this target depends on the files prog1 and prog2, the make utility will first bring those files up to date. Since there are no instructions to actually create a file all, this means every time we execute the make utility with no arguments it will check that the files given by the variable PROGRAMS are all up to date.
• [prog1:] The second dependency is the normal kind. It specifies that the file prog1 depends on the files shared.h and prog1.c That means that if prog1 does not exist or if it exists but has been modified more recently than shared.h or prog1.c, then it should be regenerated. Following it is the command that should be executed to generate the file prog1. The command or commands must immediately follow the dependency line, and must start with a tab (not spaces).
• [clean:] The last dependency is for clean, another dummy target, similar to the dummy target all. There is never any file named clean so if a person executes make clean the make utility will simply execute the commands for this dependency rule. Those commands will remove all the various temporary files that are byproducts of making other targets, so that the next call to the make utility will build everything from scratch.

The syntax of a makefile is not the same as a shell script, although there are some similarities and shell commands may be embedded in the construction rules of the makefile. In particular, in a makefile it is OK to have spaces in symbol definitions, such as CC = gcc, but if you leave spaces like that in a shell script the shell would try to execute gcc. Another difference is that to refer to the value of a make variable you use the syntax $(variablename) but to refer to the value of a shell variable you use the syntax ${variablename}.

A More Sophisticated Example

# a makefile that uses a suffix-based pattern
PROGRAMS=prog1 prog2
...
include Config
.c:
        $(CC) $(CFLAGS) $(LDFLAGS) -o $@ mylib.o $<
all: $(PROGRAMS)

Observe:

• the suffix-based general rule for compiling C programs:

  .c:
          $(CC) $(CFLAGS) $(LDFLAGS) -o $@ myobject.o $
  

  This rule specifies that the make utility should try to build any target file filename, if there is a corresponding file filename.c, by executing the command pattern

          $(CC) $(CFLAGS) $(LDFLAGS) -o $@ myobject.o $<
  

  The symbols in this command will be expanded out by the make utility before it executes the command, replacing $@ by the current target. For example, if CC has been defiend to be "gcc", CFLAGS has been defined to be "-ansi -g", and LDFLAGS has been defined to be "-lsocket -lnsl", the would expand out to

  gcc -ansi -g -o filename -lsocket -lnsl myobject.o filename.c
  

  This particular rule is shown for pedagogical reasons only. These particular libraries and the object file myobject.o have no special significance.

• the use of the line include Config to include configurable text from the file Config

  For example, the file Config might contain the following:

  CFLAGS=-ansi -g
  CC=gcc
  LDFLAGS=-lnsl -lsocket
  

• the use of variables CC, CFLAGS, and LDFLAGS to specify compiler options

The example above could be simplified still further, if we did not want to always link in the special object file myobject.o. By default, make has certain built-in rules. One of these is:

.c:
$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $<