Publications

Here is a list of my published papers (currently out of date, but it should be fixed by June 12, 2008). These papers are gzip'ed postscript files. A few of the papers are not in the published form: For the IJPP papers, the final editing was done on proof sheets and the format of sections and references differs from the published form.

  • Optimizing Memory Subsystem Designs by Exploiting Region Reference Characteristics (0 bytes) Postscript
    Hsien-Hsin Lee, Chris Newburn, Mikhail Smelyanski and Gary Tyson
    To appear in IEEE Transactions on Computers.

  • High Quality ISA Synthesis for Low-Power Cache Designs in Embedded Processors (0 bytes) Postscript
    Allen Cheng and Gary Tyson
    IBM Journal of Research and Development (JRD), Vol 50, No 1, April 2006, to appear.

  • Exhaustive Optimization Phase Order Space Exploration (0 bytes) Postscript
    Prasad Kulkarni, David Whalley, Gary Tyson and Jack Davidson
    Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, March 2006.

  • Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation (0 bytes) Postscript
    Mike Geiger, Gary Tyson and Sally McKee
    Proceedings of the International Conference on High Performance Embedded Architectures and Compilers, November 2005.

  • Reducing Instruction Fetch Cost by Packing Instructions into Register Windows (0 bytes) Postscript
    Steve Hines. Gary Tyson and David Whalley
    Proceedings of the 38th Annual International Symposium on Microarchitecture (MICRO38), November 2005.

  • Improving the Energy and Execution Efficiency of a Small Instruction Cache by Using an Instruction Register File (0 bytes) Postscript
    Steve Hines. Gary Tyson and David Whalley
    Proceedings of the second Watson conference on Interactions between Architecture, Circuits and Compilers (PAC2), pp. 160-169, September 2004.

  • Java Debugging Guide (0 bytes) Postscript
    Sandy Bartlett, Ann Ford, Toby Teorey, and Gary Tyson
    ISBN: 0536987041; Published: August 2005, Pearson Publishing.

  • C++ Debugging Guide (0 bytes) Postscript
    Ann Ford, Toby Teorey, and Gary Tyson,
    ISBN: 0536987653; Published: August 2005, Pearson Publishing.

  • Improving Program Efficiency by Packing Instructions into Registers (0 bytes) Postscript
    Steve Hines, Joshua Green, Gary Tyson and David Whalley
    IEEE Transactions on Computers, Vol 54, No. 6, pp. 698-713, June 2005. Proceedings of the 2005 IEEE International Symposium on Computer Architecture (ISCA), June 2005.

  • An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded Systems Designs (0 bytes) Postscript
    Allen Cheng and Gary Tyson
    IEEE Transactions on Computers, Vol 54, No. 6, pp. 698-713, June 2005.

  • Drowsy Region Based Caches: Minimizing both Dynamic and Static Power Dissipation (0 bytes) Postscript
    Mike Geiger, Gary Tyson and Sally McKee
    Proceedings of the 2005 ACM International Conference on Computing Frontiers, May 2005.

  • PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis (0 bytes) Postscript
    Allen Cheng and Gary Tyson
    Proceedings of the 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2005.

  • Application Specific Instruction Set Synthesis to Reduce Instruction Cache Power in Embedded Processors (0 bytes) Postscript
    Allen Cheng and Gary Tyson
    Proceedings of the first Watson conference on Interactions between Architecture, Circuits and Compilers (PAC2), October 2004.

  • Reducing Static Power Dissipation on Region Based Caches (0 bytes) Postscript
    Mike Geiger and Gary Tyson
    Proceedings of the first Watson conference on Interactions between Architecture, Circuits and Compilers (PAC2), October 2004.

  • FITS: Framework Based Instruction Set Tuning for Embedded Application Specific Processors (0 bytes) Postscript
    Allen Cheng, Gary Tyson and Trevor Mudge
    Proceedings of the 41st Design Automation Conference, pp 940-943, June 2004.

  • FITS: Increasing Code Density for Embedded Systems with a Cost Effective 16-bit Synthesis Technique (0 bytes) Postscript
    Allen Cheng, Gary Tyson and Trevor Mudge
    Digest of the 2nd workshop on Optimization for DSP and Embedded Systems (ODES-2), March 2004.

  • A Prefetch Taxonomy (0 bytes) Postscript
    Viji, Srinivasan, Edward Davidson and Gary Tyson
    IEEE Transactions on Computers 53(2), pp. 126-140, February 2004.

  • Practical Debugging in Java (0 bytes) Postscript
    Ann Ford, Toby Teorey, Sandra Bartlett and Gary Tyson,
    ISBN: 0131427814; Published: July 2003, Prentice Hall.

  • Exploiting Load Latency Tolerance for Relaxed Cache Design Constraints (0 bytes) Postscript
    Ramu Pyreddy and Gary Tyson
    Proceedings of the Workshop on Complexity-Effective Design, June 2002.

  • Improving Bandwidth Utilization using Eager Writeback (0 bytes) Postscript
    Hsien-Hsin Lee, Gary Tyson and Matthew Farrens
    International Journal of Parallel Programming 3(1) October 2001.

  • Allocation by Conflict: A Simple, Effective Cache Management Scheme (0 bytes) Postscript
    Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson and Edward Davidson
    IEEE International Conference of Computer Design, Sept 2001.

  • Evaluating the Use of Register Queues in Software Pipelined Loops (135,156 bytes) Postscript
    Gary Tyson, Mikhail Smelyanski and Edward Davidson
    IEEE Transactions on Computers, Vol, 50, No. 8, pp. 769 - 783, August 2001.

  • Evaluating Design Tradeoffs in Dual Pipelines (0 bytes) Postscript
    Ramu Pyreddy and Gary Tyson
    Workshop on Complexity-Effective Design in association with the 28th Annual Symposium on Computer Architecture, 2001.

  • Stack Value File: Custom Microarchitecture for the Stack (291,358 bytes) Postscript
    Hsien-Hsin Lee, Mikhail Smelyanski, Chris Newburn and Gary Tyson
    Seventh International Symposium on High Performance Computer Architecture (HPCA-7), pp. 5-14, Jan. 2001.

  • Branch History Guided Instruction Prefetching (111,804 bytes) Postscript
    Viji Srinivasan, Edward Davidson and Gary Tyson
    Seventh International Symposium on High Performance Computer Architecture (HPCA-7), pp. 291-300, Jan. 2001.

  • Eager Writeback - a Technique for Improving Bandwidth Utilization (305,615 bytes) Postscript
    Hsien-Hsin Lee, Gary Tyson and Matthew Farrens
    33rd Annual International Symposium on Microarchitecture (Micro 33), pp. 11-20, Dec. 2000.

  • Improving BTB performance in the presence of DLLs (366,032 bytes) Postscript
    Steve Vlaovic, Edward Davidson and Gary Tyson
    33rd Annual International Symposium on Microarchitecture (Micro 33), pp. 77-86, Dec. 2000.

  • Region-based caching: An energy-delay efficient memory architecture for embedded processors (159,265 bytes) Postscript
    Hsien-Hsin Lee and Gary Tyson
    International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2000), Nov. 2000.

  • Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining (269,829 bytes) Postscript
    Mikhail Smelyanskiy, Gary Tyson and Edward Davidson
    International Conference on Parallel Architectures and Compilation Techniques (PACT 2000), Oct 2000.

  • Quantifying Instruction-Level Parallelism Limits on an EPIC Architecture (456,283 bytes) Postscript
    Hsien-Hsin Lee, Youfeng Wu, and Gary Tyson
    IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 21-27, April 2000.

  • Instruction Overhead and Data Locality Effects in Superscalar Processors (83,894 bytes) Postscript
    Murali Annavaram, Gary S. Tyson and Edward S. Davidson
    IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 95-100, April 2000.

  • A Prefetch Taxonomy (129,646 bytes) Postscript
    Viji Srinivasan, Edward Davidson and Gary Tyson
    UM EECS/CSE Technical Report CSE-TR-424-00. April 2000.

  • SpliCS - Split Latency Cache System (118,728 bytes) Postscript
    Viji Srinivasan, Mark Charney, Gary Tyson and Edward Davidson
    UM EECS/CSE Technical Report CSE-TR-425-00. April 2000.

  • Memory Renaming: Fast, Early and Accurate Processing of Memory Communication (144,895 bytes) Postscript
    Gary Tyson and Todd Austin
    International Journal of Parallel Programming, 1999.

  • Classifying Load and Store Instructions for Memory Renaming (247,893 bytes) Postscript
    Glenn Reinman, Brad Calder, Dean Tullsen, Gary Tyson and Todd Austin
    ACM International Conference on Supercomputing, pg. 399-407, June 1999.

  • Active Management of Data Caches by Exploiting Reuse Information (156,095 bytes) Postscript
    Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson and Edward S. Davidson
    IEEE Transactions on Computers, Vol 48, No 11, pp. 1244-1259, Nov 1999.

  • Performance Limits of Trace Caches. (282,900 bytes) Postscript
    Matt Postiff, Gary Tyson and Trevor Mudge
    Journal of Instruction Level Parallelism, 1999.

  • Limits of Instruction Level Parallelism in SPEC95 Applications. (196,891 bytes) Postscript
    Matthew A. Postiff, David A. Green, Gary S. Tyson and Trevor N. Mudge
    Computer Architecture News, Vol 27 No. 1, March 1999.

  • MirvSim: A high level simulator integrated with the Mirv compiler. (39,052 bytes) Postscript
    Krisztian Flautner, Gary S. Tyson and Trevor Mudge
    Computer Architecture News, Vol 27 No. 1, March 1999.

  • Eager Writeback a Technique for Improving Bandwidth Utilization. (594,741 bytes) Postscript
    Hsien-Hsin Lee, Gary Tyson and Matthew Farrens
    UM EECS/CSE Technical Report CSE-TR-399-99. June 1999.

  • A Static Filter for Reducing Prefetch Traffic. (98,026 bytes) Postscript
    Viji Srinivasan, Gary Tyson and Edward Davidson
    UM EECS/CSE Technical Report CSE-TR-400-99. June 1999.

  • Allocation By Conflict A Simple Effective Cache Management Scheme. (95,960 bytes) Postscript
    Edward Tam, Gary Tyson and Edward Davidson
    UM EECS/CSE Technical Report CSE-TR-401-99. June 1999.

  • Analyzing the Working Set Characteristics of Branch Execution (54,751 bytes) Postscript
    Sangwook P. Kim and Gary S. Tyson
    Proceeding of the 31th Annual Symposium on Microarchitecure, Dec 1998.

  • MirvSim: A high level simulator integrated with the Mirv compiler. (39,052 bytes) Postscript
    Krisztian Flautner, Gary S. Tyson and Trevor Mudge
    Proc. 3rd Workshop Interaction between Compilers and Computer Architectures (INTERACT-3) at ASPLOS-VIII, Oct, 1998.

  • Limits of Instruction Level Parallelism in SPEC95 Applications. (358,215 bytes) Postscript
    Matthew A. Postiff, David A. Green, Gary S. Tyson and Trevor N. Mudge
    Proc. 3rd Workshop Interaction between Compilers and Computer Architectures (INTERACT-3) at ASPLOS-VIII, Oct, 1998.

  • Evaluating the Performance of Active Cache Management Schemes (61,781 bytes) Postscript
    Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson and Edward S. Davidson
    Proceedings of the 1998 IEEE International Conference on Computer Design, October 1998

  • Utilizing Reuse Information in Data Cache Management (67,978 bytes) Postscript
    Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson and Matthew Farrens
    Proceedings of the 12th ACM International Conference on Supercomputing July, 1998

  • mlcache: A Flexible Multi-Lateral Cache Simulator (69,254 bytes) Postscript
    Proceedings of the 6th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS '98) July, 1998

  • Performance Limits of Trace Caches. (tech report version) (93,316 bytes) Postscript
    Matt Postiff, Gary Tyson and Trevor Mudge
    UM EECS/CSE Technical Report CSE-TR-373-98. Sep, 1998.

  • Improving the Accuracy and Performance of Memory Communication Through Renaming (105,351 bytes) Postscript
    Gary S. Tyson and Todd M. Austin
    Proceeding of the 30th Annual Symposium on Microarchitecure, Dec 1997.

  • On High-Bandwidth Data Cache Design for Multi-Issue Processors (77,677 bytes) Postscript
    Jude A. Rivers, Gary S. Tyson, Edward S. Davidson and Todd M. Austin
    Proceeding of the 30th Annual Symposium on Microarchitecure, Dec 1997.

  • Limited Dual Path Execution (77,677 bytes) Postscript
    Gary Tyson, Kelsey Lick and Matthew Farrens
    The University of Michigan, EECS Dept, Technical Report #CSE-TR-346-97

  • Managing Data Caches using Selective Cache Line Replacement (69,546 bytes) Postscript
    Gary Tyson, Matthew Farrens, John Matthews and Andrew R. Pleszkun
    International Journal of Parallel Programming, Vol. 25 No. 3, pg 213-242, June 1997.

  • Evaluating the Effects of Predicated Execution on Branch Prediction (58,895 bytes) Postscript
    Gary Tyson and Matthew Farrens
    International Journal of Parallel Programming, Vol. 24 No. 2, 1996.

  • A Modified Approach to Cache Management" (55,393 bytes) Postscript
    Gary Tyson, Matthew Farrens, John Matthews and Andrew R. Pleszkun
    Proceeding of the 28th Annual Symposium on Microarchitecure, Nov 28 - Dec 1, 1995.

  • The Effects of Predicated Execution on Branch Prediction" (58,526 bytes) Postscript
    Gary Scott Tyson
    Proceeding of the 27th Annual Symposium on Microarchitecure, Nov 30 - Dec 2, 1994.

  • Code Scheduling for Multiple Instruction Stream Architectures (66142 bytes) Postscript
    Gary Tyson and Matthew Farrens
    International Journal of Parallel Programming, Vol. 22 No. 3, 1994.

  • A Study of Single-Chip Processor/Cache Organizations (50,623 bytes) Postscript
    Matthew Farrens, Gary Tyson and Andrew R. Pleszkun
    Proceeding of the 21st Annual Symposium on Computer Architecture, Apr. 18-21, 1994

  • Techniques for Extracting Instruction Level Parallelism on MIMD Machines (50,054 bytes) Postscript
    Gary Tyson and Matthew Farrens
    Proceeding of the 26th Annual Symposium on Microarchitecure, Dec. 1-3, 1993.

  • An Interactive Compiler Development System (16,999 bytes) Postscript
    Gary S. Tyson, Robert J. Shaw and Matthew K. Farrens
    First Tcl/Tk Workshop, June 10-11, 1993.

  • Modifying VM Hardware to Reduce Address Pin Requirements (unavailable)
    Matthew Farrens, Arvin Park and Gary Tyson
    Proceeding of the 25th Annual Symposium on Microarchitecure, Dec. 1-4, 1992.

  • MISC: A Multiple Instruction Stream Computer (44,927 bytes) Postscript
    Gary Tyson, Matthew Farrens and Andrew R. Pleszkun
    Proceeding of the 25th Annual Symposium on Microarchitecure, Dec. 1-4, 1992.

  • A Partitioned TLB Approach to Reduced Address Bandwidth (39,604 bytes) Postscript
    Matthew Farrens, Arvin Park, Rob Fanfelle, Pius Ng and Gary Tyson
    Proceeding of the 19th Annual Symposium on Computer Architecture, May 19-21, 1992

    My Dissertation

  • Dissertation: Evaluation of a Scalable Decoupled Microprocessor Design (210,745 bytes) Postscript

    Student Theses and Dissertations

  • Ed Tam's Dissertation: Improving Cache Performance Via Active Management (1999) (264,773 bytes)

  • Jude Rivers' Dissertation: Perforrmance Aspects of High-Bandwidth Multi-Lateral Cache Organizations (1998) (unavailable)

  • Kelsey Lick's Thesis: Hybrid Branch Prediction Using Limited Dual Path Execution (1996) (519,640 bytes)

  • Brian Harvey's Thesis: Graphical User Interface for Compiler Optimizations with Simple-SUIF (1996) (608,919 bytes)

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    1/20/95