A digital image can be thought of as a matrix of numbers. A simple example of a digital image is shown in Figure 2. One possible digital representation of that scene is shown on the right.
Figure 2: Digital Image Example
Each element of the digital image is referred to as a picture element, or pixel. In Figure 2 a single bit is used to represent intensity within the sampled position. The white ball has an intensity represented by a one, and the black screen is represented by an intensity of zero in the digital image. As a convention in this paper, a digital intensity of one represents white in a black and white image.
FG-100-V image processor (or frame grabber) has a feedback processing mechanism to deal with an image. The mechanism includes the MUX (multiplexer), the feedback/input LUT (Look-Up Table), and the frame memory, which is accessed for display or additional computer processing. The manual of the FG-100-V () explains the mechanism as follows.
`` A multiplexer allows the frame grabber to operate in several feedback processing modes. There are seven selectable digital feedback modes, numbered 0 to 6. Each mode is optimized to perform a different type of image processing or graphics function. The multiplexer has 24 input bits: twelve frame memory bits MEM(11-0), the digitized video input signal from the analog/digital converter A/D(7-0), and four LUT Control Register bits ILUT(4-0). The twelve of these bits are passed to the feedback/input LUT for the processing before storage in frame memory. This fully-programmable LUT is used as a single 4096x12-bit LUT. Each LUT consists of 4096 8-bit values. However, each is mapped in the address space as 4096 16-bit values; only the low order byte of each word written to LUTs is stored.''
The way the LUT operates is explained in Section 3, in detail.
Figure 3: Feedback Processing
``The frame memory is organized as a two-dimensional array of pixels and stores one or more frames of video information. In normal feedback processing mode, the image processor simultaneously acquires and displays an image using read/modify/write cycles (scan cycle) for every memory cycle. The pixel read is transmitted to the feedback circuitry and display interface and converted to an analog signal while a new pixel, derived from the MUX inputs, is written to memory at the same location.''
The feedback processing mechanism is illustrated in Figure 3 ().
An analog video signal with a frame time of one-thirtieth of a second constitutes a high data rate signal. The FG-100-V converts each frame into a 512x480 8 bit/pixel image every 1/30 second. It also provides lower resolution, such as 256x240, 128x120, and 64x60 images. The number of pixels that are transferred to or from frame memory in one frame time defines the display resolution (number of pixels that are displayed) of the frame memory. The resolution of the FG-100-V is altered through a process called pixel replication. Creating different zoom factors of 1(512x512), 2(256x256), 3(128x128) and 4(64x64) are available. The FG-100-V outputs a 512 by 480 image and replicates pixels in a frame to make it fit that resloution. For example for expanding a 64x64 pixel window, each pixel is repeated (replicated) 8 times to produce a zoom factor of eight.
Figure 4: Zoom Factor of Two