§  address: Florida State University, A211-W Academic Center, Panama City, FL 32405

§   phone: 850-770-2236

§   email: gangryunguh@gmail.com

§   web:   http://www.cs.fsu.edu/~uh

·       Top 10 Algorithms (python/C/C++/java)

(under)

Florida State University

·       Introduction to Compiler Writing (C/C++)

(under)

Florida State University

·       Programming Languages (C/C++)

(under)

Florida State University

·       Operating Systems (C)

(under)

Florida State University

·       Computer Organization I (C/C++)

(under)

Florida State University

·       Computer Organization II (C/C++)

(under)

Florida State University

·       Massively Parallel Computing (OpenMP/MPI/CUDA)

(under/grad)

Boise State University

·       Advanced Topics in Compilation (LLVM)

(under/grad)

Boise State University

·       Computer Architecture (C/C++)

(under/grad)

Boise State University

·       Introduction to CS I and II (Java)

(under)

Boise State University

·       Embedded Systems Design (C)

(under)

Boise State University

·       2022 – 2026

Vectorized Instruction Space (VIS), Detailed Project Description , NSF grant CCF-2211354

·       2020 - 2024

Statically Controlled Asynchronous Lane Execution (SCALE), NSF grant CCF-1901005

·       2021 – present

Teaching professor II at Florida State University Computer Science of Online Distance Learning Program

·       2017 – 2021

Teaching professor I at Florida State University Computer Science of Online Distance Learning Program

·       2015 – 2016

Senior Staff Engineer at Qualcomm:  LLVM based code generation for GPU

·       2008 – 2015

Tenured Associate Professor, Computer Science Department, Boise State University

·       2010 – 2011

Research Associate (sabbatical) for the NSF grant CNS-0964413

·       2002 – 2008

Assistant Professor, Computer Science Department, Boise State University

·       2006 and 2007

Consultant, Intel System Software Lab, Hillsboro and Consultant, Intel Performance, Analysis and Threading Lab, Champaign, USA

·       1998 - 2002

Member of Technical Staff, Agere/Lucent Technology, USA

1.     I. Finlayson, Gang-Ryung Uh, D. Whalley and G. Tyson.  “An Overview of Static Pipelining,” IEEE Computer Architecture Letter (CAL), ISSN:1556-6056, Volume 11, No.  1, Jan 2012.  The paper was selected as the BEST paper and presented during the 19th IEEE International Symposium on HPCA.

2.     Gang-Ryung Uh, Yuhong Wang, David Whalley, and et al. “Compiler Transformations for Effectively Exploiting a Zero Overhead Loop Buffer,” In the journal of Software Practice & Experience, Volume 35, pages 393-412, 2005.

3.     W. Kreahling, D. Whalley, M. Bailey, X. Yuan, Gang-Ryung Uh, R. Van. “Branch Elimination via Multi- Variable Condition Merging,” In the journal of Software Practice & Experience, Volume 35, pages 51-74, 2005.

4.     Jinhwan Kim, Yunheung Paek, Gang-Ryung Uh. “Code Optimization for a VLIW-style network process- ing unit,” In the journal of Software Practice & Experience, Volume 34, pages 847-874, 2004.

5.     Minghui Yang, Gang-Ryung Uh, David Whalley. “Efficient and Effective Branch Reordering Using Profile Data,” In ACM Transactions on Programming Languages and Systems (TOPLAS), Volume 26, Number 6, pages 667-697, 2002.

6.      Gang-Ryung Uh and David Whalley. “Effectively Exploiting Indirect Jumps,”

In the journal of Software Practice & Experience, December 1999, pages 1061-1101.

7.  A. Mortensen, S. Pomerville, D. Whalley, S. Onder, and Gang-Ryung Uh. “Facilitating the Bootstrapping of a New ISA,” In the Proceedings of the 24^th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, June 2023, Pages 2-12, Orlando, FL. https://doi.org/10.1145/35896282.

8.  B. Davis, P. Gavin, R. Baird, P. Gavin, M. Sjalander, I. Finlayson, F. Rasapour, G. Cook, Gang-Ryung Uh, and David Whalley. “Scheduling Instruction Effects for a Statically Pipelined Processor” will be appeared in the proceeding of ACM International Conference on Compilers, Architectures and Synthesis of Embedded Systems, October Amsterdam, Netherlands.

9.     R. Baird, P. Gavin, M. Sjalander, Gang-Ryung Uh, and David Whalley. “Optimizing Transfers of Control in the Static Pipeline Architecture”. Will be appeared in the proceeding of ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES), June 2015, Portland, OR.

10.  K. Schwab, J. Law, G. Cook, K. Hoff and Gang-Ryung Uh.  “SAVE: Self-organizing Air VEntilation system,” In the proceeding of UKC 2013, New York/New Jersey, August 2013.  This work is selected one of 10 finalists for the Business Venture Challenge (BVC) competition program and will be presented during the conference for $10,000 cash award competition.

11.  I. Finlayson, B. Davis, P. Gavin, Gang-Ryung Uh, D. Whalley, M. Sjalander and G. Tyson. “Improving Processor Efficiency by Statically Pipelining Instructions,” In the proceeding of ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES), June 2013, Seattle, WA.

12.  Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, and Yunheung Paek. “Preprocessing Strategy for Effective Modulo Scheduling on Multi-Issue Digital Signal Processors,” In the Proceedings of the 16th International Conference on Compiler Construction, March 2007, Braga, Portugal.

13.  Wankang Zhao, Prasad Kullkarni, David Whalley, Christopher Healy, Frank Mueller, Gang Ryung Uh. “Tuning WCET of Embedded System,” In the Proceedings of IEEE 10th  Real-Time and Embedded Technology and Applications Symposium, May 2004, Toronto, Canada.

14.  W. Kreahling, D. Whalley, M. Bailey, X. Yuan, Gang-Ryung Uh, R. Van. “Branch Elimination via Multi- Variable Condition Merging,” In the Proceedings of European Conference on Parallel and Distributed Computing (EuroPar03), August 26-29, 2003, Klagenfurt, Austria.

15.  J. Kim, S. Jung, Y. Paek, and Gang-Ryung Uh. “Experience with a Retargetable Compiler for a Com- mercial Network Processor,” In the Proceedings of the 2002 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, 2002, Grenoble, France.

16.  Gang-Ryung Uh, Yuhong Wang, David Whalley, and et al “Techniques for Effectively Exploiting a Zero Overhead Loop Buffer,” In the Proceedings of the 9th International Conference on Compiler Construction (CC’2000), pages 157-172, March 2000, Berlin, Germany.

17.  Minghui Yang, Gang-Ryung Uh, David Whalley.  “Improving Performance by Branch Reordering,” In the Proceedings of ACM SIGPLAN Conference on Programming Language Design and Implementation, pages 130-141, June 1998, Montreal, Canada.

18.  Gang-Ryung Uh, David Whalley.  “Coalescing Conditional Branches into Efficient Indirect Jumps,” In the proceedings of International Static Analysis Symposium, pages 315-329, September 1997, Paris, France.

19.  Gang-Ryung Uh, Daniel Schwartz. Predicting Consumer Expenditure Behavior with Neural Nets,” In the Proceedings of IEEE’93 World Congress on Neural Networks.

20. R. Baird, B. Davis, Gang-Ryung Uh, and D. Whalley.  “Open Source LLVM-VPO Compiler,”, 2013 European LLVM Conference, April 2013, Paris, France.

21.  I. Finlayson, Gang-Ryung Uh, D. Whalley and G. Tyson. “Improving Low Power Processor Efficiency with Static Pipelining,” In the proceeding of 15th Workshop on Interaction between Compilers and Computer Architectures (INTERACT), Feburary 2011, San Antonio, TX.

22.  Gang-Ryung Uh, Robert Cohn, Bharadwaj Yadavalli, Ramesh Peri, and Ravi Ayyagari. “Analyzing Dynamic Binary Instrumentation Overhead,” In the Proceedings of the Workshop on Binary Instrumentation and Applications, October, 2006, San Jose, USA: appeared in the ACM SIGARCH Computer Architecture News, ISSN:0163-5964.

23.  Gang-Ryung Uh.   “Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer,” In the Proceedings of the 7th  International Workshop on Software and Compilers for Embed- ded Systems (SCOPES 2003), September 24-26, 2003, Vienna, Austria: published in Lecture Notes in Computer Science (LNCS), ISSN:0302-9743.

24.  Gang-Ryung Uh, Yuhong Wang, David Whalley, and et al., “Effective Exploitation of a Zero Overhead Loop Buffer,” In the Proceedings of ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, pages 10-19, May 1999, Atlanta, USA: published in ACM SIGPLAN Notices, Volume 34, Issue 7, ISBN:1-58113-136-4.

25.  Indoor Natural Lighting - Smart Lighting LED Control

https://www.youtube.com/watch?v=bs_ZPmuGkFQ

26.  Intelligent four wheel-differential Rover

            https://www.youtube.com/watch?v=JCvomBUaRpE

27.  Self-Organizing Air VEntilation (SAVE) System

  https://www.youtube.com/watch?v=vd1nXOZA4YM

·       Co-Principal Investigator, Florida State University, National Science Foundation CCF-2211354, Vectorized Instruction Space (VIS), $1,200,000, October 2022 – September 2026.

·      Principal Investigator, Idaho State Board of Education, Higher Education Research Council, Idaho Incubation Fund Program FY 2014 RFP, “SAVE: Enhancement to Self-organizing Air VEntilation system” $50,000, July 2014 – June 2015.

·      Idaho State Board of Education, Higher Education Research Council, Idaho Incubation Fund Program FY 2014 RFP, “SAVE: Self-organizing Air VEntilation system” $45,800, July 2013 – June 2014.

·      Google Faculty Research Award, “Preprocessing for Modulo Scheduling within Open-Source ARM Cortex-A8 Compiler,” $37,400, August 2012 – 2014.

·      Co-Principal Investigator, Korea Evaluation Institute of Industry Technology (KEIT), GrantNO.10041725, “ELFWAND: Building the Service and Software Foundation for Personalized Smart Device Sensor Applications,” $240,000 (for Boise State University), Jun 2012 – May 2015.

·      Principal Investigator, NASA Idaho EPSCoR, “PIN Based Non-Uniform Memory Access (NUMA) Memory Simulator,” $30,000, May 2009 – August 2010.

·      Principal Investigator, INTEL Corporation, “Multi-threaded PIN Simulator Design,” $25,000, Jan 2007– Oct 2011.

·      Principal Investigator, NASA Idaho EPSCoR, “Compiler Optimization for Ultra-Low Power Wireless Sensor Signal Processor,” $8,000, Nov 2005–Nov 2006.

·      Principal Investigator, Brain Pool (Korean Federation of Science and Technology Societies) “Compiler Infrastructure Development,” $20,000, Period: May 2005–Dec 2005.

·      Principal Investigator, NASA Idaho EPSCoR, “Optimizing Compiler Benchmark Infrastructures for Ultra-low Power Embedded Processors,” $60,294.00, Period: Oct 2003–Aug 2004.

·      Principal Investigator, NSF Idaho EPSCoR, “Instruction Selection Sensitive Software Pipelining for Effectively Exploiting Zero Overhead Loop Buffer,” $50,800, Mar 2003–Dec 2003.

·       Program Committee Member, Local Chair, and Session Chair for ACM SIGPLAN/SIGBED Conferences on Languages, Compiles, and Tools for Embedded Systems (LCTES).

·       Reviewers for numerous ACM SIGPLAN/SIGBED and IEEE journals including Transaction on Computers.