Chapter 5: The Processor: Datapath and Control
1: Concepts Introduced in Chapter 5
2: Subset of MIPS Instruction Set
3: Figure 5.1: An abstract view of the implementation of the MIPS subset showing the major functional units and the major connections between them.
4: Logic Elements
5: Types of Signals
6: Figure 5.2: Combinational logic, state elements, and the clock are closely related.
7: Figure 5.3: An edge-triggered methodology allows a state element to be read and written in the same clock cycle without creating a race that could lead to indeterminate data values.
8: Implementing an Instruction Set
9: Figure 5.4: Two state elements are needed to store and access instructions, and an adder is needed to compute the next instruction address.
10: Figure 5.5: A portion of the datapath used for fetching instructions and incrementing the program counter.
11: Figure 5.6: The two elements needed to implement R-format ALU operations are the register file and the ALU.
12: Figure 5.7: The datapath for R-type instructions.
13: Figure 5.8: The two units needed to implement loads and stores, in addition to the register file and ALU of Figure 5.6, are the data memory unit and the sign-extension unit.
14: Figure 5.9: The datapath for a load or store that does a register access, followed by a memory address calculation, then a read or write from memory, and a write into the register file if the instruction is a load.
15: Figure 5.10: The datapath for a branch uses an ALU for evaluation of the branch condition and a separate adder for computing the branch target as the sum of the incremented PC and ...
16: Figure 5.14: How the ALU control bits are set depending on the ALUOp control bits and the different function codes for the R-type instruction.
17: Figure 5.15: The truth table for the three ALU control bits (called Operation).
18: MIPS Instruction Formats
19: Figure 5.18: The effect of each of the seven control signals.
20: Figure 5.20: The setting of the control lines is completely determined by the opcode fields of the instruction.
21: Figure 5.29: The simple control and datapath are extended to handle the jump instruction.
22: Advantages of a Multicycle Implementation
23: Figure 5.34 (top portion): The action caused by the setting of each control signal in Figure 5.33 on page 383.
24: Figure 5.34 (bottom portion): The action caused by the setting of each control signal in Figure 5.33 on page 383.
25: Multicycle Implementation Steps of Execution
26: Figure 5.35: Summary of the steps taken to execute any instruction class.
27: Multicycle Control
28: Finite State Machine for Multicycle Control
29: Figure C.7: The control unit for the MIPS will consist of some control logic and a register to hold the states.
30: Figure C.8: The logic equations for the control unit shown in a shorthand form.
31: Microprogramming for Multicycle Control
32: Exceptions and Interrupts
33: Figure 5.48: The multicycle datapath with the addition needed to implement exceptions.
34: Figure 5.50: This shows the finite state machine with the additions to handle exception detection.
35: Fallacies and Pitfalls
