module half_adder (A,B,Sum,Carry);
	input A,B; 
	output Sum, Carry; 

	assign Sum = A ^ B; 
	assign Carry = A & B; 
endmodule


module two_one_Selector (A,B,Sel,O);
	input A,B,Sel; 
  output O;
  
  assign O = (~Sel & A) | (Sel & B);

/*
	output reg O; 
	always @(A, B, Sel)
		case (Sel) 
			0: O <= A;
			1: O <= B;
			default: O<=A;
	endcase
*/

/*
	output reg O; 
	always @(A, B, Sel)
		if (Sel == 1'b0)
			O <= A;
		else
			O <= B;	
*/		
endmodule


module comparator5 (I,O);
input [2:0] I; 
/*
output reg O; 

	always @(I)
		if (I < 3'd5)
			O <= 1'b0 ;
		else
			O <= 1'b1;	
*/
  output O; 
	assign O = (I[2]&I[1]) | (I[2]&I[0]); 

endmodule



module full_adder (A,B,Cin,Sum, Cout);
	input A,B,Cin; 
	output Sum, Cout; 

	assign Sum = (A & B & Cin) | (~A & ~B & Cin) | (~A & B & ~Cin) | (A & ~B & ~Cin); 
	assign Cout = (A & Cin) | (A & B) | (B & Cin);	

endmodule



module four_bit_adder (A,B,Cin,Sum, Cout);
	input [3:0] A;
	input [3:0] B;
	input Cin; 
	output [3:0] Sum;
	output Cout; 

	wire C0, C1, C2;

	full_adder FA1(A[0], B[0], Cin, Sum[0], C0);
	full_adder FA2(A[1], B[1], C0, Sum[1], C1);
	full_adder FA3(A[2], B[2], C1, Sum[2], C2);
	full_adder FA4(A[3], B[3], C2, Sum[3], Cout);

endmodule


module MIPSALU (ALUctl, A, B, ALUOut, Zero);
input [3:0] ALUctl;
input [31:0] A,B;
output reg [31:0] ALUOut;
output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
always @(ALUctl, A, B) //reevaluate if these change
case (ALUctl)
0: ALUOut <= A & B;
1: ALUOut <= A | B;
2: ALUOut <= A + B;
6: ALUOut <= A - B;
7: ALUOut <= A < B ? 1:0;
12: ALUOut <= ~(A | B); // result is nor
default: ALUOut <= 0; //default to 0, should not happen;
endcase
endmodule


module downcounter (clr, clk, OC);
	input clr, clk; 
	output reg [2:0] OC; 

	initial begin
		OC = 0;
	end

	always @(posedge clk) begin
		if (clr == 0)
			OC = 0;
		else 
			OC = OC - 1;
	end

endmodule


module counter (clr, clk, OC);
	input clr, clk; 
	output reg [2:0] OC; 

	initial begin
		OC = 0;
	end

	always @(posedge clk) begin
		if (clr == 0)
			OC = 0;
		else 
			OC = OC + 1;
	end

endmodule


module counter4bit (clr, clk, OC);
	input clr, clk; 
	output reg [3:0] OC; 

	initial begin
		OC = 0;
	end

	always @(posedge clk) begin
		if (clr == 0)
			OC = 0;
		else 
			OC = OC + 1;
	end

endmodule


module test_bench ();

reg osc;

initial begin
osc = 0;
end

always begin
#10 osc = ~osc;
end

wire clr, clk;
assign clr=1;
assign clk=osc; 

/*
wire A,B,S,C;
assign A=0;
assign B=1;
half_adder A1(A, B, S, C);
*/

/*
wire A,B,Sel,O;
assign A=1;
assign B=0;
assign Sel=osc;
two_one_Selector S1(A,B,Sel,O);
*/

/*
wire [2:0] counterO;
wire FASum, FACout;
full_adder FA1(counterO[2], counterO[1], counterO[0], FASum, FACout);
counter C1(clr, clk, counterO);
*/

/*
wire CMCout;
comparator5 CM1(counterO, CMCout);
*/


wire [3:0] c4bitO0;
wire [3:0] AdderSum;
wire AdderCout;
counter4bit C4bit0(clr, clk, c4bitO0);
four_bit_adder Adder(c4bitO0, 4'b1010, 1'b0, AdderSum, AdderCout);


/*
wire [3:0] ALUctl;
wire [31:0] ALUA, ALUB;
wire [31:0] ALUOut;
wire ALUZero;

assign ALUA = 32'd12;
assign ALUB = 32'd25;
counter4bit C4bitALUctl(clr, clk, ALUctl);

MIPSALU ALU(ALUctl, ALUA, ALUB,ALUOut,ALUZero);
*/


endmodule