The performance of cache coherence protocols depends heavily on the workload.
Consider an SMP system whose workload exhibits the migratory memory access
pattern: a shared memory is usually accessed (read and write) multiple times 
exclusively by one processor for a period time, after that another processor
would exclusively access the memory for a period of time, and then 
another processor will do the same thing, and so on. Design a new cache
coherence protocol that is similar to the MSI protocol discussed in the class,
but provides better performance in terms of minimizing the bus activity for 
the system. Draw the finite state machine for your protocol. Briefly justify
why your protocol is better than MSI for the migratory memory access 
pattern.