GANG-RYUNG UH, Ph.D.

CURRICULUM VITAE

 

Š       Contact Information

 

o   Gang-Ryung Uh, Ph.D

 address: A211-W Academic Center / Panama City Campus

 phone: 850-770-2236

 email: gangryunguh@gmail.com

 web:   http://www.cs.fsu.edu/~uh

 

Š       A complete listing of all higher education experience and degrees, and of academic honors including memberships, awards, grants, and fellowships:

 

o   Higher Education:

1997

Ph.D

Major: Computer Science. Florida State University, Tallahassee, Florida

 

 

Dissertation: “Effectively Exploiting Indirect Jumps”

1993

M.S.

Major:  Computer Science.  Florida State University, Tallahassee, Florida

 

 

Thesis: “Predicting Consumer Expenditure Behavior with Neural Nets”

1987

B.A.

Major: Economics. Hankuk University of Foreign Studies, Korea.

 

 

 

o   Membership:

                Association for Computing Machinery (ACM)

 

Š       List of Courses developed and taught

1.     Programming Languages (C/C++)

(under)

Florida State University

2.     Operating Systems (C)

(under)

Florida State University

3.     Computer Organization I (C/C++)

(under)

Florida State University

4.     Computer Organization II (C/C++)

(under)

Florida State University

5.     Computer Architecture (C/C++)

(under/grad)

Boise State University

6.     Massively Parallel Computing

(under/grad)

Boise State University

7.     Advanced Topics in Compilation (LLVM)

(under/grad)

Boise State University

8.     Introduction to CS I (Java)

(under)

Boise State University

9.     Introduction to CS II (Java)

(under)

Boise State University

10.  Embedded Systems Design (C)

(under)

Boise State University

11.  Compiler (C)

(under)

Boise State University

 

Š       A comprehensive list of your employment since completion of your terminal degree

o   2017 –                   Teaching professor at Florida State University Computer Science for

                                     Online Distance Learning Program

o   2015 2017           Senior Staff Engineer at Qualcomm, USA - LLVM based code generation for GPU

o   2014                         Consultant, Micron, Boise

o   2008 2015          Tenured Associate Professor, Computer Science Department, Boise State University.

o   2010 – 2011          Research Associate (sabbatical) for the NSF grant CNS-0964413,

             Static Pipelining, an Approach for Ultra-low Power Embedded Processors,

             Dept. of Computer Science, Florida State University, Tallahassee, FL.

o   2002 2008          Assistant Professor, Computer Science Department, Boise State University.

o   2007                      Consultant, Intel Performance, Analysis and Threading Lab, Champaign, USA.

o   2006                      Consultant, Intel System Software Lab, Hillsboro

o   2005                      Research Faculty, Seoul National University, Korea

o   2000 2002          Research Scientist, Agere Systems, USA

o   1998 2000          Research Scientist, Lucent Technology, USA

o   1990 –1997           Research/Teaching Assistant, Department of Computer Science

                              Florida State University, Tallahassee


 

Š       A listing of your publications, creative works, performances, and other indices of accomplishment in your field:

 

o   Publications

 

             Refereed Journals

 

1. I. Finlayson, Gang-Ryung Uh, D. Whalley and G. Tyson.  “An Overview of Static Pipelining, IEEE Computer Architecture Letter (CAL), ISSN:1556-6056, Volume 11, No.  1, Jan 2012.  The paper was selected as the BEST paper and presented during the 19th IEEE International Symposium on HPCA.

 

2. Gang-Ryung Uh, Yuhong Wang, David Whalley, and et al. ”Compiler Transformations for Effectively Exploiting a Zero Overhead Loop Buffer, In the journal of Software Practice & Experience, Volume 35, pages 393-412, 2005.

 

3. W. Kreahling, D. Whalley, M. Bailey, X. Yuan, Gang-Ryung Uh, R. Van. ”Branch Elimination via Multi- Variable Condition Merging, In the journal of Software Practice & Experience, Volume 35, pages 51-74, 2005.

 

4. Jinhwan Kim, Yunheung Paek, Gang-Ryung Uh. “Code Optimization for a VLIW-style network process- ing unit, In the journal of Software Practice & Experience, Volume 34, pages 847-874, 2004.

5. Minghui Yang, Gang-Ryung Uh, David Whalley.  ”Efficient and Effective Branch Reordering Using Profile Data, In ACM Transactions on Programming Languages and Systems (TOPLAS),Volume 26, Number 6, pages 667-697, 2002.

6. Gang-Ryung Uh and David Whalley. “Effectively Exploiting Indirect Jumps, In the journal of Software Practice & Experience, December 1999, pages 1061-1101.

 

   Refereed Conferences

 

1.       B. Davis, P. Gavin, R. Baird, P. Gavin, M. Sjalander, I. Finlayson, F. Rasapour, G. Cook, Gang-Ryung Uh, and David Whalley. “Scheduling Instruction Effects for a Statically Pipelined Processor” will be appeared in the proceeding of ACM International Conference on Compilers, Architectures and Synthesis of Embedded Systems, October Amsterdam, Netherlands.

 

2.  R. Baird, P. Gavin, M. Sjalander, Gang-Ryung Uh, and David Whalley. “Optimizing Transfers of Control in the Static Pipeline Architecture”. Will be appeared in the proceeding of ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES), June 2015, Portland, OR.

 

3. K. Schwab, J. Law, G. Cook, K. Hoff and Gang-Ryung Uh.  ”SAVE: Self-organizing Air VEntilation system, In the proceeding of UKC 2013, New York/New Jersey, August, 2013.  This work is selected one of 10 finalists for the Business Venture Challenge (BVC) competition program and will be presented during the conference for $10,000 cash award competition.

 

4. I. Finlayson, B. Davis, P. Gavin, Gang-Ryung Uh, D. Whalley, M. Sjalander and G. Tyson. ”Improving Processor Efficiency by Statically Pipelining Instructions,In the proceeding of ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES), June 2013, Seattle, WA.

 

5.  Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, and Yunheung Paek. ”Preprocessing Strategy for Effective Modulo Scheduling on Multi-Issue Digital Signal Processors, In the Proceedings of the 16th International Conference on Compiler Construction, March, 2007, Braga, Portugal.

 

6.     Wankang Zhao, Prasad Kullkarni, David Whalley, Christopher Healy, Frank Mueller, Gang Ryung Uh. Tuning WCET of Embedded System, In the Proceedings of IEEE 10th  Real-Time and Embedded Tech- nology and Applications Symposium, May 2004, Toronto, Canada.

7. W. Kreahling, D. Whalley, M. Bailey, X. Yuan, Gang-Ryung Uh, R. Van. ”Branch Elimination via Multi- Variable Condition Merging, In the Proceedings of European Conference on Parallel and Distributed Computing (EuroPar03), August 26-29, 2003, Klagenfurt, Austria.

 

8. J. Kim, S. Jung, Y. Paek, and Gang-Ryung Uh. ”Experience with a Retargetable Compiler for a Com- mercial Network Processor, In the Proceedings of the 2002 International Conference on Compilers, Ar- chitecture and Synthesis for Embedded Systems, 2002, Grenoble, France.

 

9. Gang-Ryung Uh, Yuhong Wang, David Whalley, and et al. Techniques for Effectively Exploiting a Zero Overhead Loop Buffer, In the Proceedings of the 9th International Conference on Compiler Construction (CC’2000), pages 157-172, March 2000, Berlin, Germany.

 

10. Minghui Yang, Gang-Ryung Uh, David Whalley. ”Improving Performance by Branch Reordering, In the Proceedings of ACM SIGPLAN Conference on Programming Language Design and Implementation, pages 130-141, June 1998, Montreal, Canada.

 

11. Gang-Ryung Uh, David Whalley.  ”Coalescing Conditional Branches into Efficient Indirect Jumps,In the proceedings of International Static Analysis Symposium, pages 315-329, September 1997, Paris, France.

 

  12. Gang-Ryung Uh, Daniel Schwartz. Predicting Consumer Expenditure Behavior with Neural Nets, In the Proceedings of IEEE’93 World Congress on Neural Networks.

 

           Refereed Workshops

 

1.   R. Baird, B. Davis, Gang-Ryung Uh, and D. Whalley.  ”Open Source LLVM-VPO Compiler,,

2013 European LLVM Conference, April 2013, Paris, France.

 

2. I. Finlayson, Gang-Ryung Uh, D. Whalley and G. Tyson. ”Improving Low Power Processor Efficiency with Static Pipelining, In the proceeding of 15th Workshop on Interaction between Compilers and Com- puter Architectures (INTERACT), Feburary, 2011, San Antonio, TX.

 

3. Gang-Ryung Uh, Robert Cohn, Bharadwaj Yadavalli, Ramesh Peri, and Ravi Ayyagari. “Analyzing Dy- namic Binary Instrumentation Overhead, In the Proceedings of the Workshop on Binary Instrumentation and Applications, October, 2006, San Jose, USA: appeared in the ACM SIGARCH Computer Architecture News, ISSN:0163-5964.

 

4. Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, and Yunheung Paek.  ”Instruction Re-selection for It- erative Modulo Scheduling on High Performance Multi-issue DSPs, In the Proceeding of the 1st In- ternational Workshop on Embedded Software Optimization, August, 2006, Seoul, Korea: published in Lecture Notes in Computer Science (LNCS), ISSN:0302-9743.

 

5. Gang-Ryung Uh.   Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer, In the Proceedings of the 7th  International Workshop on Software and Compilers for Embed- ded Systems (SCOPES 2003), September 24-26, 2003, Vienna, Austria: published in Lecture Notes in Computer Science (LNCS), ISSN:0302-9743.

 

6.     Gang-Ryung Uh, Yuhong Wang, David Whalley, and et al. ”Effective Exploitation of a Zero Overhead Loop Buffer, In the Proceedings of ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, pages 10-19, May 1999, Atlanta, USA: published in ACM SIGPLAN Notices, Volume 34, Issue 7, ISBN:1-58113-136-4.

 

Patent

 

1.     Gang-Ryung Uh, Doosan Cho, and et. al.Effective Modulo Scheduling for Multi-issue High Performance Digital Signal Processor” is filed January 2006.

 

2.     Gang-Ryung Uh, David Whalley, and et. al. “Compiler Optimization for Exploiting Zero Overhead Loop Mechanism”, Inventor Number: 2083757, Patent Number: 6367071, Approval Date: April 2, 2002.

 

Š       Creative works and performance

 

1.     Indoor Natural Lighting - Smart Lighting LED Control

https://www.youtube.com/watch?v=bs_ZPmuGkFQ

2.     Intelligent four wheel-differential Rover

      https://www.youtube.com/watch?v=JCvomBUaRpE

3.     Self-Organizing Air VEntilation (SAVE) System

 

https://www.youtube.com/watch?v=vd1nXOZA4YM

 

4.     PIN shared address space cache simulator

5.     Improving Machine Code Generation Quality by Interfacing VPO with LLVM

http://www.cs.fsu.edu/~uh/research.html

 

Š       Other indices of accomplishment in my field: Invited Talks/Presentations

 

1. “Improving Processor Efficiency by Statically Pipelining Instructions’, KOCSEA Technical Symposium, Atlanta, Georgia, 2012.

 

2. “LLVM-VPO Compiler Infrastructure for a Low Power Embedded Processor, Seoul National University, Seoul, Korea, 2012.

 

3. “Overview of Statically Pipelined Processor, ETRI, DaeChun Korea, 2012.

 

4. “Compiler Optimization Strategies for Mobile Processors, ETRI and Monuel ELFWAND Project Workshop, DaeChun, Korea, 2012.

 

5. “Architecture and Compiler Techniques to Improve Processor Energy Efficiency, Samsung System-On-Chip (SOC), Seoul, Korea, 2012.

 

6.           “PIN - Dynamic Binary Instrumentation”, NASA Advanced Supercomputing Division, Ames, CA,  

USA, 2006.

 

7. StarCore VLES SC1400 DSP and Compiler Optimization, Samsung Electronics, Seoul, Korea,

       2005.

 

8. “Effective Modulo Scheduling for VLES SC1400 DSP, Seoul National University, Seoul, Korea,

       2005.

 

9. “Compiler Optimization Strategy to Reduce Power without Degrading Performance, NASA

     Advanced Supercomputing Division, NASA Ames, CA, USA, 2004.

 

10. “Compiler Optimization Strategy to Reduce Power without Degrading Performance”, Agere Systems, Allentown, PA, USA, 2004.

 

11. Tailoring Software Pipelining for Effective Exploitation of Zero Overhead loop buffer, SCOPES,   Vienne, Austria, 2003.

 

Š      Funding

 

1.     Principle Investigator, Idaho State Board of Education, Higher Education Research Council, Idaho Incubation Fund Program FY 2014 RFP, “SAVE: Enhancement to Self-organizing Air VEntilation system” $50,000, July 2014 – June 2015.

2.     Idaho State Board of Education, Higher Education Research Council, Idaho Incubation Fund Program FY 2014 RFP, “SAVE: Self-organizing Air VEntilation system” $45,800, July 2013 – June 2014.

3.     Google Faculty Research Award,Preprocessing for Modulo Scheduling within Open-Source ARM Cortex-A8 Compiler,” $37,400, August 2012 –.

4.    Co-Principle Investigator, Korea Evaluation Institute of Industry Technology(KEIT), GrantNO.10041725, “ELFWAND: Building the Service and Software Foundation for Personalized Smart Device Sensor Applications,” $240,000 (for Boise State University), Jun 2012 – May 2015. _

5.     Co-Principle Investigator, Korea Small Medium Business Administration, GrantNO.0004537, “Development of Virtual Machine for Smart Sensor Network Access Control-based Platform,” $130,594 (for Boise State University), Jun 2011 – May 2013.

6.     Principle Investigator, NASA Idaho EPSCoR, “PIN Based Non-Uniform Memory Access (NUMA) Memory Simulator,” $30,000, May 2009 – August 2010.

7.     Principle Investigator, INTEL Corporation, “Multi-threaded PIN Simulator Design,” $25,000, Jan 2007– Oct 2011.

8.     Principle Investigator, NASA Idaho EPSCoR, “Compiler Optimization for Ultra-Low Power Wireless Sensor Signal Processor,” $8,000, Nov 2005–Nov 2006.

9.     Principle Investigator, Brain Pool (Korean Federation of Science and Technology Societies) “Compiler Infrastructure Development,” $20,000, Period: May 2005–Dec 2005.

10.  Principle Investigator, NASA Idaho EPSCoR, “Optimizing Compiler Benchmark Infrastructuresfor Ultra-low Power Embedded Processors,” $60,294.00, Period: Oct 2003–Aug 2004.

11.  Principle Investigator, NSF Idaho EPSCoR, “Instruction Selection Sensitive Software Pipelining for Effectively Exploiting Zero Overhead Loop Buffer,” $50,800, Mar 2003–Dec 2003.

12.  Principle Investigator, Dean’s Office, “Automatic Code Generator for Embedded Processors,” $30,000, Jan 2003–.

 

Š      Professional Service

 

1)    2016         Program Committee Member, ACM SIGPLAN/SIGBED Conference on Languages,

Compiles, and Tools for Embedded Systems (LCTES).

2)    2013-2014   Reviewer, IEEE Transaction on Computers

3)    2010-2011   Program Committee Member, Workshop on Interaction between Compilers and Computer Architectures (INTERACT)

4)    2004          Chair of Board of Directors, Idaho Korean Community Association

5)    2002          Reviewer of numerous journal and conference articles, approx. 40.

6)    2005          Local Chair, ACM SIGPLAN/SIGBED 2005 Conference on Languages, Compiles, and

Tools for Embedded Systems (LCTES).

7)    2005          Session Chair, ACM SIGPLAN/SIGBED 2005 Conference on Languages, Compiles, and Tools

for Embedded Systems (LCTES).

8)    2003          Student Poster Session Chair, ACM SIGPLAN/SIGBED Conference on Languages,

Compiles, and Tools for Embedded Systems (LCTES).

9)    2003          Program Committee Member, ACM SIGPLAN/SIGBED Conference on Languages,

Compiles, and Tools for Embedded Systems (LCTES).

10) 2003          Program Committee Member, International Conference on Parallel Processing (ICPP).

11) 2002          Program Committee Member, ACM SIGPLAN/SIGBED Conference on Languages,

Compiles, and Tools for Embedded Systems (LCTES).