Section: ÿ 9:05-9:55AM ÿ 10:10-11:00AM Name: ____________________
Feedback Quiz #3 –
Assembly Programming, Architecture Styles, and Algorithms for Arithmetic
Operations - Solutions
CDA 3100, Computer Organization I, Spring 2007
Department of Computer Science,
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Problem 1 True or false.
[ False] The throughput of a CISC instruction set
architecture is higher than that of a RISC one because it has more powerful
instructions and thus uses fewer instructions for a given task.
Note that the throughput for a given task depends on how many
instructions and how fast on average each instruction is. For a CISC architecture, because instructions are more powerful,
they are also slower.
[ False ] In MIPS, for instruction “add $t1, $t2, $t3”,
overflow happens if the carrying bit for the most significant bit is 1.
Note that the overflow happens when the signs of two operands are the
same but different from the result. The carrying bit for the most significant
bit can be 1 when there is no overflow (for example, when we add a positive
number with a negative number, the carrying it of the most significant bit is 1
but there is no overflow).
[False] The
more addressing modes an instruction set architecture
supports, the better the performance.
The
more addressing modes an instruction set architecture supports, the more complicated
instructions in general and there the slower on average the instructions.
[ True ] The
opcode size is 0 bit for a single instruction set
architecture.
Since there is only one instruction set, there is no need to encode the
instruction.
Problem 2 In
MIPS, suppose that instruction “add $t1, $t2, $t3” at address 0x004000b4 causes
an overflow. Describe how the overflow is handled. Note that the exception
handler in MIPS is at 0x80000180.
Answer: When MIPS
detects an overflow in the “add” instruction, it will be handled as an
exception by saving the current instruction address to EPC and set the PC to
0x80000180. Because of this, the next instruction to be executed will be the
first instruction of the exception handler. Note that the exception handler can
decide to resume the interrupted program by setting the PC to EPC + 4 or it can
abort the interrupted program. In a real computer system, this is handled by
the operating system for the user.
Problem 3 The
following is the MIPS assembly code for a function. Add necessary MIPS
instructions so that the function will work properly regardless what registers are
used by the calling procedure and what registers are used by my_comp. We assume that all the procedures and functions
follow MIPS calling conventions.
Answer: According to
MIPS conventions, a calling program should save all caller-saved registers
while a called program should save all callee-saved registers. The given
program is both a called program (it will be called by another program) and
calling program (it calls my_comp).
At the beginning, it
needs to save all the callee-saved registers on the stack (including $s0, $s1,
$fp, and $ra (jal will change $ra)). At the end,
these registers will be stored by loading them from the stack.
Before it calls my_comp, it needs to save all the caller-saved registers
(including $t0, $t1, $a0, $a1) since my_comp can
change these registers without restoring them. The complete code is given as
follows:
