PPT Slide
Large Page Tables
- One solution: two-level paging.
- Chop the page address into two pages: a master page and a secondary page (example: 10 bits for each; 12 bits for offset).
- Let master page table contain not PTEs, but memory pointers to secondary page tables, which do contain PTEs.
- Assuming the process address requirements are sparse, not all the secondary page tables will be needed, resulting in significant memory savings for page tables.
- Figures 12.13 and 12.14 show two views of two-level paging.
- While the master page table should be in memory, why not page out the secondary tables?
- Notice, though, the cost of an extra memory access; assume that the TLB will alleviate the 2-level costs.