PPT Slide
TLB & Paging Behavior
- One good reason programs get high cache hit rates is due to a program’s address locality in space and time.
- Programs tend to stay in one small address range within a short period of time.
- Useful to analyze a program’s behavior and see how it affects paging performance:
- Assume we are traversing an array that spans many pages.
- Each page is 4 KB in size (1024 4-byte words of the array).
- 1st word of each page will cause a page cache miss.
- Next 1023 words per page will use the already-cached page entries.
- Therefore, 2+1023 (=1025) memory accesses to fetch 1024 words = 1.001 memory cycles per word. Pretty efficient!