/** * struct subwindow - describes a region-of-interest, i.e., * a part of the frame */ struct subwindow { int width, height; int startx, starty; }; /** * struct i2c_regval - this is for the I2C register ioctl */ struct i2c_regval { int reg; /* Register number */ unsigned char val; /* Value to set it to */ }; /** * Compile time options */ #define HRT_HAS_INTERRUPTS /** * Card determination constants */ #define TYPE_OF_CARD_IS_GRAY 0 #define TYPE_OF_CARD_IS_COLOR 1 /** * Interrupt options */ #define HRT_INTERRUPT_ON 0x01 #define HRT_INTERRUPT_OFF 0x00 /** * Card specific constants */ #define HRT_VENDOR_ID 0x0004 #define HRT_DEVICE_ID_GRAY 0x0404 #define HRT_DEVICE_ID_COLOR 0x0408 #define HRT_CONTROL_REG 0x2000 #define HRT_Y_LOW_REG 0x2002 #define HRT_Y_HIGH_REG 0x2003 #define HRT_IRQ_REG 0x2005 /* The unique I2C bus address of the SAA7110 (A/D) device */ #define HRT_AD_DEVICE_ID (128+16+8+4) #define HRT_WIDTH_COLOR 640 #define HRT_WIDTH_GRAY 512 #define HRT_HEIGHT 480 #define HRT_BYTES_PER_PIXEL_GRAY 1 #define HRT_BYTES_PER_PIXEL_COLOR 2 #define HRT_BYTES_PER_LINE_COLOR (HRT_WIDTH_COLOR * HRT_BYTES_PER_PIXEL_COLOR) #define HRT_FRAMESIZE_COLOR (HRT_WIDTH_COLOR * HRT_HEIGHT * HRT_BYTES_PER_PIXEL_COLOR) #define HRT_BYTES_PER_LINE_GRAY (HRT_WIDTH_GRAY * HRT_BYTES_PER_PIXEL_GRAY) #define HRT_FRAMESIZE_GRAY (HRT_WIDTH_GRAY * HRT_HEIGHT * HRT_BYTES_PER_PIXEL_GRAY) /* Number of bytes of the device's memory that we ioremap() */ #define BYTES_NEEDED 0x4000 /* * The commands for freeze, live, etc. */ #define HRT_FIELD_MASK 0x01 #define HRT_LIVE_CMD 0x91 #define HRT_FREEZE_IMM_CMD 0x5B #define HRT_FREEZE_NEXT_CMD 0x99 /* A/D registers */ #define HRT_BRIGHTNESS_REG 0x19 #define HRT_CONTRAST_REG 0x13 #define HRT_VID_TYPE (VID_TYPE_CAPTURE | VID_TYPE_MONOCHROME) /* Maximum number of buffers for streaming */ #define MAX_CAPTURE_BUFFERS 16 /* Private ioctl's */ #define IOC_HRT_SET_I2CREG _IOW('v', BASE_VIDIOCPRIVATE + 30, struct i2c_regval) #define IOC_HRT_GET_I2CREG _IOR('v', BASE_VIDIOCPRIVATE + 31, struct i2c_regval) #define IOC_HRT_SET_WIDTH _IOW('v', BASE_VIDIOCPRIVATE + 32, int) #define IOC_HRT_SET_HEIGHT _IOW('v', BASE_VIDIOCPRIVATE + 33, int) #define IOC_HRT_SET_STARTX _IOW('v', BASE_VIDIOCPRIVATE + 34, int) #define IOC_HRT_SET_STARTY _IOW('v', BASE_VIDIOCPRIVATE + 35, int) #define IOC_HRT_SET_ROI _IOW('v', BASE_VIDIOCPRIVATE + 36, struct subwindow) #define IOC_HRT_GET_ROI _IOR('v', BASE_VIDIOCPRIVATE + 37, struct subwindow) #define IOC_HRT_SET_I2CREGS _IOW('v', BASE_VIDIOCPRIVATE + 38, char *) #define IOC_HRT_ENABLE_SUBFRAME _IO('v', BASE_VIDIOCPRIVATE + 39) #define IOC_HRT_DISABLE_SUBFRAME _IO('v', BASE_VIDIOCPRIVATE + 40) /* Pass this as the offset to mmap() to get direct access to the board's memory */ #define HRT_MAGIC_MMAP_OFFSET (PAGE_SIZE*100) #define IOC_HRT_GET_MAGIC_MMAP_OFFSET _IOW('v', BASE_VIDIOCPRIVATE + 41, int) /* Number of registers on teh board - checked in i2c_init() */ #define HRT_NUMREGS 0x34 #ifdef HAVE_V4L2 /* ************************************************************* */ /* struct stream_buffer */ /* represents a single buffer for streaming */ /* ************************************************************* */ struct stream_buffer { struct v4l2_buffer vidbuf; /* For the V4L ioctl's */ int fields_grabbed; /* Two-bit pair of flags indicating which fields have been grabbed (i.e., 00 = no fields, 11 = both) */ struct list_head node; /* Connection into queues */ int requested; /* Set by REQBUF ioctl */ unsigned char *vaddress; /* This is the pointer to the vmalloc()'d memory into which the actual frame goes */ int vma_refcount; /* Reference count */ }; /* added by Newton Etienne: determines if stream buffer has already been queued */ int stream_buffer_use = 0; #define BUFFER_NOT_QUEUED 0 #define BUFFER_QUEUED 1 /* ************************************************************ */ /* struct stream_buffer_queue */ /* FIFO of stream_buffer structs */ /* ************************************************************ */ struct stream_buffer_queue { struct stream_buffer *streambuf; /* Pointer to node data */ struct list_head head; /* Start of the queue */ rwlock_t lock; /* Lock to protect the queue */ int length; /* How many nodes are on the queue */ }; #endif /* ************************************************************** */ /* ************************************************************** */ /* HRT STRUCT DEFINITION */ /* the main device struct. This represents the card */ /* ************************************************************** */ /* ************************************************************** */ struct hrt { unsigned long physaddr; /* Physical address */ unsigned long virtaddr; /* Virtual address (was ioremapped) */ struct pci_dev *pcidev; /* PCI device */ struct semaphore sem; /* Protective mutex */ unsigned int field_bit; /* Which field (even or odd) is capturing */ wait_queue_head_t waitqueue; /* Wait queue for poll() */ unsigned char regvals[HRT_NUMREGS]; /* Current values of the regs */ unsigned char *framedata; /* The data for a frame for read() */ struct subwindow *win; /* Current region of interest */ unsigned int bytesperline; /* Bytes per raster line */ unsigned int framesize; /* Size of a frame */ unsigned int users; /* Number of processes that have open()'d hrtmem */ unsigned int typeofcard; #ifdef HAVE_V4L2 struct video_device video_dev; int streaming; /* Flag for streaming mode */ int numbufs; /* Number of buffers for streaming */ struct stream_buffer *streambufs; /* Array of buffers */ struct stream_buffer_queue capture_list; /* List of queued buffers */ struct stream_buffer_queue done_list; /* List of filled buffers */ /* Veena and Arthi's streaming */ struct v4l2_format clientfmt; struct v4l2_captureparm capture; int stream_buffers_mapped; struct stream_buffer stream_buf[MAX_CAPTURE_BUFFERS]; int stream_buffers_requested; #endif }; /* ************************************************************** */ /* ************************************************************** */ /* HRT PRINT FUNCTIONS */ /* ************************************************************** */ /* ************************************************************** */ #define dprintk(fmt, arg...) if (debug) \ printk("hrt: " fmt, ## arg) #define hrt_printk(fmt, arg...) printk("hrt: " fmt, ## arg) /** * hrt_addresses - a list of possible jumper-selected addresses * jumper A on = plug and play address (above one MB address) * jumper A off = hardwired to 0xdc000 or 0xd4000 * jumper B on = address 0xd4000 (ignored if jumper A is on) * jumper B off = address 0xdc000 (ignored if jumper A is on) */ const unsigned long hrt_addresses[] = { 0xd4000, 0xdc000 }; /** * saa7110_default_init_regs - the register values used to * initialize the SAA7110 A/D converter. * Because some registers are not set, this is given * as a list of pairs. The first element of each pair * is the register number, and the second number is the * value of the register. The array is terminated by * a double zero-byte. This generalization allows us to reuse * the initialization routine with different tables, * to allow an application to reset any set of device * registers. */ const unsigned char saa7110_default_init_regs[] = { 94, /* there are 94 bytes that follow */ 0x00, 0x4c, /* increment delay (IDEL) */ 0x01, 0x3c, /* HSY begin 50 Hz */ 0x02, 0x0d, /* HSY stop 50 Hz */ 0x03, 0xef, /* HCL begin 50 Hz */ 0x04, 0xbd, /* HCL stop 50 Hz */ 0x05, 0xf0, /* HSY after PHI1 50 Hz */ 0x06, 0x00, /* luminance control */ 0x07, 0x00, /* hue control */ 0x08, 0xf8, /* colour killer threshold QUAM (PAL/NTSC) */ 0x09, 0xf8, /* colour killer threshold SECAM */ 0x0A, 0x60, /* PAL switch sensitivity */ 0x0B, 0x50, /* SECAM switch sensitivity */ 0x0C, 0x00, /* gain control chrominance */ 0x0D, 0x86, /* standard/mode control */ /* 7 VTRC = 1 (VCR mode, not TV) 6 XXX 5 XXX 4 XXX 3 RTSE = 0 (PLIN switched to output) 2 HRMV = 1 (HREF normal position) 1 SSTB = 1 (status byte = 1) 0 SECS = 0 (other standards, not SECAM) */ 0x0E, 0x18, /* I/O and clock control */ 0x0F, 0x90, /* control #1 */ 0x10, 0x00, /* control #2 */ 0x11, 0x2c, /* chrominance gain reference */ 0x12, 0x7f, /* chrominance saturation */ 0x13, 0x5e, /* luminance contrast */ 0x14, 0x42, /* HSY begin 60 Hz */ 0x15, 0x1a, /* HSY stop 60 Hz */ 0x16, 0xff, /* HCL begin 60 Hz */ 0x17, 0xda, /* HCL stop 60 Hz */ 0x18, 0xf0, /* HSY after PHI1 60 Hz */ 0x19, 0x9b, /* luminance brightness */ /* 0x1A - not used 0x1B - not used 0x1C - not used 0x1D - not used 0x1E - not used 0x1F - not used */ 0x20, 0x7c, /* analog control #1 */ 0x21, 0x03, /* analog control #2 */ 0x22, 0xd2, /* mixer control #1 */ 0x23, 0x41, /* clamping level control 21 */ 0x24, 0x80, /* clamping level control 22 */ 0x25, 0x41, /* clamping level control 31 */ 0x26, 0x80, /* clamping level control 32 */ 0x27, 0x4f, /* gain control #1 */ 0x28, 0xfe, /* white peak control */ 0x29, 0x01, /* sync bottom control */ 0x2A, 0xcf, /* gain control analog #2 */ 0x2B, 0x0f, /* gain control analog #3 */ 0x2C, 0x83, /* mixer control #2 */ 0x2D, 0x01, /* integration value gain */ 0x2E, 0x81, /* vertical blanking pulse set */ 0x2F, 0x03, /* vertical blanking pulse reset */ 0x30, 0x60, /* ADCs gain control */ 0x31, 0x71, /* mixer control #3 */ 0x32, 0x02, /* integration value white peak */ 0x33, 0x8c, /* mixer control #4 */ 0x34, 0x03, /* gain update level */ };