1 /*
2 * s3c2443-ac97.c -- ALSA Soc Audio Layer
3 *
4 * (c) 2007 Wolfson Microelectronics PLC.
5 * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
6 *
7 * Copyright (C) 2005, Sean Choi <sh428.choi@samsung.com>
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/wait.h>
21 #include <linux/delay.h>
22 #include <linux/gpio.h>
23 #include <linux/clk.h>
24
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/ac97_codec.h>
28 #include <sound/initval.h>
29 #include <sound/soc.h>
30
31 #include <mach/hardware.h>
32 #include <plat/regs-ac97.h>
33 #include <mach/regs-gpio.h>
34 #include <mach/regs-clock.h>
35 #include <plat/audio.h>
36 #include <asm/dma.h>
37 #include <mach/dma.h>
38
39 #include "s3c24xx-pcm.h"
40 #include "s3c24xx-ac97.h"
41
42 struct s3c24xx_ac97_info {
43 void __iomem *regs;
44 struct clk *ac97_clk;
45 };
46 static struct s3c24xx_ac97_info s3c24xx_ac97;
47
48 static DECLARE_COMPLETION(ac97_completion);
49 static u32 codec_ready;
50 static DECLARE_MUTEX(ac97_mutex);
51
52 static unsigned short s3c2443_ac97_read(struct snd_ac97 *ac97,
53 unsigned short reg)
54 {
55 u32 ac_glbctrl;
56 u32 ac_codec_cmd;
57 u32 stat, addr, data;
58
59 down(&ac97_mutex);
60
61 codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
62 ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
63 ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
64 writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
65
66 udelay(50);
67
68 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
69 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
70 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
71
72 wait_for_completion(&ac97_completion);
73
74 stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT);
75 addr = (stat >> 16) & 0x7f;
76 data = (stat & 0xffff);
77
78 if (addr != reg)
79 printk(KERN_ERR "s3c24xx-ac97: req addr = %02x,"
80 " rep addr = %02x\n", reg, addr);
81
82 up(&ac97_mutex);
83
84 return (unsigned short)data;
85 }
86
87 static void s3c2443_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
88 unsigned short val)
89 {
90 u32 ac_glbctrl;
91 u32 ac_codec_cmd;
92
93 down(&ac97_mutex);
94
95 codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
96 ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
97 ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
98 writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
99
100 udelay(50);
101
102 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
103 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
104 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
105
106 wait_for_completion(&ac97_completion);
107
108 ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
109 ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
110 writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
111
112 up(&ac97_mutex);
113
114 }
115
116 static void s3c2443_ac97_warm_reset(struct snd_ac97 *ac97)
117 {
118 u32 ac_glbctrl;
119
120 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
121 ac_glbctrl = S3C_AC97_GLBCTRL_WARMRESET;
122 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
123 msleep(1);
124
125 ac_glbctrl = 0;
126 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
127 msleep(1);
128 }
129
130 static void s3c2443_ac97_cold_reset(struct snd_ac97 *ac97)
131 {
132 u32 ac_glbctrl;
133
134 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
135 ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
136 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
137 msleep(1);
138
139 ac_glbctrl = 0;
140 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
141 msleep(1);
142
143 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
144 ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
145 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
146 msleep(1);
147
148 ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
149 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
150 msleep(1);
151
152 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA |
153 S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA;
154 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
155 }
156
157 static irqreturn_t s3c2443_ac97_irq(int irq, void *dev_id)
158 {
159 int status;
160 u32 ac_glbctrl;
161
162 status = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT) & codec_ready;
163
164 if (status) {
165 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
166 ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
167 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
168 complete(&ac97_completion);
169 }
170 return IRQ_HANDLED;
171 }
172
173 struct snd_ac97_bus_ops soc_ac97_ops = {
174 .read = s3c2443_ac97_read,
175 .write = s3c2443_ac97_write,
176 .warm_reset = s3c2443_ac97_warm_reset,
177 .reset = s3c2443_ac97_cold_reset,
178 };
179
180 static struct s3c2410_dma_client s3c2443_dma_client_out = {
181 .name = "AC97 PCM Stereo out"
182 };
183
184 static struct s3c2410_dma_client s3c2443_dma_client_in = {
185 .name = "AC97 PCM Stereo in"
186 };
187
188 static struct s3c2410_dma_client s3c2443_dma_client_micin = {
189 .name = "AC97 Mic Mono in"
190 };
191
192 static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_out = {
193 .client = &s3c2443_dma_client_out,
194 .channel = DMACH_PCM_OUT,
195 .dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
196 .dma_size = 4,
197 };
198
199 static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_in = {
200 .client = &s3c2443_dma_client_in,
201 .channel = DMACH_PCM_IN,
202 .dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
203 .dma_size = 4,
204 };
205
206 static struct s3c24xx_pcm_dma_params s3c2443_ac97_mic_mono_in = {
207 .client = &s3c2443_dma_client_micin,
208 .channel = DMACH_MIC_IN,
209 .dma_addr = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
210 .dma_size = 4,
211 };
212
213 static int s3c2443_ac97_probe(struct platform_device *pdev,
214 struct snd_soc_dai *dai)
215 {
216 int ret;
217 u32 ac_glbctrl;
218
219 s3c24xx_ac97.regs = ioremap(S3C2440_PA_AC97, 0x100);
220 if (s3c24xx_ac97.regs == NULL)
221 return -ENXIO;
222
223 s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
224 if (s3c24xx_ac97.ac97_clk == NULL) {
225 printk(KERN_ERR "s3c2443-ac97 failed to get ac97_clock\n");
226 iounmap(s3c24xx_ac97.regs);
227 return -ENODEV;
228 }
229 clk_enable(s3c24xx_ac97.ac97_clk);
230
231 s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2443_GPE0_AC_nRESET);
232 s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2443_GPE1_AC_SYNC);
233 s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2443_GPE2_AC_BITCLK);
234 s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2443_GPE3_AC_SDI);
235 s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2443_GPE4_AC_SDO);
236
237 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
238 ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
239 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
240 msleep(1);
241
242 ac_glbctrl = 0;
243 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
244 msleep(1);
245
246 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
247 ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
248 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
249 msleep(1);
250
251 ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
252 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
253
254 ret = request_irq(IRQ_S3C244x_AC97, s3c2443_ac97_irq,
255 IRQF_DISABLED, "AC97", NULL);
256 if (ret < 0) {
257 printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n");
258 clk_disable(s3c24xx_ac97.ac97_clk);
259 clk_put(s3c24xx_ac97.ac97_clk);
260 iounmap(s3c24xx_ac97.regs);
261 }
262 return ret;
263 }
264
265 static void s3c2443_ac97_remove(struct platform_device *pdev,
266 struct snd_soc_dai *dai)
267 {
268 free_irq(IRQ_S3C244x_AC97, NULL);
269 clk_disable(s3c24xx_ac97.ac97_clk);
270 clk_put(s3c24xx_ac97.ac97_clk);
271 iounmap(s3c24xx_ac97.regs);
272 }
273
274 static int s3c2443_ac97_hw_params(struct snd_pcm_substream *substream,
275 struct snd_pcm_hw_params *params,
276 struct snd_soc_dai *dai)
277 {
278 struct snd_soc_pcm_runtime *rtd = substream->private_data;
279 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
280
281 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
282 cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_out;
283 else
284 cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_in;
285
286 return 0;
287 }
288
289 static int s3c2443_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
290 struct snd_soc_dai *dai)
291 {
292 u32 ac_glbctrl;
293
294 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
295 switch (cmd) {
296 case SNDRV_PCM_TRIGGER_START:
297 case SNDRV_PCM_TRIGGER_RESUME:
298 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
299 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
300 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
301 else
302 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
303 break;
304 case SNDRV_PCM_TRIGGER_STOP:
305 case SNDRV_PCM_TRIGGER_SUSPEND:
306 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
307 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
308 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
309 else
310 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
311 break;
312 }
313 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
314
315 return 0;
316 }
317
318 static int s3c2443_ac97_hw_mic_params(struct snd_pcm_substream *substream,
319 struct snd_pcm_hw_params *params,
320 struct snd_soc_dai *dai)
321 {
322 struct snd_soc_pcm_runtime *rtd = substream->private_data;
323 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
324
325 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
326 return -ENODEV;
327 else
328 cpu_dai->dma_data = &s3c2443_ac97_mic_mono_in;
329
330 return 0;
331 }
332
333 static int s3c2443_ac97_mic_trigger(struct snd_pcm_substream *substream,
334 int cmd, struct snd_soc_dai *dai)
335 {
336 u32 ac_glbctrl;
337
338 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
339 switch (cmd) {
340 case SNDRV_PCM_TRIGGER_START:
341 case SNDRV_PCM_TRIGGER_RESUME:
342 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
343 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
344 break;
345 case SNDRV_PCM_TRIGGER_STOP:
346 case SNDRV_PCM_TRIGGER_SUSPEND:
347 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
348 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
349 }
350 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
351
352 return 0;
353 }
354
355 #define s3c2443_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
356 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
357 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
358
359 static struct snd_soc_dai_ops s3c2443_ac97_dai_ops = {
360 .hw_params = s3c2443_ac97_hw_params,
361 .trigger = s3c2443_ac97_trigger,
362 };
363
364 static struct snd_soc_dai_ops s3c2443_ac97_mic_dai_ops = {
365 .hw_params = s3c2443_ac97_hw_mic_params,
366 .trigger = s3c2443_ac97_mic_trigger,
367 };
368
369 struct snd_soc_dai s3c2443_ac97_dai[] = {
370 {
371 .name = "s3c2443-ac97",
372 .id = 0,
373 .ac97_control = 1,
374 .probe = s3c2443_ac97_probe,
375 .remove = s3c2443_ac97_remove,
376 .playback = {
377 .stream_name = "AC97 Playback",
378 .channels_min = 2,
379 .channels_max = 2,
380 .rates = s3c2443_AC97_RATES,
381 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
382 .capture = {
383 .stream_name = "AC97 Capture",
384 .channels_min = 2,
385 .channels_max = 2,
386 .rates = s3c2443_AC97_RATES,
387 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
388 .ops = &s3c2443_ac97_dai_ops,
389 },
390 {
391 .name = "pxa2xx-ac97-mic",
392 .id = 1,
393 .ac97_control = 1,
394 .capture = {
395 .stream_name = "AC97 Mic Capture",
396 .channels_min = 1,
397 .channels_max = 1,
398 .rates = s3c2443_AC97_RATES,
399 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
400 .ops = &s3c2443_ac97_mic_dai_ops,
401 },
402 };
403 EXPORT_SYMBOL_GPL(s3c2443_ac97_dai);
404 EXPORT_SYMBOL_GPL(soc_ac97_ops);
405
406 static int __init s3c2443_ac97_init(void)
407 {
408 return snd_soc_register_dais(s3c2443_ac97_dai,
409 ARRAY_SIZE(s3c2443_ac97_dai));
410 }
411 module_init(s3c2443_ac97_init);
412
413 static void __exit s3c2443_ac97_exit(void)
414 {
415 snd_soc_unregister_dais(s3c2443_ac97_dai,
416 ARRAY_SIZE(s3c2443_ac97_dai));
417 }
418 module_exit(s3c2443_ac97_exit);
419
420
421 MODULE_AUTHOR("Graeme Gregory");
422 MODULE_DESCRIPTION("AC97 driver for the Samsung s3c2443 chip");
423 MODULE_LICENSE("GPL");
424
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