1 /*
2 * ALSA driver for RME Hammerfall DSP audio interface(s)
3 *
4 * Copyright (c) 2002 Paul Davis
5 * Marcus Andersson
6 * Thomas Charbonnel
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <sound/driver.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/interrupt.h>
28 #include <linux/slab.h>
29 #include <linux/pci.h>
30 #include <linux/firmware.h>
31 #include <linux/moduleparam.h>
32
33 #include <sound/core.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/info.h>
37 #include <sound/asoundef.h>
38 #include <sound/rawmidi.h>
39 #include <sound/hwdep.h>
40 #include <sound/initval.h>
41 #include <sound/hdsp.h>
42
43 #include <asm/byteorder.h>
44 #include <asm/current.h>
45 #include <asm/io.h>
46
47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
49 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
50 static int precise_ptr[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0 }; /* Enable precise pointer */
51 static int line_outs_monitor[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0}; /* Send all inputs/playback to line outs */
52
53 module_param_array(index, int, NULL, 0444);
54 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
55 module_param_array(id, charp, NULL, 0444);
56 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
57 module_param_array(enable, bool, NULL, 0444);
58 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
59 module_param_array(precise_ptr, bool, NULL, 0444);
60 MODULE_PARM_DESC(precise_ptr, "Enable precise pointer (doesn't work reliably).");
61 module_param_array(line_outs_monitor, bool, NULL, 0444);
62 MODULE_PARM_DESC(line_outs_monitor, "Send all input and playback streams to line outs by default.");
63 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
64 MODULE_DESCRIPTION("RME Hammerfall DSP");
65 MODULE_LICENSE("GPL");
66 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
67 "{RME HDSP-9652},"
68 "{RME HDSP-9632}}");
69
70 #define HDSP_MAX_CHANNELS 26
71 #define HDSP_MAX_DS_CHANNELS 14
72 #define HDSP_MAX_QS_CHANNELS 8
73 #define DIGIFACE_SS_CHANNELS 26
74 #define DIGIFACE_DS_CHANNELS 14
75 #define MULTIFACE_SS_CHANNELS 18
76 #define MULTIFACE_DS_CHANNELS 14
77 #define H9652_SS_CHANNELS 26
78 #define H9652_DS_CHANNELS 14
79 /* This does not include possible Analog Extension Boards
80 AEBs are detected at card initialization
81 */
82 #define H9632_SS_CHANNELS 12
83 #define H9632_DS_CHANNELS 8
84 #define H9632_QS_CHANNELS 4
85
86 /* Write registers. These are defined as byte-offsets from the iobase value.
87 */
88 #define HDSP_resetPointer 0
89 #define HDSP_outputBufferAddress 32
90 #define HDSP_inputBufferAddress 36
91 #define HDSP_controlRegister 64
92 #define HDSP_interruptConfirmation 96
93 #define HDSP_outputEnable 128
94 #define HDSP_control2Reg 256
95 #define HDSP_midiDataOut0 352
96 #define HDSP_midiDataOut1 356
97 #define HDSP_fifoData 368
98 #define HDSP_inputEnable 384
99
100 /* Read registers. These are defined as byte-offsets from the iobase value
101 */
102
103 #define HDSP_statusRegister 0
104 #define HDSP_timecode 128
105 #define HDSP_status2Register 192
106 #define HDSP_midiDataOut0 352
107 #define HDSP_midiDataOut1 356
108 #define HDSP_midiDataIn0 360
109 #define HDSP_midiDataIn1 364
110 #define HDSP_midiStatusOut0 384
111 #define HDSP_midiStatusOut1 388
112 #define HDSP_midiStatusIn0 392
113 #define HDSP_midiStatusIn1 396
114 #define HDSP_fifoStatus 400
115
116 /* the meters are regular i/o-mapped registers, but offset
117 considerably from the rest. the peak registers are reset
118 when read; the least-significant 4 bits are full-scale counters;
119 the actual peak value is in the most-significant 24 bits.
120 */
121
122 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
123 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
124 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
125 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
126 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
127
128
129 /* This is for H9652 cards
130 Peak values are read downward from the base
131 Rms values are read upward
132 There are rms values for the outputs too
133 26*3 values are read in ss mode
134 14*3 in ds mode, with no gap between values
135 */
136 #define HDSP_9652_peakBase 7164
137 #define HDSP_9652_rmsBase 4096
138
139 /* c.f. the hdsp_9632_meters_t struct */
140 #define HDSP_9632_metersBase 4096
141
142 #define HDSP_IO_EXTENT 7168
143
144 /* control2 register bits */
145
146 #define HDSP_TMS 0x01
147 #define HDSP_TCK 0x02
148 #define HDSP_TDI 0x04
149 #define HDSP_JTAG 0x08
150 #define HDSP_PWDN 0x10
151 #define HDSP_PROGRAM 0x020
152 #define HDSP_CONFIG_MODE_0 0x040
153 #define HDSP_CONFIG_MODE_1 0x080
154 #define HDSP_VERSION_BIT 0x100
155 #define HDSP_BIGENDIAN_MODE 0x200
156 #define HDSP_RD_MULTIPLE 0x400
157 #define HDSP_9652_ENABLE_MIXER 0x800
158 #define HDSP_TDO 0x10000000
159
160 #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
161 #define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
162
163 /* Control Register bits */
164
165 #define HDSP_Start (1<<0) /* start engine */
166 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
167 #define HDSP_Latency1 (1<<2) /* [ see above ] */
168 #define HDSP_Latency2 (1<<3) /* [ see above ] */
169 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
170 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
171 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
172 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
173 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
174 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
175 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
176 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
177 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
178 #define HDSP_SyncRef2 (1<<13)
179 #define HDSP_SPDIFInputSelect0 (1<<14)
180 #define HDSP_SPDIFInputSelect1 (1<<15)
181 #define HDSP_SyncRef0 (1<<16)
182 #define HDSP_SyncRef1 (1<<17)
183 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
184 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
185 #define HDSP_Midi0InterruptEnable (1<<22)
186 #define HDSP_Midi1InterruptEnable (1<<23)
187 #define HDSP_LineOut (1<<24)
188 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
189 #define HDSP_ADGain1 (1<<26)
190 #define HDSP_DAGain0 (1<<27)
191 #define HDSP_DAGain1 (1<<28)
192 #define HDSP_PhoneGain0 (1<<29)
193 #define HDSP_PhoneGain1 (1<<30)
194 #define HDSP_QuadSpeed (1<<31)
195
196 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
197 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
198 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
199 #define HDSP_ADGainLowGain 0
200
201 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
202 #define HDSP_DAGainHighGain HDSP_DAGainMask
203 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
204 #define HDSP_DAGainMinus10dBV 0
205
206 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
207 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
208 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
209 #define HDSP_PhoneGainMinus12dB 0
210
211 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
212 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
213
214 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
215 #define HDSP_SPDIFInputADAT1 0
216 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
217 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
218 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
219
220 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
221 #define HDSP_SyncRef_ADAT1 0
222 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
223 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
224 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
225 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
226 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
227
228 /* Sample Clock Sources */
229
230 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
231 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
232 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
233 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
234 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
235 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
236 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
237 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
238 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
239 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
240
241 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
242
243 #define HDSP_SYNC_FROM_WORD 0
244 #define HDSP_SYNC_FROM_SPDIF 1
245 #define HDSP_SYNC_FROM_ADAT1 2
246 #define HDSP_SYNC_FROM_ADAT_SYNC 3
247 #define HDSP_SYNC_FROM_ADAT2 4
248 #define HDSP_SYNC_FROM_ADAT3 5
249
250 /* SyncCheck status */
251
252 #define HDSP_SYNC_CHECK_NO_LOCK 0
253 #define HDSP_SYNC_CHECK_LOCK 1
254 #define HDSP_SYNC_CHECK_SYNC 2
255
256 /* AutoSync references - used by "autosync_ref" control switch */
257
258 #define HDSP_AUTOSYNC_FROM_WORD 0
259 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
260 #define HDSP_AUTOSYNC_FROM_SPDIF 2
261 #define HDSP_AUTOSYNC_FROM_NONE 3
262 #define HDSP_AUTOSYNC_FROM_ADAT1 4
263 #define HDSP_AUTOSYNC_FROM_ADAT2 5
264 #define HDSP_AUTOSYNC_FROM_ADAT3 6
265
266 /* Possible sources of S/PDIF input */
267
268 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
269 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
270 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
271 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
272
273 #define HDSP_Frequency32KHz HDSP_Frequency0
274 #define HDSP_Frequency44_1KHz HDSP_Frequency1
275 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
276 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
277 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
278 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
279 /* For H9632 cards */
280 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
281 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
282 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
283
284 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
285 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
286
287 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
288 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
289
290 /* Status Register bits */
291
292 #define HDSP_audioIRQPending (1<<0)
293 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
294 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
295 #define HDSP_Lock1 (1<<2)
296 #define HDSP_Lock0 (1<<3)
297 #define HDSP_SPDIFSync (1<<4)
298 #define HDSP_TimecodeLock (1<<5)
299 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
300 #define HDSP_Sync2 (1<<16)
301 #define HDSP_Sync1 (1<<17)
302 #define HDSP_Sync0 (1<<18)
303 #define HDSP_DoubleSpeedStatus (1<<19)
304 #define HDSP_ConfigError (1<<20)
305 #define HDSP_DllError (1<<21)
306 #define HDSP_spdifFrequency0 (1<<22)
307 #define HDSP_spdifFrequency1 (1<<23)
308 #define HDSP_spdifFrequency2 (1<<24)
309 #define HDSP_SPDIFErrorFlag (1<<25)
310 #define HDSP_BufferID (1<<26)
311 #define HDSP_TimecodeSync (1<<27)
312 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
313 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
314 #define HDSP_midi0IRQPending (1<<30)
315 #define HDSP_midi1IRQPending (1<<31)
316
317 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
318
319 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
320 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
321 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
322
323 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
324 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
325 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
326
327 /* This is for H9632 cards */
328 #define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask
329 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
330 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
331
332 /* Status2 Register bits */
333
334 #define HDSP_version0 (1<<0)
335 #define HDSP_version1 (1<<1)
336 #define HDSP_version2 (1<<2)
337 #define HDSP_wc_lock (1<<3)
338 #define HDSP_wc_sync (1<<4)
339 #define HDSP_inp_freq0 (1<<5)
340 #define HDSP_inp_freq1 (1<<6)
341 #define HDSP_inp_freq2 (1<<7)
342 #define HDSP_SelSyncRef0 (1<<8)
343 #define HDSP_SelSyncRef1 (1<<9)
344 #define HDSP_SelSyncRef2 (1<<10)
345
346 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
347
348 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
349 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
350 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
351 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
352 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
353 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
354 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
355 /* FIXME : more values for 9632 cards ? */
356
357 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
358 #define HDSP_SelSyncRef_ADAT1 0
359 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
360 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
361 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
362 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
363 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
364
365 /* Card state flags */
366
367 #define HDSP_InitializationComplete (1<<0)
368 #define HDSP_FirmwareLoaded (1<<1)
369 #define HDSP_FirmwareCached (1<<2)
370
371 /* FIFO wait times, defined in terms of 1/10ths of msecs */
372
373 #define HDSP_LONG_WAIT 5000
374 #define HDSP_SHORT_WAIT 30
375
376 #define UNITY_GAIN 32768
377 #define MINUS_INFINITY_GAIN 0
378
379 #ifndef PCI_VENDOR_ID_XILINX
380 #define PCI_VENDOR_ID_XILINX 0x10ee
381 #endif
382 #ifndef PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP
383 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
384 #endif
385
386 /* the size of a substream (1 mono data stream) */
387
388 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
389 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
390
391 /* the size of the area we need to allocate for DMA transfers. the
392 size is the same regardless of the number of channels - the
393 Multiface still uses the same memory area.
394
395 Note that we allocate 1 more channel than is apparently needed
396 because the h/w seems to write 1 byte beyond the end of the last
397 page. Sigh.
398 */
399
400 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
401 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
402
403 /* use hotplug firmeare loader? */
404 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
405 #ifndef HDSP_USE_HWDEP_LOADER
406 #define HDSP_FW_LOADER
407 #endif
408 #endif
409
410 typedef struct _hdsp hdsp_t;
411 typedef struct _hdsp_midi hdsp_midi_t;
412 typedef struct _hdsp_9632_meters hdsp_9632_meters_t;
413
414 struct _hdsp_9632_meters {
415 u32 input_peak[16];
416 u32 playback_peak[16];
417 u32 output_peak[16];
418 u32 xxx_peak[16];
419 u32 padding[64];
420 u32 input_rms_low[16];
421 u32 playback_rms_low[16];
422 u32 output_rms_low[16];
423 u32 xxx_rms_low[16];
424 u32 input_rms_high[16];
425 u32 playback_rms_high[16];
426 u32 output_rms_high[16];
427 u32 xxx_rms_high[16];
428 };
429
430 struct _hdsp_midi {
431 hdsp_t *hdsp;
432 int id;
433 snd_rawmidi_t *rmidi;
434 snd_rawmidi_substream_t *input;
435 snd_rawmidi_substream_t *output;
436 char istimer; /* timer in use */
437 struct timer_list timer;
438 spinlock_t lock;
439 int pending;
440 };
441
442 struct _hdsp {
443 spinlock_t lock;
444 snd_pcm_substream_t *capture_substream;
445 snd_pcm_substream_t *playback_substream;
446 hdsp_midi_t midi[2];
447 struct tasklet_struct midi_tasklet;
448 int precise_ptr;
449 u32 control_register; /* cached value */
450 u32 control2_register; /* cached value */
451 u32 creg_spdif;
452 u32 creg_spdif_stream;
453 char *card_name; /* digiface/multiface */
454 HDSP_IO_Type io_type; /* ditto, but for code use */
455 unsigned short firmware_rev;
456 unsigned short state; /* stores state bits */
457 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
458 size_t period_bytes; /* guess what this is */
459 unsigned char max_channels;
460 unsigned char qs_in_channels; /* quad speed mode for H9632 */
461 unsigned char ds_in_channels;
462 unsigned char ss_in_channels; /* different for multiface/digiface */
463 unsigned char qs_out_channels;
464 unsigned char ds_out_channels;
465 unsigned char ss_out_channels;
466
467 struct snd_dma_buffer capture_dma_buf;
468 struct snd_dma_buffer playback_dma_buf;
469 unsigned char *capture_buffer; /* suitably aligned address */
470 unsigned char *playback_buffer; /* suitably aligned address */
471
472 pid_t capture_pid;
473 pid_t playback_pid;
474 int running;
475 int passthru; /* non-zero if doing pass-thru */
476 int system_sample_rate;
477 char *channel_map;
478 int dev;
479 int irq;
480 unsigned long port;
481 void __iomem *iobase;
482 snd_card_t *card;
483 snd_pcm_t *pcm;
484 snd_hwdep_t *hwdep;
485 struct pci_dev *pci;
486 snd_kcontrol_t *spdif_ctl;
487 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
488 };
489
490 /* These tables map the ALSA channels 1..N to the channels that we
491 need to use in order to find the relevant channel buffer. RME
492 refer to this kind of mapping as between "the ADAT channel and
493 the DMA channel." We index it using the logical audio channel,
494 and the value is the DMA channel (i.e. channel buffer number)
495 where the data for that channel can be read/written from/to.
496 */
497
498 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
499 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
500 18, 19, 20, 21, 22, 23, 24, 25
501 };
502
503 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
504 /* Analog */
505 0, 1, 2, 3, 4, 5, 6, 7,
506 /* ADAT 2 */
507 16, 17, 18, 19, 20, 21, 22, 23,
508 /* SPDIF */
509 24, 25,
510 -1, -1, -1, -1, -1, -1, -1, -1
511 };
512
513 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
514 /* ADAT channels are remapped */
515 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
516 /* channels 12 and 13 are S/PDIF */
517 24, 25,
518 /* others don't exist */
519 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
520 };
521
522 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
523 /* ADAT channels */
524 0, 1, 2, 3, 4, 5, 6, 7,
525 /* SPDIF */
526 8, 9,
527 /* Analog */
528 10, 11,
529 /* AO4S-192 and AI4S-192 extension boards */
530 12, 13, 14, 15,
531 /* others don't exist */
532 -1, -1, -1, -1, -1, -1, -1, -1,
533 -1, -1
534 };
535
536 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
537 /* ADAT */
538 1, 3, 5, 7,
539 /* SPDIF */
540 8, 9,
541 /* Analog */
542 10, 11,
543 /* AO4S-192 and AI4S-192 extension boards */
544 12, 13, 14, 15,
545 /* others don't exist */
546 -1, -1, -1, -1, -1, -1, -1, -1,
547 -1, -1, -1, -1, -1, -1
548 };
549
550 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
551 /* ADAT is disabled in this mode */
552 /* SPDIF */
553 8, 9,
554 /* Analog */
555 10, 11,
556 /* AO4S-192 and AI4S-192 extension boards */
557 12, 13, 14, 15,
558 /* others don't exist */
559 -1, -1, -1, -1, -1, -1, -1, -1,
560 -1, -1, -1, -1, -1, -1, -1, -1,
561 -1, -1
562 };
563
564 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
565 {
566 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
567 dmab->dev.dev = snd_dma_pci_data(pci);
568 if (! snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
569 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
570 size, dmab) < 0)
571 return -ENOMEM;
572 }
573 return 0;
574 }
575
576 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
577 {
578 if (dmab->area)
579 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
580 }
581
582
583 static struct pci_device_id snd_hdsp_ids[] = {
584 {
585 .vendor = PCI_VENDOR_ID_XILINX,
586 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
587 .subvendor = PCI_ANY_ID,
588 .subdevice = PCI_ANY_ID,
589 }, /* RME Hammerfall-DSP */
590 { 0, },
591 };
592
593 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
594
595 /* prototypes */
596 static int snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp);
597 static int snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp);
598 static int snd_hdsp_enable_io (hdsp_t *hdsp);
599 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp);
600 static void snd_hdsp_initialize_channels (hdsp_t *hdsp);
601 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout);
602 static int hdsp_autosync_ref(hdsp_t *hdsp);
603 static int snd_hdsp_set_defaults(hdsp_t *hdsp);
604 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp);
605
606 static int hdsp_playback_to_output_key (hdsp_t *hdsp, int in, int out)
607 {
608 switch (hdsp->firmware_rev) {
609 case 0xa:
610 return (64 * out) + (32 + (in));
611 case 0x96:
612 case 0x97:
613 return (32 * out) + (16 + (in));
614 default:
615 return (52 * out) + (26 + (in));
616 }
617 }
618
619 static int hdsp_input_to_output_key (hdsp_t *hdsp, int in, int out)
620 {
621 switch (hdsp->firmware_rev) {
622 case 0xa:
623 return (64 * out) + in;
624 case 0x96:
625 case 0x97:
626 return (32 * out) + in;
627 default:
628 return (52 * out) + in;
629 }
630 }
631
632 static void hdsp_write(hdsp_t *hdsp, int reg, int val)
633 {
634 writel(val, hdsp->iobase + reg);
635 }
636
637 static unsigned int hdsp_read(hdsp_t *hdsp, int reg)
638 {
639 return readl (hdsp->iobase + reg);
640 }
641
642 static int hdsp_check_for_iobox (hdsp_t *hdsp)
643 {
644
645 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
646 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
647 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
648 hdsp->state &= ~HDSP_FirmwareLoaded;
649 return -EIO;
650 }
651 return 0;
652
653 }
654
655 static int snd_hdsp_load_firmware_from_cache(hdsp_t *hdsp) {
656
657 int i;
658 unsigned long flags;
659
660 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
661
662 snd_printk ("loading firmware\n");
663
664 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
665 hdsp_write (hdsp, HDSP_fifoData, 0);
666
667 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
668 snd_printk ("timeout waiting for download preparation\n");
669 return -EIO;
670 }
671
672 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
673
674 for (i = 0; i < 24413; ++i) {
675 hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
676 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
677 snd_printk ("timeout during firmware loading\n");
678 return -EIO;
679 }
680 }
681
682 if ((1000 / HZ) < 3000) {
683 set_current_state(TASK_UNINTERRUPTIBLE);
684 schedule_timeout((3000 * HZ + 999) / 1000);
685 } else {
686 mdelay(3000);
687 }
688
689 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
690 snd_printk ("timeout at end of firmware loading\n");
691 return -EIO;
692 }
693
694 #ifdef SNDRV_BIG_ENDIAN
695 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
696 #else
697 hdsp->control2_register = 0;
698 #endif
699 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
700 snd_printk ("finished firmware loading\n");
701
702 }
703 if (hdsp->state & HDSP_InitializationComplete) {
704 snd_printk("firmware loaded from cache, restoring defaults\n");
705 spin_lock_irqsave(&hdsp->lock, flags);
706 snd_hdsp_set_defaults(hdsp);
707 spin_unlock_irqrestore(&hdsp->lock, flags);
708 }
709
710 hdsp->state |= HDSP_FirmwareLoaded;
711
712 return 0;
713 }
714
715 static int hdsp_get_iobox_version (hdsp_t *hdsp)
716 {
717 int err;
718
719 if (hdsp_check_for_iobox (hdsp)) {
720 return -EIO;
721 }
722
723 if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
724 return err;
725 }
726
727 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
728
729 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
730 hdsp_write (hdsp, HDSP_fifoData, 0);
731 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) {
732 return -EIO;
733 }
734
735 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
736 hdsp_write (hdsp, HDSP_fifoData, 0);
737
738 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
739 hdsp->io_type = Multiface;
740 hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
741 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
742 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
743 } else {
744 hdsp->io_type = Digiface;
745 }
746 } else {
747 /* firmware was already loaded, get iobox type */
748 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
749 hdsp->io_type = Multiface;
750 } else {
751 hdsp->io_type = Digiface;
752 }
753 }
754 return 0;
755 }
756
757
758 static int hdsp_check_for_firmware (hdsp_t *hdsp)
759 {
760 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
761 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
762 snd_printk("firmware not present.\n");
763 hdsp->state &= ~HDSP_FirmwareLoaded;
764 return -EIO;
765 }
766 return 0;
767 }
768
769
770 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout)
771 {
772 int i;
773
774 /* the fifoStatus registers reports on how many words
775 are available in the command FIFO.
776 */
777
778 for (i = 0; i < timeout; i++) {
779
780 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
781 return 0;
782
783 /* not very friendly, but we only do this during a firmware
784 load and changing the mixer, so we just put up with it.
785 */
786
787 udelay (100);
788 }
789
790 snd_printk ("wait for FIFO status <= %d failed after %d iterations\n",
791 count, timeout);
792 return -1;
793 }
794
795 static int hdsp_read_gain (hdsp_t *hdsp, unsigned int addr)
796 {
797 if (addr >= HDSP_MATRIX_MIXER_SIZE) {
798 return 0;
799 }
800 return hdsp->mixer_matrix[addr];
801 }
802
803 static int hdsp_write_gain(hdsp_t *hdsp, unsigned int addr, unsigned short data)
804 {
805 unsigned int ad;
806
807 if (addr >= HDSP_MATRIX_MIXER_SIZE)
808 return -1;
809
810 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
811
812 /* from martin björnsen:
813
814 "You can only write dwords to the
815 mixer memory which contain two
816 mixer values in the low and high
817 word. So if you want to change
818 value 0 you have to read value 1
819 from the cache and write both to
820 the first dword in the mixer
821 memory."
822 */
823
824 if (hdsp->io_type == H9632 && addr >= 512) {
825 return 0;
826 }
827
828 if (hdsp->io_type == H9652 && addr >= 1352) {
829 return 0;
830 }
831
832 hdsp->mixer_matrix[addr] = data;
833
834
835 /* `addr' addresses a 16-bit wide address, but
836 the address space accessed via hdsp_write
837 uses byte offsets. put another way, addr
838 varies from 0 to 1351, but to access the
839 corresponding memory location, we need
840 to access 0 to 2703 ...
841 */
842 ad = addr/2;
843
844 hdsp_write (hdsp, 4096 + (ad*4),
845 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
846 hdsp->mixer_matrix[addr&0x7fe]);
847
848 return 0;
849
850 } else {
851
852 ad = (addr << 16) + data;
853
854 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) {
855 return -1;
856 }
857
858 hdsp_write (hdsp, HDSP_fifoData, ad);
859 hdsp->mixer_matrix[addr] = data;
860
861 }
862
863 return 0;
864 }
865
866 static int snd_hdsp_use_is_exclusive(hdsp_t *hdsp)
867 {
868 unsigned long flags;
869 int ret = 1;
870
871 spin_lock_irqsave(&hdsp->lock, flags);
872 if ((hdsp->playback_pid != hdsp->capture_pid) &&
873 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) {
874 ret = 0;
875 }
876 spin_unlock_irqrestore(&hdsp->lock, flags);
877 return ret;
878 }
879
880 static int hdsp_external_sample_rate (hdsp_t *hdsp)
881 {
882 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
883 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
884
885 switch (rate_bits) {
886 case HDSP_systemFrequency32: return 32000;
887 case HDSP_systemFrequency44_1: return 44100;
888 case HDSP_systemFrequency48: return 48000;
889 case HDSP_systemFrequency64: return 64000;
890 case HDSP_systemFrequency88_2: return 88200;
891 case HDSP_systemFrequency96: return 96000;
892 default:
893 return 0;
894 }
895 }
896
897 static int hdsp_spdif_sample_rate(hdsp_t *hdsp)
898 {
899 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
900 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
901
902 if (status & HDSP_SPDIFErrorFlag) {
903 return 0;
904 }
905
906 switch (rate_bits) {
907 case HDSP_spdifFrequency32KHz: return 32000;
908 case HDSP_spdifFrequency44_1KHz: return 44100;
909 case HDSP_spdifFrequency48KHz: return 48000;
910 case HDSP_spdifFrequency64KHz: return 64000;
911 case HDSP_spdifFrequency88_2KHz: return 88200;
912 case HDSP_spdifFrequency96KHz: return 96000;
913 case HDSP_spdifFrequency128KHz:
914 if (hdsp->io_type == H9632) return 128000;
915 break;
916 case HDSP_spdifFrequency176_4KHz:
917 if (hdsp->io_type == H9632) return 176400;
918 break;
919 case HDSP_spdifFrequency192KHz:
920 if (hdsp->io_type == H9632) return 192000;
921 break;
922 default:
923 break;
924 }
925 snd_printk ("unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
926 return 0;
927 }
928
929 static void hdsp_compute_period_size(hdsp_t *hdsp)
930 {
931 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
932 }
933
934 static snd_pcm_uframes_t hdsp_hw_pointer(hdsp_t *hdsp)
935 {
936 int position;
937
938 position = hdsp_read(hdsp, HDSP_statusRegister);
939
940 if (!hdsp->precise_ptr) {
941 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
942 }
943
944 position &= HDSP_BufferPositionMask;
945 position /= 4;
946 position &= (hdsp->period_bytes/2) - 1;
947 return position;
948 }
949
950 static void hdsp_reset_hw_pointer(hdsp_t *hdsp)
951 {
952 hdsp_write (hdsp, HDSP_resetPointer, 0);
953 }
954
955 static void hdsp_start_audio(hdsp_t *s)
956 {
957 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
958 hdsp_write(s, HDSP_controlRegister, s->control_register);
959 }
960
961 static void hdsp_stop_audio(hdsp_t *s)
962 {
963 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
964 hdsp_write(s, HDSP_controlRegister, s->control_register);
965 }
966
967 static void hdsp_silence_playback(hdsp_t *hdsp)
968 {
969 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
970 }
971
972 static int hdsp_set_interrupt_interval(hdsp_t *s, unsigned int frames)
973 {
974 int n;
975
976 spin_lock_irq(&s->lock);
977
978 frames >>= 7;
979 n = 0;
980 while (frames) {
981 n++;
982 frames >>= 1;
983 }
984
985 s->control_register &= ~HDSP_LatencyMask;
986 s->control_register |= hdsp_encode_latency(n);
987
988 hdsp_write(s, HDSP_controlRegister, s->control_register);
989
990 hdsp_compute_period_size(s);
991
992 spin_unlock_irq(&s->lock);
993
994 return 0;
995 }
996
997 static int hdsp_set_rate(hdsp_t *hdsp, int rate, int called_internally)
998 {
999 int reject_if_open = 0;
1000 int current_rate;
1001 int rate_bits;
1002
1003 /* ASSUMPTION: hdsp->lock is either held, or
1004 there is no need for it (e.g. during module
1005 initialization).
1006 */
1007
1008 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1009 if (called_internally) {
1010 /* request from ctl or card initialization */
1011 snd_printk("device is not running as a clock master: cannot set sample rate.\n");
1012 return -1;
1013 } else {
1014 /* hw_param request while in AutoSync mode */
1015 int external_freq = hdsp_external_sample_rate(hdsp);
1016 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1017
1018 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1019 snd_printk("Detected ADAT in double speed mode\n");
1020 } else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1021 snd_printk("Detected ADAT in quad speed mode\n");
1022 } else if (rate != external_freq) {
1023 snd_printk("No AutoSync source for requested rate\n");
1024 return -1;
1025 }
1026 }
1027 }
1028
1029 current_rate = hdsp->system_sample_rate;
1030
1031 /* Changing from a "single speed" to a "double speed" rate is
1032 not allowed if any substreams are open. This is because
1033 such a change causes a shift in the location of
1034 the DMA buffers and a reduction in the number of available
1035 buffers.
1036
1037 Note that a similar but essentially insoluble problem
1038 exists for externally-driven rate changes. All we can do
1039 is to flag rate changes in the read/write routines. */
1040
1041 if (rate > 96000 && hdsp->io_type != H9632) {
1042 return -EINVAL;
1043 }
1044
1045 switch (rate) {
1046 case 32000:
1047 if (current_rate > 48000) {
1048 reject_if_open = 1;
1049 }
1050 rate_bits = HDSP_Frequency32KHz;
1051 break;
1052 case 44100:
1053 if (current_rate > 48000) {
1054 reject_if_open = 1;
1055 }
1056 rate_bits = HDSP_Frequency44_1KHz;
1057 break;
1058 case 48000:
1059 if (current_rate > 48000) {
1060 reject_if_open = 1;
1061 }
1062 rate_bits = HDSP_Frequency48KHz;
1063 break;
1064 case 64000:
1065 if (current_rate <= 48000 || current_rate > 96000) {
1066 reject_if_open = 1;
1067 }
1068 rate_bits = HDSP_Frequency64KHz;
1069 break;
1070 case 88200:
1071 if (current_rate <= 48000 || current_rate > 96000) {
1072 reject_if_open = 1;
1073 }
1074 rate_bits = HDSP_Frequency88_2KHz;
1075 break;
1076 case 96000:
1077 if (current_rate <= 48000 || current_rate > 96000) {
1078 reject_if_open = 1;
1079 }
1080 rate_bits = HDSP_Frequency96KHz;
1081 break;
1082 case 128000:
1083 if (current_rate < 128000) {
1084 reject_if_open = 1;
1085 }
1086 rate_bits = HDSP_Frequency128KHz;
1087 break;
1088 case 176400:
1089 if (current_rate < 128000) {
1090 reject_if_open = 1;
1091 }
1092 rate_bits = HDSP_Frequency176_4KHz;
1093 break;
1094 case 192000:
1095 if (current_rate < 128000) {
1096 reject_if_open = 1;
1097 }
1098 rate_bits = HDSP_Frequency192KHz;
1099 break;
1100 default:
1101 return -EINVAL;
1102 }
1103
1104 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1105 snd_printk ("cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1106 hdsp->capture_pid,
1107 hdsp->playback_pid);
1108 return -EBUSY;
1109 }
1110
1111 hdsp->control_register &= ~HDSP_FrequencyMask;
1112 hdsp->control_register |= rate_bits;
1113 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1114
1115 if (rate >= 128000) {
1116 hdsp->channel_map = channel_map_H9632_qs;
1117 } else if (rate > 48000) {
1118 if (hdsp->io_type == H9632) {
1119 hdsp->channel_map = channel_map_H9632_ds;
1120 } else {
1121 hdsp->channel_map = channel_map_ds;
1122 }
1123 } else {
1124 switch (hdsp->io_type) {
1125 case Multiface:
1126 hdsp->channel_map = channel_map_mf_ss;
1127 break;
1128 case Digiface:
1129 case H9652:
1130 hdsp->channel_map = channel_map_df_ss;
1131 break;
1132 case H9632:
1133 hdsp->channel_map = channel_map_H9632_ss;
1134 break;
1135 default:
1136 /* should never happen */
1137 break;
1138 }
1139 }
1140
1141 hdsp->system_sample_rate = rate;
1142
1143 return 0;
1144 }
1145
1146 static void hdsp_set_thru(hdsp_t *hdsp, int channel, int enable)
1147 {
1148
1149 hdsp->passthru = 0;
1150
1151 if (channel < 0) {
1152
1153 int i;
1154
1155 /* set thru for all channels */
1156
1157 if (enable) {
1158 for (i = 0; i < hdsp->max_channels; i++) {
1159 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), UNITY_GAIN);
1160 }
1161 } else {
1162 for (i = 0; i < hdsp->max_channels; i++) {
1163 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), MINUS_INFINITY_GAIN);
1164 }
1165 }
1166
1167 } else {
1168 int mapped_channel;
1169
1170 snd_assert(channel < hdsp->max_channels, return);
1171
1172 mapped_channel = hdsp->channel_map[channel];
1173
1174 snd_assert(mapped_channel > -1, return);
1175
1176 if (enable) {
1177 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), UNITY_GAIN);
1178 } else {
1179 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), MINUS_INFINITY_GAIN);
1180 }
1181 }
1182 }
1183
1184 static int hdsp_set_passthru(hdsp_t *hdsp, int onoff)
1185 {
1186 if (onoff) {
1187 hdsp_set_thru(hdsp, -1, 1);
1188 hdsp_reset_hw_pointer(hdsp);
1189 hdsp_silence_playback(hdsp);
1190
1191 /* we don't want interrupts, so do a
1192 custom version of hdsp_start_audio().
1193 */
1194
1195 hdsp->control_register |= (HDSP_Start|HDSP_AudioInterruptEnable|hdsp_encode_latency(7));
1196
1197 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1198 hdsp->passthru = 1;
1199 } else {
1200 hdsp_set_thru(hdsp, -1, 0);
1201 hdsp_stop_audio(hdsp);
1202 hdsp->passthru = 0;
1203 }
1204
1205 return 0;
1206 }
1207
1208 /*----------------------------------------------------------------------------
1209 MIDI
1210 ----------------------------------------------------------------------------*/
1211
1212 static unsigned char snd_hdsp_midi_read_byte (hdsp_t *hdsp, int id)
1213 {
1214 /* the hardware already does the relevant bit-mask with 0xff */
1215 if (id) {
1216 return hdsp_read(hdsp, HDSP_midiDataIn1);
1217 } else {
1218 return hdsp_read(hdsp, HDSP_midiDataIn0);
1219 }
1220 }
1221
1222 static void snd_hdsp_midi_write_byte (hdsp_t *hdsp, int id, int val)
1223 {
1224 /* the hardware already does the relevant bit-mask with 0xff */
1225 if (id) {
1226 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1227 } else {
1228 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1229 }
1230 }
1231
1232 static int snd_hdsp_midi_input_available (hdsp_t *hdsp, int id)
1233 {
1234 if (id) {
1235 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1236 } else {
1237 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1238 }
1239 }
1240
1241 static int snd_hdsp_midi_output_possible (hdsp_t *hdsp, int id)
1242 {
1243 int fifo_bytes_used;
1244
1245 if (id) {
1246 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1247 } else {
1248 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1249 }
1250
1251 if (fifo_bytes_used < 128) {
1252 return 128 - fifo_bytes_used;
1253 } else {
1254 return 0;
1255 }
1256 }
1257
1258 static void snd_hdsp_flush_midi_input (hdsp_t *hdsp, int id)
1259 {
1260 while (snd_hdsp_midi_input_available (hdsp, id)) {
1261 snd_hdsp_midi_read_byte (hdsp, id);
1262 }
1263 }
1264
1265 static int snd_hdsp_midi_output_write (hdsp_midi_t *hmidi)
1266 {
1267 unsigned long flags;
1268 int n_pending;
1269 int to_write;
1270 int i;
1271 unsigned char buf[128];
1272
1273 /* Output is not interrupt driven */
1274
1275 spin_lock_irqsave (&hmidi->lock, flags);
1276 if (hmidi->output) {
1277 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1278 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1279 if (n_pending > (int)sizeof (buf))
1280 n_pending = sizeof (buf);
1281
1282 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1283 for (i = 0; i < to_write; ++i)
1284 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1285 }
1286 }
1287 }
1288 }
1289 spin_unlock_irqrestore (&hmidi->lock, flags);
1290 return 0;
1291 }
1292
1293 static int snd_hdsp_midi_input_read (hdsp_midi_t *hmidi)
1294 {
1295 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1296 unsigned long flags;
1297 int n_pending;
1298 int i;
1299
1300 spin_lock_irqsave (&hmidi->lock, flags);
1301 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1302 if (hmidi->input) {
1303 if (n_pending > (int)sizeof (buf)) {
1304 n_pending = sizeof (buf);
1305 }
1306 for (i = 0; i < n_pending; ++i) {
1307 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1308 }
1309 if (n_pending) {
1310 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1311 }
1312 } else {
1313 /* flush the MIDI input FIFO */
1314 while (--n_pending) {
1315 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1316 }
1317 }
1318 }
1319 hmidi->pending = 0;
1320 if (hmidi->id) {
1321 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1322 } else {
1323 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1324 }
1325 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1326 spin_unlock_irqrestore (&hmidi->lock, flags);
1327 return snd_hdsp_midi_output_write (hmidi);
1328 }
1329
1330 static void snd_hdsp_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1331 {
1332 hdsp_t *hdsp;
1333 hdsp_midi_t *hmidi;
1334 unsigned long flags;
1335 u32 ie;
1336
1337 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1338 hdsp = hmidi->hdsp;
1339 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1340 spin_lock_irqsave (&hdsp->lock, flags);
1341 if (up) {
1342 if (!(hdsp->control_register & ie)) {
1343 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1344 hdsp->control_register |= ie;
1345 }
1346 } else {
1347 hdsp->control_register &= ~ie;
1348 }
1349
1350 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1351 spin_unlock_irqrestore (&hdsp->lock, flags);
1352 }
1353
1354 static void snd_hdsp_midi_output_timer(unsigned long data)
1355 {
1356 hdsp_midi_t *hmidi = (hdsp_midi_t *) data;
1357 unsigned long flags;
1358
1359 snd_hdsp_midi_output_write(hmidi);
1360 spin_lock_irqsave (&hmidi->lock, flags);
1361
1362 /* this does not bump hmidi->istimer, because the
1363 kernel automatically removed the timer when it
1364 expired, and we are now adding it back, thus
1365 leaving istimer wherever it was set before.
1366 */
1367
1368 if (hmidi->istimer) {
1369 hmidi->timer.expires = 1 + jiffies;
1370 add_timer(&hmidi->timer);
1371 }
1372
1373 spin_unlock_irqrestore (&hmidi->lock, flags);
1374 }
1375
1376 static void snd_hdsp_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1377 {
1378 hdsp_midi_t *hmidi;
1379 unsigned long flags;
1380
1381 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1382 spin_lock_irqsave (&hmidi->lock, flags);
1383 if (up) {
1384 if (!hmidi->istimer) {
1385 init_timer(&hmidi->timer);
1386 hmidi->timer.function = snd_hdsp_midi_output_timer;
1387 hmidi->timer.data = (unsigned long) hmidi;
1388 hmidi->timer.expires = 1 + jiffies;
1389 add_timer(&hmidi->timer);
1390 hmidi->istimer++;
1391 }
1392 } else {
1393 if (hmidi->istimer && --hmidi->istimer <= 0) {
1394 del_timer (&hmidi->timer);
1395 }
1396 }
1397 spin_unlock_irqrestore (&hmidi->lock, flags);
1398 if (up)
1399 snd_hdsp_midi_output_write(hmidi);
1400 }
1401
1402 static int snd_hdsp_midi_input_open(snd_rawmidi_substream_t * substream)
1403 {
1404 hdsp_midi_t *hmidi;
1405
1406 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1407 spin_lock_irq (&hmidi->lock);
1408 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1409 hmidi->input = substream;
1410 spin_unlock_irq (&hmidi->lock);
1411
1412 return 0;
1413 }
1414
1415 static int snd_hdsp_midi_output_open(snd_rawmidi_substream_t * substream)
1416 {
1417 hdsp_midi_t *hmidi;
1418
1419 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1420 spin_lock_irq (&hmidi->lock);
1421 hmidi->output = substream;
1422 spin_unlock_irq (&hmidi->lock);
1423
1424 return 0;
1425 }
1426
1427 static int snd_hdsp_midi_input_close(snd_rawmidi_substream_t * substream)
1428 {
1429 hdsp_midi_t *hmidi;
1430
1431 snd_hdsp_midi_input_trigger (substream, 0);
1432
1433 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1434 spin_lock_irq (&hmidi->lock);
1435 hmidi->input = NULL;
1436 spin_unlock_irq (&hmidi->lock);
1437
1438 return 0;
1439 }
1440
1441 static int snd_hdsp_midi_output_close(snd_rawmidi_substream_t * substream)
1442 {
1443 hdsp_midi_t *hmidi;
1444
1445 snd_hdsp_midi_output_trigger (substream, 0);
1446
1447 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1448 spin_lock_irq (&hmidi->lock);
1449 hmidi->output = NULL;
1450 spin_unlock_irq (&hmidi->lock);
1451
1452 return 0;
1453 }
1454
1455 static snd_rawmidi_ops_t snd_hdsp_midi_output =
1456 {
1457 .open = snd_hdsp_midi_output_open,
1458 .close = snd_hdsp_midi_output_close,
1459 .trigger = snd_hdsp_midi_output_trigger,
1460 };
1461
1462 static snd_rawmidi_ops_t snd_hdsp_midi_input =
1463 {
1464 .open = snd_hdsp_midi_input_open,
1465 .close = snd_hdsp_midi_input_close,
1466 .trigger = snd_hdsp_midi_input_trigger,
1467 };
1468
1469 static int __devinit snd_hdsp_create_midi (snd_card_t *card, hdsp_t *hdsp, int id)
1470 {
1471 char buf[32];
1472
1473 hdsp->midi[id].id = id;
1474 hdsp->midi[id].rmidi = NULL;
1475 hdsp->midi[id].input = NULL;
1476 hdsp->midi[id].output = NULL;
1477 hdsp->midi[id].hdsp = hdsp;
1478 hdsp->midi[id].istimer = 0;
1479 hdsp->midi[id].pending = 0;
1480 spin_lock_init (&hdsp->midi[id].lock);
1481
1482 sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1483 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) {
1484 return -1;
1485 }
1486
1487 sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1488 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1489
1490 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1491 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1492
1493 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1494 SNDRV_RAWMIDI_INFO_INPUT |
1495 SNDRV_RAWMIDI_INFO_DUPLEX;
1496
1497 return 0;
1498 }
1499
1500 /*-----------------------------------------------------------------------------
1501 Control Interface
1502 ----------------------------------------------------------------------------*/
1503
1504 static u32 snd_hdsp_convert_from_aes(snd_aes_iec958_t *aes)
1505 {
1506 u32 val = 0;
1507 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1508 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1509 if (val & HDSP_SPDIFProfessional)
1510 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1511 else
1512 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1513 return val;
1514 }
1515
1516 static void snd_hdsp_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
1517 {
1518 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1519 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1520 if (val & HDSP_SPDIFProfessional)
1521 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1522 else
1523 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1524 }
1525
1526 static int snd_hdsp_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1527 {
1528 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1529 uinfo->count = 1;
1530 return 0;
1531 }
1532
1533 static int snd_hdsp_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1534 {
1535 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1536
1537 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1538 return 0;
1539 }
1540
1541 static int snd_hdsp_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1542 {
1543 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1544 int change;
1545 u32 val;
1546
1547 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1548 spin_lock_irq(&hdsp->lock);
1549 change = val != hdsp->creg_spdif;
1550 hdsp->creg_spdif = val;
1551 spin_unlock_irq(&hdsp->lock);
1552 return change;
1553 }
1554
1555 static int snd_hdsp_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1556 {
1557 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1558 uinfo->count = 1;
1559 return 0;
1560 }
1561
1562 static int snd_hdsp_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1563 {
1564 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1565
1566 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1567 return 0;
1568 }
1569
1570 static int snd_hdsp_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1571 {
1572 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1573 int change;
1574 u32 val;
1575
1576 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1577 spin_lock_irq(&hdsp->lock);
1578 change = val != hdsp->creg_spdif_stream;
1579 hdsp->creg_spdif_stream = val;
1580 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1581 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1582 spin_unlock_irq(&hdsp->lock);
1583 return change;
1584 }
1585
1586 static int snd_hdsp_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1587 {
1588 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1589 uinfo->count = 1;
1590 return 0;
1591 }
1592
1593 static int snd_hdsp_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1594 {
1595 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1596 return 0;
1597 }
1598
1599 #define HDSP_SPDIF_IN(xname, xindex) \
1600 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1601 .name = xname, \
1602 .index = xindex, \
1603 .info = snd_hdsp_info_spdif_in, \
1604 .get = snd_hdsp_get_spdif_in, \
1605 .put = snd_hdsp_put_spdif_in }
1606
1607 static unsigned int hdsp_spdif_in(hdsp_t *hdsp)
1608 {
1609 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1610 }
1611
1612 static int hdsp_set_spdif_input(hdsp_t *hdsp, int in)
1613 {
1614 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1615 hdsp->control_register |= hdsp_encode_spdif_in(in);
1616 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1617 return 0;
1618 }
1619
1620 static int snd_hdsp_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1621 {
1622 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1623 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1624
1625 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1626 uinfo->count = 1;
1627 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1628 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1629 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1630 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1631 return 0;
1632 }
1633
1634 static int snd_hdsp_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1635 {
1636 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1637
1638 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1639 return 0;
1640 }
1641
1642 static int snd_hdsp_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1643 {
1644 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1645 int change;
1646 unsigned int val;
1647
1648 if (!snd_hdsp_use_is_exclusive(hdsp))
1649 return -EBUSY;
1650 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1651 spin_lock_irq(&hdsp->lock);
1652 change = val != hdsp_spdif_in(hdsp);
1653 if (change)
1654 hdsp_set_spdif_input(hdsp, val);
1655 spin_unlock_irq(&hdsp->lock);
1656 return change;
1657 }
1658
1659 #define HDSP_SPDIF_OUT(xname, xindex) \
1660 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1661 .info = snd_hdsp_info_spdif_bits, \
1662 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1663
1664 static int hdsp_spdif_out(hdsp_t *hdsp)
1665 {
1666 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1667 }
1668
1669 static int hdsp_set_spdif_output(hdsp_t *hdsp, int out)
1670 {
1671 if (out) {
1672 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1673 } else {
1674 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1675 }
1676 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1677 return 0;
1678 }
1679
1680 static int snd_hdsp_info_spdif_bits(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1681 {
1682 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1683 uinfo->count = 1;
1684 uinfo->value.integer.min = 0;
1685 uinfo->value.integer.max = 1;
1686 return 0;
1687 }
1688
1689 static int snd_hdsp_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1690 {
1691 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1692
1693 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1694 return 0;
1695 }
1696
1697 static int snd_hdsp_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1698 {
1699 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1700 int change;
1701 unsigned int val;
1702
1703 if (!snd_hdsp_use_is_exclusive(hdsp))
1704 return -EBUSY;
1705 val = ucontrol->value.integer.value[0] & 1;
1706 spin_lock_irq(&hdsp->lock);
1707 change = (int)val != hdsp_spdif_out(hdsp);
1708 hdsp_set_spdif_output(hdsp, val);
1709 spin_unlock_irq(&hdsp->lock);
1710 return change;
1711 }
1712
1713 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1714 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1715 .info = snd_hdsp_info_spdif_bits, \
1716 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1717
1718 static int hdsp_spdif_professional(hdsp_t *hdsp)
1719 {
1720 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1721 }
1722
1723 static int hdsp_set_spdif_professional(hdsp_t *hdsp, int val)
1724 {
1725 if (val) {
1726 hdsp->control_register |= HDSP_SPDIFProfessional;
1727 } else {
1728 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1729 }
1730 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1731 return 0;
1732 }
1733
1734 static int snd_hdsp_get_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1735 {
1736 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1737
1738 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1739 return 0;
1740 }
1741
1742 static int snd_hdsp_put_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1743 {
1744 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1745 int change;
1746 unsigned int val;
1747
1748 if (!snd_hdsp_use_is_exclusive(hdsp))
1749 return -EBUSY;
1750 val = ucontrol->value.integer.value[0] & 1;
1751 spin_lock_irq(&hdsp->lock);
1752 change = (int)val != hdsp_spdif_professional(hdsp);
1753 hdsp_set_spdif_professional(hdsp, val);
1754 spin_unlock_irq(&hdsp->lock);
1755 return change;
1756 }
1757
1758 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1759 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1760 .info = snd_hdsp_info_spdif_bits, \
1761 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1762
1763 static int hdsp_spdif_emphasis(hdsp_t *hdsp)
1764 {
1765 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1766 }
1767
1768 static int hdsp_set_spdif_emphasis(hdsp_t *hdsp, int val)
1769 {
1770 if (val) {
1771 hdsp->control_register |= HDSP_SPDIFEmphasis;
1772 } else {
1773 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1774 }
1775 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1776 return 0;
1777 }
1778
1779 static int snd_hdsp_get_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1780 {
1781 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1782
1783 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1784 return 0;
1785 }
1786
1787 static int snd_hdsp_put_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1788 {
1789 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1790 int change;
1791 unsigned int val;
1792
1793 if (!snd_hdsp_use_is_exclusive(hdsp))
1794 return -EBUSY;
1795 val = ucontrol->value.integer.value[0] & 1;
1796 spin_lock_irq(&hdsp->lock);
1797 change = (int)val != hdsp_spdif_emphasis(hdsp);
1798 hdsp_set_spdif_emphasis(hdsp, val);
1799 spin_unlock_irq(&hdsp->lock);
1800 return change;
1801 }
1802
1803 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1804 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1805 .info = snd_hdsp_info_spdif_bits, \
1806 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1807
1808 static int hdsp_spdif_nonaudio(hdsp_t *hdsp)
1809 {
1810 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1811 }
1812
1813 static int hdsp_set_spdif_nonaudio(hdsp_t *hdsp, int val)
1814 {
1815 if (val) {
1816 hdsp->control_register |= HDSP_SPDIFNonAudio;
1817 } else {
1818 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1819 }
1820 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1821 return 0;
1822 }
1823
1824 static int snd_hdsp_get_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1825 {
1826 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1827
1828 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1829 return 0;
1830 }
1831
1832 static int snd_hdsp_put_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1833 {
1834 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1835 int change;
1836 unsigned int val;
1837
1838 if (!snd_hdsp_use_is_exclusive(hdsp))
1839 return -EBUSY;
1840 val = ucontrol->value.integer.value[0] & 1;
1841 spin_lock_irq(&hdsp->lock);
1842 change = (int)val != hdsp_spdif_nonaudio(hdsp);
1843 hdsp_set_spdif_nonaudio(hdsp, val);
1844 spin_unlock_irq(&hdsp->lock);
1845 return change;
1846 }
1847
1848 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1849 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1850 .name = xname, \
1851 .index = xindex, \
1852 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1853 .info = snd_hdsp_info_spdif_sample_rate, \
1854 .get = snd_hdsp_get_spdif_sample_rate \
1855 }
1856
1857 static int snd_hdsp_info_spdif_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1858 {
1859 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1860 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1861
1862 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1863 uinfo->count = 1;
1864 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1865 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1866 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1867 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1868 return 0;
1869 }
1870
1871 static int snd_hdsp_get_spdif_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1872 {
1873 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1874
1875 switch (hdsp_spdif_sample_rate(hdsp)) {
1876 case 32000:
1877 ucontrol->value.enumerated.item[0] = 0;
1878 break;
1879 case 44100:
1880 ucontrol->value.enumerated.item[0] = 1;
1881 break;
1882 case 48000:
1883 ucontrol->value.enumerated.item[0] = 2;
1884 break;
1885 case 64000:
1886 ucontrol->value.enumerated.item[0] = 3;
1887 break;
1888 case 88200:
1889 ucontrol->value.enumerated.item[0] = 4;
1890 break;
1891 case 96000:
1892 ucontrol->value.enumerated.item[0] = 5;
1893 break;
1894 case 128000:
1895 ucontrol->value.enumerated.item[0] = 7;
1896 break;
1897 case 176400:
1898 ucontrol->value.enumerated.item[0] = 8;
1899 break;
1900 case 192000:
1901 ucontrol->value.enumerated.item[0] = 9;
1902 break;
1903 default:
1904 ucontrol->value.enumerated.item[0] = 6;
1905 }
1906 return 0;
1907 }
1908
1909 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1910 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1911 .name = xname, \
1912 .index = xindex, \
1913 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1914 .info = snd_hdsp_info_system_sample_rate, \
1915 .get = snd_hdsp_get_system_sample_rate \
1916 }
1917
1918 static int snd_hdsp_info_system_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1919 {
1920 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1921 uinfo->count = 1;
1922 return 0;
1923 }
1924
1925 static int snd_hdsp_get_system_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1926 {
1927 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1928
1929 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1930 return 0;
1931 }
1932
1933 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1934 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1935 .name = xname, \
1936 .index = xindex, \
1937 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1938 .info = snd_hdsp_info_autosync_sample_rate, \
1939 .get = snd_hdsp_get_autosync_sample_rate \
1940 }
1941
1942 static int snd_hdsp_info_autosync_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1943 {
1944 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1945 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1946 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1947 uinfo->count = 1;
1948 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1949 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1950 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1951 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1952 return 0;
1953 }
1954
1955 static int snd_hdsp_get_autosync_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1956 {
1957 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1958
1959 switch (hdsp_external_sample_rate(hdsp)) {
1960 case 32000:
1961 ucontrol->value.enumerated.item[0] = 0;
1962 break;
1963 case 44100:
1964 ucontrol->value.enumerated.item[0] = 1;
1965 break;
1966 case 48000:
1967 ucontrol->value.enumerated.item[0] = 2;
1968 break;
1969 case 64000:
1970 ucontrol->value.enumerated.item[0] = 3;
1971 break;
1972 case 88200:
1973 ucontrol->value.enumerated.item[0] = 4;
1974 break;
1975 case 96000:
1976 ucontrol->value.enumerated.item[0] = 5;
1977 break;
1978 case 128000:
1979 ucontrol->value.enumerated.item[0] = 7;
1980 break;
1981 case 176400:
1982 ucontrol->value.enumerated.item[0] = 8;
1983 break;
1984 case 192000:
1985 ucontrol->value.enumerated.item[0] = 9;
1986 break;
1987 default:
1988 ucontrol->value.enumerated.item[0] = 6;
1989 }
1990 return 0;
1991 }
1992
1993 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1994 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1995 .name = xname, \
1996 .index = xindex, \
1997 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1998 .info = snd_hdsp_info_system_clock_mode, \
1999 .get = snd_hdsp_get_system_clock_mode \
2000 }
2001
2002 static int hdsp_system_clock_mode(hdsp_t *hdsp)
2003 {
2004 if (hdsp->control_register & HDSP_ClockModeMaster) {
2005 return 0;
2006 } else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) {
2007 return 0;
2008 }
2009 return 1;
2010 }
2011
2012 static int snd_hdsp_info_system_clock_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2013 {
2014 static char *texts[] = {"Master", "Slave" };
2015
2016 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2017 uinfo->count = 1;
2018 uinfo->value.enumerated.items = 2;
2019 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2020 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2021 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2022 return 0;
2023 }
2024
2025 static int snd_hdsp_get_system_clock_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2026 {
2027 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2028
2029 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
2030 return 0;
2031 }
2032
2033 #define HDSP_CLOCK_SOURCE(xname, xindex) \
2034 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
2035 .name = xname, \
2036 .index = xindex, \
2037 .info = snd_hdsp_info_clock_source, \
2038 .get = snd_hdsp_get_clock_source, \
2039 .put = snd_hdsp_put_clock_source \
2040 }
2041
2042 static int hdsp_clock_source(hdsp_t *hdsp)
2043 {
2044 if (hdsp->control_register & HDSP_ClockModeMaster) {
2045 switch (hdsp->system_sample_rate) {
2046 case 32000:
2047 return 1;
2048 case 44100:
2049 return 2;
2050 case 48000:
2051 return 3;
2052 case 64000:
2053 return 4;
2054 case 88200:
2055 return 5;
2056 case 96000:
2057 return 6;
2058 case 128000:
2059 return 7;
2060 case 176400:
2061 return 8;
2062 case 192000:
2063 return 9;
2064 default:
2065 return 3;
2066 }
2067 } else {
2068 return 0;
2069 }
2070 }
2071
2072 static int hdsp_set_clock_source(hdsp_t *hdsp, int mode)
2073 {
2074 int rate;
2075 switch (mode) {
2076 case HDSP_CLOCK_SOURCE_AUTOSYNC:
2077 if (hdsp_external_sample_rate(hdsp) != 0) {
2078 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2079 hdsp->control_register &= ~HDSP_ClockModeMaster;
2080 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2081 return 0;
2082 }
2083 }
2084 return -1;
2085 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2086 rate = 32000;
2087 break;
2088 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2089 rate = 44100;
2090 break;
2091 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2092 rate = 48000;
2093 break;
2094 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2095 rate = 64000;
2096 break;
2097 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2098 rate = 88200;
2099 break;
2100 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2101 rate = 96000;
2102 break;
2103 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2104 rate = 128000;
2105 break;
2106 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2107 rate = 176400;
2108 break;
2109 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2110 rate = 192000;
2111 break;
2112 default:
2113 rate = 48000;
2114 }
2115 hdsp->control_register |= HDSP_ClockModeMaster;
2116 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2117 hdsp_set_rate(hdsp, rate, 1);
2118 return 0;
2119 }
2120
2121 static int snd_hdsp_info_clock_source(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2122 {
2123 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2124 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2125
2126 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2127 uinfo->count = 1;
2128 if (hdsp->io_type == H9632)
2129 uinfo->value.enumerated.items = 10;
2130 else
2131 uinfo->value.enumerated.items = 7;
2132 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2133 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2134 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2135 return 0;
2136 }
2137
2138 static int snd_hdsp_get_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2139 {
2140 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2141
2142 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2143 return 0;
2144 }
2145
2146 static int snd_hdsp_put_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2147 {
2148 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2149 int change;
2150 int val;
2151
2152 if (!snd_hdsp_use_is_exclusive(hdsp))
2153 return -EBUSY;
2154 val = ucontrol->value.enumerated.item[0];
2155 if (val < 0) val = 0;
2156 if (hdsp->io_type == H9632) {
2157 if (val > 9) val = 9;
2158 } else {
2159 if (val > 6) val = 6;
2160 }
2161 spin_lock_irq(&hdsp->lock);
2162 if (val != hdsp_clock_source(hdsp)) {
2163 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2164 } else {
2165 change = 0;
2166 }
2167 spin_unlock_irq(&hdsp->lock);
2168 return change;
2169 }
2170
2171 #define HDSP_DA_GAIN(xname, xindex) \
2172 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2173 .name = xname, \
2174 .index = xindex, \
2175 .info = snd_hdsp_info_da_gain, \
2176 .get = snd_hdsp_get_da_gain, \
2177 .put = snd_hdsp_put_da_gain \
2178 }
2179
2180 static int hdsp_da_gain(hdsp_t *hdsp)
2181 {
2182 switch (hdsp->control_register & HDSP_DAGainMask) {
2183 case HDSP_DAGainHighGain:
2184 return 0;
2185 case HDSP_DAGainPlus4dBu:
2186 return 1;
2187 case HDSP_DAGainMinus10dBV:
2188 return 2;
2189 default:
2190 return 1;
2191 }
2192 }
2193
2194 static int hdsp_set_da_gain(hdsp_t *hdsp, int mode)
2195 {
2196 hdsp->control_register &= ~HDSP_DAGainMask;
2197 switch (mode) {
2198 case 0:
2199 hdsp->control_register |= HDSP_DAGainHighGain;
2200 break;
2201 case 1:
2202 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2203 break;
2204 case 2:
2205 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2206 break;
2207 default:
2208 return -1;
2209
2210 }
2211 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2212 return 0;
2213 }
2214
2215 static int snd_hdsp_info_da_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2216 {
2217 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2218
2219 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2220 uinfo->count = 1;
2221 uinfo->value.enumerated.items = 3;
2222 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2223 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2224 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2225 return 0;
2226 }
2227
2228 static int snd_hdsp_get_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2229 {
2230 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2231
2232 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2233 return 0;
2234 }
2235
2236 static int snd_hdsp_put_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2237 {
2238 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2239 int change;
2240 int val;
2241
2242 if (!snd_hdsp_use_is_exclusive(hdsp))
2243 return -EBUSY;
2244 val = ucontrol->value.enumerated.item[0];
2245 if (val < 0) val = 0;
2246 if (val > 2) val = 2;
2247 spin_lock_irq(&hdsp->lock);
2248 if (val != hdsp_da_gain(hdsp)) {
2249 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2250 } else {
2251 change = 0;
2252 }
2253 spin_unlock_irq(&hdsp->lock);
2254 return change;
2255 }
2256
2257 #define HDSP_AD_GAIN(xname, xindex) \
2258 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2259 .name = xname, \
2260 .index = xindex, \
2261 .info = snd_hdsp_info_ad_gain, \
2262 .get = snd_hdsp_get_ad_gain, \
2263 .put = snd_hdsp_put_ad_gain \
2264 }
2265
2266 static int hdsp_ad_gain(hdsp_t *hdsp)
2267 {
2268 switch (hdsp->control_register & HDSP_ADGainMask) {
2269 case HDSP_ADGainMinus10dBV:
2270 return 0;
2271 case HDSP_ADGainPlus4dBu:
2272 return 1;
2273 case HDSP_ADGainLowGain:
2274 return 2;
2275 default:
2276 return 1;
2277 }
2278 }
2279
2280 static int hdsp_set_ad_gain(hdsp_t *hdsp, int mode)
2281 {
2282 hdsp->control_register &= ~HDSP_ADGainMask;
2283 switch (mode) {
2284 case 0:
2285 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2286 break;
2287 case 1:
2288 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2289 break;
2290 case 2:
2291 hdsp->control_register |= HDSP_ADGainLowGain;
2292 break;
2293 default:
2294 return -1;
2295
2296 }
2297 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2298 return 0;
2299 }
2300
2301 static int snd_hdsp_info_ad_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2302 {
2303 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2304
2305 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2306 uinfo->count = 1;
2307 uinfo->value.enumerated.items = 3;
2308 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2309 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2310 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2311 return 0;
2312 }
2313
2314 static int snd_hdsp_get_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2315 {
2316 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2317
2318 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2319 return 0;
2320 }
2321
2322 static int snd_hdsp_put_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2323 {
2324 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2325 int change;
2326 int val;
2327
2328 if (!snd_hdsp_use_is_exclusive(hdsp))
2329 return -EBUSY;
2330 val = ucontrol->value.enumerated.item[0];
2331 if (val < 0) val = 0;
2332 if (val > 2) val = 2;
2333 spin_lock_irq(&hdsp->lock);
2334 if (val != hdsp_ad_gain(hdsp)) {
2335 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2336 } else {
2337 change = 0;
2338 }
2339 spin_unlock_irq(&hdsp->lock);
2340 return change;
2341 }
2342
2343 #define HDSP_PHONE_GAIN(xname, xindex) \
2344 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2345 .name = xname, \
2346 .index = xindex, \
2347 .info = snd_hdsp_info_phone_gain, \
2348 .get = snd_hdsp_get_phone_gain, \
2349 .put = snd_hdsp_put_phone_gain \
2350 }
2351
2352 static int hdsp_phone_gain(hdsp_t *hdsp)
2353 {
2354 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2355 case HDSP_PhoneGain0dB:
2356 return 0;
2357 case HDSP_PhoneGainMinus6dB:
2358 return 1;
2359 case HDSP_PhoneGainMinus12dB:
2360 return 2;
2361 default:
2362 return 0;
2363 }
2364 }
2365
2366 static int hdsp_set_phone_gain(hdsp_t *hdsp, int mode)
2367 {
2368 hdsp->control_register &= ~HDSP_PhoneGainMask;
2369 switch (mode) {
2370 case 0:
2371 hdsp->control_register |= HDSP_PhoneGain0dB;
2372 break;
2373 case 1:
2374 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2375 break;
2376 case 2:
2377 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2378 break;
2379 default:
2380 return -1;
2381
2382 }
2383 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2384 return 0;
2385 }
2386
2387 static int snd_hdsp_info_phone_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2388 {
2389 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2390
2391 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2392 uinfo->count = 1;
2393 uinfo->value.enumerated.items = 3;
2394 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2395 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2396 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2397 return 0;
2398 }
2399
2400 static int snd_hdsp_get_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2401 {
2402 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2403
2404 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2405 return 0;
2406 }
2407
2408 static int snd_hdsp_put_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2409 {
2410 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2411 int change;
2412 int val;
2413
2414 if (!snd_hdsp_use_is_exclusive(hdsp))
2415 return -EBUSY;
2416 val = ucontrol->value.enumerated.item[0];
2417 if (val < 0) val = 0;
2418 if (val > 2) val = 2;
2419 spin_lock_irq(&hdsp->lock);
2420 if (val != hdsp_phone_gain(hdsp)) {
2421 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2422 } else {
2423 change = 0;
2424 }
2425 spin_unlock_irq(&hdsp->lock);
2426 return change;
2427 }
2428
2429 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2430 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2431 .name = xname, \
2432 .index = xindex, \
2433 .info = snd_hdsp_info_xlr_breakout_cable, \
2434 .get = snd_hdsp_get_xlr_breakout_cable, \
2435 .put = snd_hdsp_put_xlr_breakout_cable \
2436 }
2437
2438 static int hdsp_xlr_breakout_cable(hdsp_t *hdsp)
2439 {
2440 if (hdsp->control_register & HDSP_XLRBreakoutCable) {
2441 return 1;
2442 }
2443 return 0;
2444 }
2445
2446 static int hdsp_set_xlr_breakout_cable(hdsp_t *hdsp, int mode)
2447 {
2448 if (mode) {
2449 hdsp->control_register |= HDSP_XLRBreakoutCable;
2450 } else {
2451 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2452 }
2453 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2454 return 0;
2455 }
2456
2457 static int snd_hdsp_info_xlr_breakout_cable(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2458 {
2459 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2460 uinfo->count = 1;
2461 uinfo->value.integer.min = 0;
2462 uinfo->value.integer.max = 1;
2463 return 0;
2464 }
2465
2466 static int snd_hdsp_get_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2467 {
2468 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2469
2470 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2471 return 0;
2472 }
2473
2474 static int snd_hdsp_put_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2475 {
2476 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2477 int change;
2478 int val;
2479
2480 if (!snd_hdsp_use_is_exclusive(hdsp))
2481 return -EBUSY;
2482 val = ucontrol->value.integer.value[0] & 1;
2483 spin_lock_irq(&hdsp->lock);
2484 change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2485 hdsp_set_xlr_breakout_cable(hdsp, val);
2486 spin_unlock_irq(&hdsp->lock);
2487 return change;
2488 }
2489
2490 /* (De)activates old RME Analog Extension Board
2491 These are connected to the internal ADAT connector
2492 Switching this on desactivates external ADAT
2493 */
2494 #define HDSP_AEB(xname, xindex) \
2495 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2496 .name = xname, \
2497 .index = xindex, \
2498 .info = snd_hdsp_info_aeb, \
2499 .get = snd_hdsp_get_aeb, \
2500 .put = snd_hdsp_put_aeb \
2501 }
2502
2503 static int hdsp_aeb(hdsp_t *hdsp)
2504 {
2505 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
2506 return 1;
2507 }
2508 return 0;
2509 }
2510
2511 static int hdsp_set_aeb(hdsp_t *hdsp, int mode)
2512 {
2513 if (mode) {
2514 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2515 } else {
2516 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2517 }
2518 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2519 return 0;
2520 }
2521
2522 static int snd_hdsp_info_aeb(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2523 {
2524 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2525 uinfo->count = 1;
2526 uinfo->value.integer.min = 0;
2527 uinfo->value.integer.max = 1;
2528 return 0;
2529 }
2530
2531 static int snd_hdsp_get_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2532 {
2533 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2534
2535 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2536 return 0;
2537 }
2538
2539 static int snd_hdsp_put_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2540 {
2541 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2542 int change;
2543 int val;
2544
2545 if (!snd_hdsp_use_is_exclusive(hdsp))
2546 return -EBUSY;
2547 val = ucontrol->value.integer.value[0] & 1;
2548 spin_lock_irq(&hdsp->lock);
2549 change = (int)val != hdsp_aeb(hdsp);
2550 hdsp_set_aeb(hdsp, val);
2551 spin_unlock_irq(&hdsp->lock);
2552 return change;
2553 }
2554
2555 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2556 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2557 .name = xname, \
2558 .index = xindex, \
2559 .info = snd_hdsp_info_pref_sync_ref, \
2560 .get = snd_hdsp_get_pref_sync_ref, \
2561 .put = snd_hdsp_put_pref_sync_ref \
2562 }
2563
2564 static int hdsp_pref_sync_ref(hdsp_t *hdsp)
2565 {
2566 /* Notice that this looks at the requested sync source,
2567 not the one actually in use.
2568 */
2569
2570 switch (hdsp->control_register & HDSP_SyncRefMask) {
2571 case HDSP_SyncRef_ADAT1:
2572 return HDSP_SYNC_FROM_ADAT1;
2573 case HDSP_SyncRef_ADAT2:
2574 return HDSP_SYNC_FROM_ADAT2;
2575 case HDSP_SyncRef_ADAT3:
2576 return HDSP_SYNC_FROM_ADAT3;
2577 case HDSP_SyncRef_SPDIF:
2578 return HDSP_SYNC_FROM_SPDIF;
2579 case HDSP_SyncRef_WORD:
2580 return HDSP_SYNC_FROM_WORD;
2581 case HDSP_SyncRef_ADAT_SYNC:
2582 return HDSP_SYNC_FROM_ADAT_SYNC;
2583 default:
2584 return HDSP_SYNC_FROM_WORD;
2585 }
2586 return 0;
2587 }
2588
2589 static int hdsp_set_pref_sync_ref(hdsp_t *hdsp, int pref)
2590 {
2591 hdsp->control_register &= ~HDSP_SyncRefMask;
2592 switch (pref) {
2593 case HDSP_SYNC_FROM_ADAT1:
2594 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2595 break;
2596 case HDSP_SYNC_FROM_ADAT2:
2597 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2598 break;
2599 case HDSP_SYNC_FROM_ADAT3:
2600 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2601 break;
2602 case HDSP_SYNC_FROM_SPDIF:
2603 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2604 break;
2605 case HDSP_SYNC_FROM_WORD:
2606 hdsp->control_register |= HDSP_SyncRef_WORD;
2607 break;
2608 case HDSP_SYNC_FROM_ADAT_SYNC:
2609 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2610 break;
2611 default:
2612 return -1;
2613 }
2614 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2615 return 0;
2616 }
2617
2618 static int snd_hdsp_info_pref_sync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2619 {
2620 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2621 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2622
2623 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2624 uinfo->count = 1;
2625
2626 switch (hdsp->io_type) {
2627 case Digiface:
2628 case H9652:
2629 uinfo->value.enumerated.items = 6;
2630 break;
2631 case Multiface:
2632 uinfo->value.enumerated.items = 4;
2633 break;
2634 case H9632:
2635 uinfo->value.enumerated.items = 3;
2636 break;
2637 default:
2638 uinfo->value.enumerated.items = 0;
2639 break;
2640 }
2641
2642 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2643 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2644 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2645 return 0;
2646 }
2647
2648 static int snd_hdsp_get_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2649 {
2650 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2651
2652 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2653 return 0;
2654 }
2655
2656 static int snd_hdsp_put_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2657 {
2658 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2659 int change, max;
2660 unsigned int val;
2661
2662 if (!snd_hdsp_use_is_exclusive(hdsp))
2663 return -EBUSY;
2664
2665 switch (hdsp->io_type) {
2666 case Digiface:
2667 case H9652:
2668 max = 6;
2669 break;
2670 case Multiface:
2671 max = 4;
2672 break;
2673 case H9632:
2674 max = 3;
2675 break;
2676 default:
2677 return -EIO;
2678 }
2679
2680 val = ucontrol->value.enumerated.item[0] % max;
2681 spin_lock_irq(&hdsp->lock);
2682 change = (int)val != hdsp_pref_sync_ref(hdsp);
2683 hdsp_set_pref_sync_ref(hdsp, val);
2684 spin_unlock_irq(&hdsp->lock);
2685 return change;
2686 }
2687
2688 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2689 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2690 .name = xname, \
2691 .index = xindex, \
2692 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2693 .info = snd_hdsp_info_autosync_ref, \
2694 .get = snd_hdsp_get_autosync_ref, \
2695 }
2696
2697 static int hdsp_autosync_ref(hdsp_t *hdsp)
2698 {
2699 /* This looks at the autosync selected sync reference */
2700 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2701
2702 switch (status2 & HDSP_SelSyncRefMask) {
2703 case HDSP_SelSyncRef_WORD:
2704 return HDSP_AUTOSYNC_FROM_WORD;
2705 case HDSP_SelSyncRef_ADAT_SYNC:
2706 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2707 case HDSP_SelSyncRef_SPDIF:
2708 return HDSP_AUTOSYNC_FROM_SPDIF;
2709 case HDSP_SelSyncRefMask:
2710 return HDSP_AUTOSYNC_FROM_NONE;
2711 case HDSP_SelSyncRef_ADAT1:
2712 return HDSP_AUTOSYNC_FROM_ADAT1;
2713 case HDSP_SelSyncRef_ADAT2:
2714 return HDSP_AUTOSYNC_FROM_ADAT2;
2715 case HDSP_SelSyncRef_ADAT3:
2716 return HDSP_AUTOSYNC_FROM_ADAT3;
2717 default:
2718 return HDSP_AUTOSYNC_FROM_WORD;
2719 }
2720 return 0;
2721 }
2722
2723 static int snd_hdsp_info_autosync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2724 {
2725 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2726
2727 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2728 uinfo->count = 1;
2729 uinfo->value.enumerated.items = 7;
2730 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2731 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2732 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2733 return 0;
2734 }
2735
2736 static int snd_hdsp_get_autosync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2737 {
2738 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2739
2740 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2741 return 0;
2742 }
2743
2744 #define HDSP_PASSTHRU(xname, xindex) \
2745 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2746 .name = xname, \
2747 .index = xindex, \
2748 .info = snd_hdsp_info_passthru, \
2749 .put = snd_hdsp_put_passthru, \
2750 .get = snd_hdsp_get_passthru \
2751 }
2752
2753 static int snd_hdsp_info_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
2754 {
2755 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2756 uinfo->count = 1;
2757 uinfo->value.integer.min = 0;
2758 uinfo->value.integer.max = 1;
2759 return 0;
2760 }
2761
2762 static int snd_hdsp_get_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2763 {
2764 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2765
2766 spin_lock_irq(&hdsp->lock);
2767 ucontrol->value.integer.value[0] = hdsp->passthru;
2768 spin_unlock_irq(&hdsp->lock);
2769 return 0;
2770 }
2771
2772 static int snd_hdsp_put_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2773 {
2774 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2775 int change;
2776 unsigned int val;
2777 int err = 0;
2778
2779 if (!snd_hdsp_use_is_exclusive(hdsp))
2780 return -EBUSY;
2781
2782 val = ucontrol->value.integer.value[0] & 1;
2783 spin_lock_irq(&hdsp->lock);
2784 change = (ucontrol->value.integer.value[0] != hdsp->passthru);
2785 if (change)
2786 err = hdsp_set_passthru(hdsp, val);
2787 spin_unlock_irq(&hdsp->lock);
2788 return err ? err : change;
2789 }
2790
2791 #define HDSP_LINE_OUT(xname, xindex) \
2792 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2793 .name = xname, \
2794 .index = xindex, \
2795 .info = snd_hdsp_info_line_out, \
2796 .get = snd_hdsp_get_line_out, \
2797 .put = snd_hdsp_put_line_out \
2798 }
2799
2800 static int hdsp_line_out(hdsp_t *hdsp)
2801 {
2802 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2803 }
2804
2805 static int hdsp_set_line_output(hdsp_t *hdsp, int out)
2806 {
2807 if (out) {
2808 hdsp->control_register |= HDSP_LineOut;
2809 } else {
2810 hdsp->control_register &= ~HDSP_LineOut;
2811 }
2812 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2813 return 0;
2814 }
2815
2816 static int snd_hdsp_info_line_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2817 {
2818 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2819 uinfo->count = 1;
2820 uinfo->value.integer.min = 0;
2821 uinfo->value.integer.max = 1;
2822 return 0;
2823 }
2824
2825 static int snd_hdsp_get_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2826 {
2827 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2828
2829 spin_lock_irq(&hdsp->lock);
2830 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2831 spin_unlock_irq(&hdsp->lock);
2832 return 0;
2833 }
2834
2835 static int snd_hdsp_put_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2836 {
2837 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2838 int change;
2839 unsigned int val;
2840
2841 if (!snd_hdsp_use_is_exclusive(hdsp))
2842 return -EBUSY;
2843 val = ucontrol->value.integer.value[0] & 1;
2844 spin_lock_irq(&hdsp->lock);
2845 change = (int)val != hdsp_line_out(hdsp);
2846 hdsp_set_line_output(hdsp, val);
2847 spin_unlock_irq(&hdsp->lock);
2848 return change;
2849 }
2850
2851 #define HDSP_MIXER(xname, xindex) \
2852 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2853 .name = xname, \
2854 .index = xindex, \
2855 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2856 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2857 .info = snd_hdsp_info_mixer, \
2858 .get = snd_hdsp_get_mixer, \
2859 .put = snd_hdsp_put_mixer \
2860 }
2861
2862 static int snd_hdsp_info_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2863 {
2864 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2865 uinfo->count = 3;
2866 uinfo->value.integer.min = 0;
2867 uinfo->value.integer.max = 65536;
2868 uinfo->value.integer.step = 1;
2869 return 0;
2870 }
2871
2872 static int snd_hdsp_get_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2873 {
2874 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2875 int source;
2876 int destination;
2877 int addr;
2878
2879 source = ucontrol->value.integer.value[0];
2880 destination = ucontrol->value.integer.value[1];
2881
2882 if (source >= hdsp->max_channels) {
2883 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2884 } else {
2885 addr = hdsp_input_to_output_key(hdsp,source, destination);
2886 }
2887
2888 spin_lock_irq(&hdsp->lock);
2889 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2890 spin_unlock_irq(&hdsp->lock);
2891 return 0;
2892 }
2893
2894 static int snd_hdsp_put_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2895 {
2896 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2897 int change;
2898 int source;
2899 int destination;
2900 int gain;
2901 int addr;
2902
2903 if (!snd_hdsp_use_is_exclusive(hdsp))
2904 return -EBUSY;
2905
2906 source = ucontrol->value.integer.value[0];
2907 destination = ucontrol->value.integer.value[1];
2908
2909 if (source >= hdsp->max_channels) {
2910 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2911 } else {
2912 addr = hdsp_input_to_output_key(hdsp,source, destination);
2913 }
2914
2915 gain = ucontrol->value.integer.value[2];
2916
2917 spin_lock_irq(&hdsp->lock);
2918 change = gain != hdsp_read_gain(hdsp, addr);
2919 if (change)
2920 hdsp_write_gain(hdsp, addr, gain);
2921 spin_unlock_irq(&hdsp->lock);
2922 return change;
2923 }
2924
2925 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2926 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2927 .name = xname, \
2928 .index = xindex, \
2929 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2930 .info = snd_hdsp_info_sync_check, \
2931 .get = snd_hdsp_get_wc_sync_check \
2932 }
2933
2934 static int snd_hdsp_info_sync_check(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2935 {
2936 static char *texts[] = {"No Lock", "Lock", "Sync" };
2937 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2938 uinfo->count = 1;
2939 uinfo->value.enumerated.items = 3;
2940 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2941 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2942 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2943 return 0;
2944 }
2945
2946 static int hdsp_wc_sync_check(hdsp_t *hdsp)
2947 {
2948 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2949 if (status2 & HDSP_wc_lock) {
2950 if (status2 & HDSP_wc_sync) {
2951 return 2;
2952 } else {
2953 return 1;
2954 }
2955 } else {
2956 return 0;
2957 }
2958 return 0;
2959 }
2960
2961 static int snd_hdsp_get_wc_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2962 {
2963 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2964
2965 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2966 return 0;
2967 }
2968
2969 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2970 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2971 .name = xname, \
2972 .index = xindex, \
2973 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2974 .info = snd_hdsp_info_sync_check, \
2975 .get = snd_hdsp_get_spdif_sync_check \
2976 }
2977
2978 static int hdsp_spdif_sync_check(hdsp_t *hdsp)
2979 {
2980 int status = hdsp_read(hdsp, HDSP_statusRegister);
2981 if (status & HDSP_SPDIFErrorFlag) {
2982 return 0;
2983 } else {
2984 if (status & HDSP_SPDIFSync) {
2985 return 2;
2986 } else {
2987 return 1;
2988 }
2989 }
2990 return 0;
2991 }
2992
2993 static int snd_hdsp_get_spdif_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2994 {
2995 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2996
2997 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2998 return 0;
2999 }
3000
3001 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
3002 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3003 .name = xname, \
3004 .index = xindex, \
3005 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3006 .info = snd_hdsp_info_sync_check, \
3007 .get = snd_hdsp_get_adatsync_sync_check \
3008 }
3009
3010 static int hdsp_adatsync_sync_check(hdsp_t *hdsp)
3011 {
3012 int status = hdsp_read(hdsp, HDSP_statusRegister);
3013 if (status & HDSP_TimecodeLock) {
3014 if (status & HDSP_TimecodeSync) {
3015 return 2;
3016 } else {
3017 return 1;
3018 }
3019 } else {
3020 return 0;
3021 }
3022 }
3023
3024 static int snd_hdsp_get_adatsync_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3025 {
3026 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3027
3028 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3029 return 0;
3030 }
3031
3032 #define HDSP_ADAT_SYNC_CHECK \
3033 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3034 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3035 .info = snd_hdsp_info_sync_check, \
3036 .get = snd_hdsp_get_adat_sync_check \
3037 }
3038
3039 static int hdsp_adat_sync_check(hdsp_t *hdsp, int idx)
3040 {
3041 int status = hdsp_read(hdsp, HDSP_statusRegister);
3042
3043 if (status & (HDSP_Lock0>>idx)) {
3044 if (status & (HDSP_Sync0>>idx)) {
3045 return 2;
3046 } else {
3047 return 1;
3048 }
3049 } else {
3050 return 0;
3051 }
3052 }
3053
3054 static int snd_hdsp_get_adat_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3055 {
3056 int offset;
3057 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3058
3059 offset = ucontrol->id.index - 1;
3060 snd_assert(offset >= 0);
3061
3062 switch (hdsp->io_type) {
3063 case Digiface:
3064 case H9652:
3065 if (offset >= 3)
3066 return -EINVAL;
3067 break;
3068 case Multiface:
3069 case H9632:
3070 if (offset >= 1)
3071 return -EINVAL;
3072 break;
3073 default:
3074 return -EIO;
3075 }
3076
3077 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3078 return 0;
3079 }
3080
3081 static snd_kcontrol_new_t snd_hdsp_9632_controls[] = {
3082 HDSP_DA_GAIN("DA Gain", 0),
3083 HDSP_AD_GAIN("AD Gain", 0),
3084 HDSP_PHONE_GAIN("Phones Gain", 0),
3085 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0)
3086 };
3087
3088 static snd_kcontrol_new_t snd_hdsp_controls[] = {
3089 {
3090 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3091 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3092 .info = snd_hdsp_control_spdif_info,
3093 .get = snd_hdsp_control_spdif_get,
3094 .put = snd_hdsp_control_spdif_put,
3095 },
3096 {
3097 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3098 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3099 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3100 .info = snd_hdsp_control_spdif_stream_info,
3101 .get = snd_hdsp_control_spdif_stream_get,
3102 .put = snd_hdsp_control_spdif_stream_put,
3103 },
3104 {
3105 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3106 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3107 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3108 .info = snd_hdsp_control_spdif_mask_info,
3109 .get = snd_hdsp_control_spdif_mask_get,
3110 .private_value = IEC958_AES0_NONAUDIO |
3111 IEC958_AES0_PROFESSIONAL |
3112 IEC958_AES0_CON_EMPHASIS,
3113 },
3114 {
3115 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3116 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3117 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3118 .info = snd_hdsp_control_spdif_mask_info,
3119 .get = snd_hdsp_control_spdif_mask_get,
3120 .private_value = IEC958_AES0_NONAUDIO |
3121 IEC958_AES0_PROFESSIONAL |
3122 IEC958_AES0_PRO_EMPHASIS,
3123 },
3124 HDSP_MIXER("Mixer", 0),
3125 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3126 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3127 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3128 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3129 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3130 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3131 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3132 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3133 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3134 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3135 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3136 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3137 /* 'External Rate' complies with the alsa control naming scheme */
3138 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3139 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3140 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3141 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3142 HDSP_PASSTHRU("Passthru", 0),
3143 HDSP_LINE_OUT("Line Out", 0),
3144 };
3145
3146 static snd_kcontrol_new_t snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3147 static snd_kcontrol_new_t snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3148
3149 static int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp)
3150 {
3151 unsigned int idx;
3152 int err;
3153 snd_kcontrol_t *kctl;
3154
3155 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3156 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) {
3157 return err;
3158 }
3159 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3160 hdsp->spdif_ctl = kctl;
3161 }
3162
3163 /* ADAT SyncCheck status */
3164 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3165 snd_hdsp_adat_sync_check.index = 1;
3166 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3167 return err;
3168 }
3169 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3170 for (idx = 1; idx < 3; ++idx) {
3171 snd_hdsp_adat_sync_check.index = idx+1;
3172 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3173 return err;
3174 }
3175 }
3176 }
3177
3178 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3179 if (hdsp->io_type == H9632) {
3180 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3181 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) {
3182 return err;
3183 }
3184 }
3185 }
3186
3187 /* AEB control for H96xx card */
3188 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3189 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) {
3190 return err;
3191 }
3192 }
3193
3194 return 0;
3195 }
3196
3197 /*------------------------------------------------------------
3198 /proc interface
3199 ------------------------------------------------------------*/
3200
3201 static void
3202 snd_hdsp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
3203 {
3204 hdsp_t *hdsp = (hdsp_t *) entry->private_data;
3205 unsigned int status;
3206 unsigned int status2;
3207 char *pref_sync_ref;
3208 char *autosync_ref;
3209 char *system_clock_mode;
3210 char *clock_source;
3211 int x;
3212
3213 if (hdsp_check_for_iobox (hdsp)) {
3214 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3215 return;
3216 }
3217
3218 if (hdsp_check_for_firmware(hdsp)) {
3219 if (hdsp->state & HDSP_FirmwareCached) {
3220 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3221 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3222 return;
3223 }
3224 } else {
3225 snd_iprintf(buffer, "No firmware loaded nor cached, please upload firmware.\n");
3226 return;
3227 }
3228 }
3229
3230 status = hdsp_read(hdsp, HDSP_statusRegister);
3231 status2 = hdsp_read(hdsp, HDSP_status2Register);
3232
3233 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3234 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3235 hdsp->capture_buffer, hdsp->playback_buffer);
3236 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3237 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3238 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3239 snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3240 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3241 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3242 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3243
3244 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3245 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3246 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3247 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3248
3249 snd_iprintf(buffer, "\n");
3250
3251 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3252
3253 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3254 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3255 snd_iprintf(buffer, "Passthru: %s\n", hdsp->passthru ? "yes" : "no");
3256 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3257
3258 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3259
3260 snd_iprintf(buffer, "\n");
3261
3262
3263 switch (hdsp_clock_source(hdsp)) {
3264 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3265 clock_source = "AutoSync";
3266 break;
3267 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3268 clock_source = "Internal 32 kHz";
3269 break;
3270 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3271 clock_source = "Internal 44.1 kHz";
3272 break;
3273 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3274 clock_source = "Internal 48 kHz";
3275 break;
3276 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3277 clock_source = "Internal 64 kHz";
3278 break;
3279 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3280 clock_source = "Internal 88.2 kHz";
3281 break;
3282 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3283 clock_source = "Internal 96 kHz";
3284 break;
3285 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3286 clock_source = "Internal 128 kHz";
3287 break;
3288 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3289 clock_source = "Internal 176.4 kHz";
3290 break;
3291 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3292 clock_source = "Internal 192 kHz";
3293 break;
3294 default:
3295 clock_source = "Error";
3296 }
3297 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3298
3299 if (hdsp_system_clock_mode(hdsp)) {
3300 system_clock_mode = "Slave";
3301 } else {
3302 system_clock_mode = "Master";
3303 }
3304
3305 switch (hdsp_pref_sync_ref (hdsp)) {
3306 case HDSP_SYNC_FROM_WORD:
3307 pref_sync_ref = "Word Clock";
3308 break;
3309 case HDSP_SYNC_FROM_ADAT_SYNC:
3310 pref_sync_ref = "ADAT Sync";
3311 break;
3312 case HDSP_SYNC_FROM_SPDIF:
3313 pref_sync_ref = "SPDIF";
3314 break;
3315 case HDSP_SYNC_FROM_ADAT1:
3316 pref_sync_ref = "ADAT1";
3317 break;
3318 case HDSP_SYNC_FROM_ADAT2:
3319 pref_sync_ref = "ADAT2";
3320 break;
3321 case HDSP_SYNC_FROM_ADAT3:
3322 pref_sync_ref = "ADAT3";
3323 break;
3324 default:
3325 pref_sync_ref = "Word Clock";
3326 break;
3327 }
3328 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3329
3330 switch (hdsp_autosync_ref (hdsp)) {
3331 case HDSP_AUTOSYNC_FROM_WORD:
3332 autosync_ref = "Word Clock";
3333 break;
3334 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3335 autosync_ref = "ADAT Sync";
3336 break;
3337 case HDSP_AUTOSYNC_FROM_SPDIF:
3338 autosync_ref = "SPDIF";
3339 break;
3340 case HDSP_AUTOSYNC_FROM_NONE:
3341 autosync_ref = "None";
3342 break;
3343 case HDSP_AUTOSYNC_FROM_ADAT1:
3344 autosync_ref = "ADAT1";
3345 break;
3346 case HDSP_AUTOSYNC_FROM_ADAT2:
3347 autosync_ref = "ADAT2";
3348 break;
3349 case HDSP_AUTOSYNC_FROM_ADAT3:
3350 autosync_ref = "ADAT3";
3351 break;
3352 default:
3353 autosync_ref = "---";
3354 break;
3355 }
3356 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3357
3358 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3359
3360 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3361
3362 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3363
3364 snd_iprintf(buffer, "\n");
3365
3366 switch (hdsp_spdif_in(hdsp)) {
3367 case HDSP_SPDIFIN_OPTICAL:
3368 snd_iprintf(buffer, "IEC958 input: Optical\n");
3369 break;
3370 case HDSP_SPDIFIN_COAXIAL:
3371 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3372 break;
3373 case HDSP_SPDIFIN_INTERNAL:
3374 snd_iprintf(buffer, "IEC958 input: Internal\n");
3375 break;
3376 case HDSP_SPDIFIN_AES:
3377 snd_iprintf(buffer, "IEC958 input: AES\n");
3378 break;
3379 default:
3380 snd_iprintf(buffer, "IEC958 input: ???\n");
3381 break;
3382 }
3383
3384 if (hdsp->control_register & HDSP_SPDIFOpticalOut) {
3385 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3386 } else {
3387 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3388 }
3389
3390 if (hdsp->control_register & HDSP_SPDIFProfessional) {
3391 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3392 } else {
3393 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3394 }
3395
3396 if (hdsp->control_register & HDSP_SPDIFEmphasis) {
3397 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3398 } else {
3399 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3400 }
3401
3402 if (hdsp->control_register & HDSP_SPDIFNonAudio) {
3403 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3404 } else {
3405 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3406 }
3407 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) {
3408 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3409 } else {
3410 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3411 }
3412
3413 snd_iprintf(buffer, "\n");
3414
3415 /* Sync Check */
3416 x = status & HDSP_Sync0;
3417 if (status & HDSP_Lock0) {
3418 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3419 } else {
3420 snd_iprintf(buffer, "ADAT1: No Lock\n");
3421 }
3422
3423 switch (hdsp->io_type) {
3424 case Digiface:
3425 case H9652:
3426 x = status & HDSP_Sync1;
3427 if (status & HDSP_Lock1) {
3428 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3429 } else {
3430 snd_iprintf(buffer, "ADAT2: No Lock\n");
3431 }
3432 x = status & HDSP_Sync2;
3433 if (status & HDSP_Lock2) {
3434 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3435 } else {
3436 snd_iprintf(buffer, "ADAT3: No Lock\n");
3437 }
3438 default:
3439 /* relax */
3440 break;
3441 }
3442
3443 x = status & HDSP_SPDIFSync;
3444 if (status & HDSP_SPDIFErrorFlag) {
3445 snd_iprintf (buffer, "SPDIF: No Lock\n");
3446 } else {
3447 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3448 }
3449
3450 x = status2 & HDSP_wc_sync;
3451 if (status2 & HDSP_wc_lock) {
3452 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3453 } else {
3454 snd_iprintf (buffer, "Word Clock: No Lock\n");
3455 }
3456
3457 x = status & HDSP_TimecodeSync;
3458 if (status & HDSP_TimecodeLock) {
3459 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3460 } else {
3461 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3462 }
3463
3464 snd_iprintf(buffer, "\n");
3465
3466 /* Informations about H9632 specific controls */
3467 if (hdsp->io_type == H9632) {
3468 char *tmp;
3469
3470 switch (hdsp_ad_gain(hdsp)) {
3471 case 0:
3472 tmp = "-10 dBV";
3473 break;
3474 case 1:
3475 tmp = "+4 dBu";
3476 break;
3477 default:
3478 tmp = "Lo Gain";
3479 break;
3480 }
3481 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3482
3483 switch (hdsp_da_gain(hdsp)) {
3484 case 0:
3485 tmp = "Hi Gain";
3486 break;
3487 case 1:
3488 tmp = "+4 dBu";
3489 break;
3490 default:
3491 tmp = "-10 dBV";
3492 break;
3493 }
3494 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3495
3496 switch (hdsp_phone_gain(hdsp)) {
3497 case 0:
3498 tmp = "0 dB";
3499 break;
3500 case 1:
3501 tmp = "-6 dB";
3502 break;
3503 default:
3504 tmp = "-12 dB";
3505 break;
3506 }
3507 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3508
3509 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3510
3511 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
3512 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3513 } else {
3514 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3515 }
3516 snd_iprintf(buffer, "\n");
3517 }
3518
3519 }
3520
3521 static void __devinit snd_hdsp_proc_init(hdsp_t *hdsp)
3522 {
3523 snd_info_entry_t *entry;
3524
3525 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3526 snd_info_set_text_ops(entry, hdsp, 1024, snd_hdsp_proc_read);
3527 }
3528
3529 static void snd_hdsp_free_buffers(hdsp_t *hdsp)
3530 {
3531 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3532 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3533 }
3534
3535 static int __devinit snd_hdsp_initialize_memory(hdsp_t *hdsp)
3536 {
3537 unsigned long pb_bus, cb_bus;
3538
3539 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3540 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3541 if (hdsp->capture_dma_buf.area)
3542 snd_dma_free_pages(&hdsp->capture_dma_buf);
3543 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3544 return -ENOMEM;
3545 }
3546
3547 /* Align to bus-space 64K boundary */
3548
3549 cb_bus = (hdsp->capture_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3550 pb_bus = (hdsp->playback_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3551
3552 /* Tell the card where it is */
3553
3554 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3555 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3556
3557 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3558 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3559
3560 return 0;
3561 }
3562
3563 static int snd_hdsp_set_defaults(hdsp_t *hdsp)
3564 {
3565 unsigned int i;
3566
3567 /* ASSUMPTION: hdsp->lock is either held, or
3568 there is no need to hold it (e.g. during module
3569 initalization).
3570 */
3571
3572 /* set defaults:
3573
3574 SPDIF Input via Coax
3575 Master clock mode
3576 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3577 which implies 2 4096 sample, 32Kbyte periods).
3578 Enable line out.
3579 */
3580
3581 hdsp->control_register = HDSP_ClockModeMaster |
3582 HDSP_SPDIFInputCoaxial |
3583 hdsp_encode_latency(7) |
3584 HDSP_LineOut;
3585
3586
3587 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3588
3589 #ifdef SNDRV_BIG_ENDIAN
3590 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3591 #else
3592 hdsp->control2_register = 0;
3593 #endif
3594 if (hdsp->io_type == H9652) {
3595 snd_hdsp_9652_enable_mixer (hdsp);
3596 } else {
3597 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3598 }
3599
3600 hdsp_reset_hw_pointer(hdsp);
3601 hdsp_compute_period_size(hdsp);
3602
3603 /* silence everything */
3604
3605 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) {
3606 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3607 }
3608
3609 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3610 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) {
3611 return -EIO;
3612 }
3613 }
3614
3615 if ((hdsp->io_type != H9652) && line_outs_monitor[hdsp->dev]) {
3616
3617 int lineouts_base;
3618
3619 snd_printk ("sending all inputs and playback streams to line outs.\n");
3620
3621 /* route all inputs to the line outs for easy monitoring. send
3622 odd numbered channels to right, even to left.
3623 */
3624 if (hdsp->io_type == H9632) {
3625 /* this is the phones/analog output */
3626 lineouts_base = 10;
3627 } else {
3628 lineouts_base = 26;
3629 }
3630
3631 for (i = 0; i < hdsp->max_channels; i++) {
3632 if (i & 1) {
3633 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN) ||
3634 hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN)) {
3635 return -EIO;
3636 }
3637 } else {
3638 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN) ||
3639 hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN)) {
3640
3641 return -EIO;
3642 }
3643 }
3644 }
3645 }
3646
3647 hdsp->passthru = 0;
3648
3649 /* H9632 specific defaults */
3650 if (hdsp->io_type == H9632) {
3651 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3652 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3653 }
3654
3655 /* set a default rate so that the channel map is set up.
3656 */
3657
3658 hdsp_set_rate(hdsp, 48000, 1);
3659
3660 return 0;
3661 }
3662
3663 static void hdsp_midi_tasklet(unsigned long arg)
3664 {
3665 hdsp_t *hdsp = (hdsp_t *)arg;
3666
3667 if (hdsp->midi[0].pending) {
3668 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3669 }
3670 if (hdsp->midi[1].pending) {
3671 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3672 }
3673 }
3674
3675 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3676 {
3677 hdsp_t *hdsp = (hdsp_t *) dev_id;
3678 unsigned int status;
3679 int audio;
3680 int midi0;
3681 int midi1;
3682 unsigned int midi0status;
3683 unsigned int midi1status;
3684 int schedule = 0;
3685
3686 status = hdsp_read(hdsp, HDSP_statusRegister);
3687
3688 audio = status & HDSP_audioIRQPending;
3689 midi0 = status & HDSP_midi0IRQPending;
3690 midi1 = status & HDSP_midi1IRQPending;
3691
3692 if (!audio && !midi0 && !midi1) {
3693 return IRQ_NONE;
3694 }
3695
3696 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3697
3698 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3699 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3700
3701 if (audio) {
3702 if (hdsp->capture_substream) {
3703 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3704 }
3705
3706 if (hdsp->playback_substream) {
3707 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3708 }
3709 }
3710
3711 if (midi0 && midi0status) {
3712 /* we disable interrupts for this input until processing is done */
3713 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3714 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3715 hdsp->midi[0].pending = 1;
3716 schedule = 1;
3717 }
3718 if (midi1 && midi1status) {
3719 /* we disable interrupts for this input until processing is done */
3720 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3721 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3722 hdsp->midi[1].pending = 1;
3723 schedule = 1;
3724 }
3725 if (schedule)
3726 tasklet_hi_schedule(&hdsp->midi_tasklet);
3727 return IRQ_HANDLED;
3728 }
3729
3730 static snd_pcm_uframes_t snd_hdsp_hw_pointer(snd_pcm_substream_t *substream)
3731 {
3732 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3733 return hdsp_hw_pointer(hdsp);
3734 }
3735
3736 static char *hdsp_channel_buffer_location(hdsp_t *hdsp,
3737 int stream,
3738 int channel)
3739
3740 {
3741 int mapped_channel;
3742
3743 snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3744
3745 if ((mapped_channel = hdsp->channel_map[channel]) < 0) {
3746 return NULL;
3747 }
3748
3749 if (stream == SNDRV_PCM_STREAM_CAPTURE) {
3750 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3751 } else {
3752 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3753 }
3754 }
3755
3756 static int snd_hdsp_playback_copy(snd_pcm_substream_t *substream, int channel,
3757 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3758 {
3759 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3760 char *channel_buf;
3761
3762 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3763
3764 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3765 snd_assert(channel_buf != NULL, return -EIO);
3766 if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3767 return -EFAULT;
3768 return count;
3769 }
3770
3771 static int snd_hdsp_capture_copy(snd_pcm_substream_t *substream, int channel,
3772 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3773 {
3774 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3775 char *channel_buf;
3776
3777 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3778
3779 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3780 snd_assert(channel_buf != NULL, return -EIO);
3781 if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3782 return -EFAULT;
3783 return count;
3784 }
3785
3786 static int snd_hdsp_hw_silence(snd_pcm_substream_t *substream, int channel,
3787 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3788 {
3789 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3790 char *channel_buf;
3791
3792 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3793 snd_assert(channel_buf != NULL, return -EIO);
3794 memset(channel_buf + pos * 4, 0, count * 4);
3795 return count;
3796 }
3797
3798 static int snd_hdsp_reset(snd_pcm_substream_t *substream)
3799 {
3800 snd_pcm_runtime_t *runtime = substream->runtime;
3801 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3802 snd_pcm_substream_t *other;
3803 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3804 other = hdsp->capture_substream;
3805 else
3806 other = hdsp->playback_substream;
3807 if (hdsp->running)
3808 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3809 else
3810 runtime->status->hw_ptr = 0;
3811 if (other) {
3812 struct list_head *pos;
3813 snd_pcm_substream_t *s;
3814 snd_pcm_runtime_t *oruntime = other->runtime;
3815 snd_pcm_group_for_each(pos, substream) {
3816 s = snd_pcm_group_substream_entry(pos);
3817 if (s == other) {
3818 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3819 break;
3820 }
3821 }
3822 }
3823 return 0;
3824 }
3825
3826 static int snd_hdsp_hw_params(snd_pcm_substream_t *substream,
3827 snd_pcm_hw_params_t *params)
3828 {
3829 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3830 int err;
3831 pid_t this_pid;
3832 pid_t other_pid;
3833
3834 if (hdsp_check_for_iobox (hdsp)) {
3835 return -EIO;
3836 }
3837
3838 if (hdsp_check_for_firmware(hdsp)) {
3839 if (hdsp->state & HDSP_FirmwareCached) {
3840 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3841 snd_printk("Firmware loading from cache failed, please upload manually.\n");
3842 }
3843 } else {
3844 snd_printk("No firmware loaded nor cached, please upload firmware.\n");
3845 }
3846 return -EIO;
3847 }
3848
3849 spin_lock_irq(&hdsp->lock);
3850
3851 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3852 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3853 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3854 this_pid = hdsp->playback_pid;
3855 other_pid = hdsp->capture_pid;
3856 } else {
3857 this_pid = hdsp->capture_pid;
3858 other_pid = hdsp->playback_pid;
3859 }
3860
3861 if ((other_pid > 0) && (this_pid != other_pid)) {
3862
3863 /* The other stream is open, and not by the same
3864 task as this one. Make sure that the parameters
3865 that matter are the same.
3866 */
3867
3868 if (params_rate(params) != hdsp->system_sample_rate) {
3869 spin_unlock_irq(&hdsp->lock);
3870 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3871 return -EBUSY;
3872 }
3873
3874 if (params_period_size(params) != hdsp->period_bytes / 4) {
3875 spin_unlock_irq(&hdsp->lock);
3876 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3877 return -EBUSY;
3878 }
3879
3880 /* We're fine. */
3881
3882 spin_unlock_irq(&hdsp->lock);
3883 return 0;
3884
3885 } else {
3886 spin_unlock_irq(&hdsp->lock);
3887 }
3888
3889 /* how to make sure that the rate matches an externally-set one ?
3890 */
3891
3892 spin_lock_irq(&hdsp->lock);
3893 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3894 spin_unlock_irq(&hdsp->lock);
3895 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3896 return err;
3897 } else {
3898 spin_unlock_irq(&hdsp->lock);
3899 }
3900
3901 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3902 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3903 return err;
3904 }
3905
3906 return 0;
3907 }
3908
3909 static int snd_hdsp_channel_info(snd_pcm_substream_t *substream,
3910 snd_pcm_channel_info_t *info)
3911 {
3912 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3913 int mapped_channel;
3914
3915 snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3916
3917 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) {
3918 return -EINVAL;
3919 }
3920
3921 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
3922 info->first = 0;
3923 info->step = 32;
3924 return 0;
3925 }
3926
3927 static int snd_hdsp_ioctl(snd_pcm_substream_t *substream,
3928 unsigned int cmd, void *arg)
3929 {
3930 switch (cmd) {
3931 case SNDRV_PCM_IOCTL1_RESET:
3932 {
3933 return snd_hdsp_reset(substream);
3934 }
3935 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3936 {
3937 snd_pcm_channel_info_t *info = arg;
3938 return snd_hdsp_channel_info(substream, info);
3939 }
3940 default:
3941 break;
3942 }
3943
3944 return snd_pcm_lib_ioctl(substream, cmd, arg);
3945 }
3946
3947 static int snd_hdsp_trigger(snd_pcm_substream_t *substream, int cmd)
3948 {
3949 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3950 snd_pcm_substream_t *other;
3951 int running;
3952
3953 if (hdsp_check_for_iobox (hdsp)) {
3954 return -EIO;
3955 }
3956
3957 if (hdsp_check_for_firmware(hdsp)) {
3958 if (hdsp->state & HDSP_FirmwareCached) {
3959 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3960 snd_printk("Firmware loading from cache failed, please upload manually.\n");
3961 }
3962 } else {
3963 snd_printk("No firmware loaded nor cached, please upload firmware.\n");
3964 }
3965 return -EIO;
3966 }
3967
3968 spin_lock(&hdsp->lock);
3969 running = hdsp->running;
3970 switch (cmd) {
3971 case SNDRV_PCM_TRIGGER_START:
3972 running |= 1 << substream->stream;
3973 break;
3974 case SNDRV_PCM_TRIGGER_STOP:
3975 running &= ~(1 << substream->stream);
3976 break;
3977 default:
3978 snd_BUG();
3979 spin_unlock(&hdsp->lock);
3980 return -EINVAL;
3981 }
3982 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3983 other = hdsp->capture_substream;
3984 else
3985 other = hdsp->playback_substream;
3986
3987 if (other) {
3988 struct list_head *pos;
3989 snd_pcm_substream_t *s;
3990 snd_pcm_group_for_each(pos, substream) {
3991 s = snd_pcm_group_substream_entry(pos);
3992 if (s == other) {
3993 snd_pcm_trigger_done(s, substream);
3994 if (cmd == SNDRV_PCM_TRIGGER_START)
3995 running |= 1 << s->stream;
3996 else
3997 running &= ~(1 << s->stream);
3998 goto _ok;
3999 }
4000 }
4001 if (cmd == SNDRV_PCM_TRIGGER_START) {
4002 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4003 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4004 hdsp_silence_playback(hdsp);
4005 } else {
4006 if (running &&
4007 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4008 hdsp_silence_playback(hdsp);
4009 }
4010 } else {
4011 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4012 hdsp_silence_playback(hdsp);
4013 }
4014 _ok:
4015 snd_pcm_trigger_done(substream, substream);
4016 if (!hdsp->running && running)
4017 hdsp_start_audio(hdsp);
4018 else if (hdsp->running && !running)
4019 hdsp_stop_audio(hdsp);
4020 hdsp->running = running;
4021 spin_unlock(&hdsp->lock);
4022
4023 return 0;
4024 }
4025
4026 static int snd_hdsp_prepare(snd_pcm_substream_t *substream)
4027 {
4028 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4029 int result = 0;
4030
4031 if (hdsp_check_for_iobox (hdsp)) {
4032 return -EIO;
4033 }
4034
4035 if (hdsp_check_for_firmware(hdsp)) {
4036 if (hdsp->state & HDSP_FirmwareCached) {
4037 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4038 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4039 }
4040 } else {
4041 snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4042 }
4043 return -EIO;
4044 }
4045
4046 spin_lock_irq(&hdsp->lock);
4047 if (!hdsp->running)
4048 hdsp_reset_hw_pointer(hdsp);
4049 spin_unlock_irq(&hdsp->lock);
4050 return result;
4051 }
4052
4053 static snd_pcm_hardware_t snd_hdsp_playback_subinfo =
4054 {
4055 .info = (SNDRV_PCM_INFO_MMAP |
4056 SNDRV_PCM_INFO_MMAP_VALID |
4057 SNDRV_PCM_INFO_NONINTERLEAVED |
4058 SNDRV_PCM_INFO_SYNC_START |
4059 SNDRV_PCM_INFO_DOUBLE),
4060 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4061 .rates = (SNDRV_PCM_RATE_32000 |
4062 SNDRV_PCM_RATE_44100 |
4063 SNDRV_PCM_RATE_48000 |
4064 SNDRV_PCM_RATE_64000 |
4065 SNDRV_PCM_RATE_88200 |
4066 SNDRV_PCM_RATE_96000),
4067 .rate_min = 32000,
4068 .rate_max = 96000,
4069 .channels_min = 14,
4070 .channels_max = HDSP_MAX_CHANNELS,
4071 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4072 .period_bytes_min = (64 * 4) * 10,
4073 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4074 .periods_min = 2,
4075 .periods_max = 2,
4076 .fifo_size = 0
4077 };
4078
4079 static snd_pcm_hardware_t snd_hdsp_capture_subinfo =
4080 {
4081 .info = (SNDRV_PCM_INFO_MMAP |
4082 SNDRV_PCM_INFO_MMAP_VALID |
4083 SNDRV_PCM_INFO_NONINTERLEAVED |
4084 SNDRV_PCM_INFO_SYNC_START),
4085 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4086 .rates = (SNDRV_PCM_RATE_32000 |
4087 SNDRV_PCM_RATE_44100 |
4088 SNDRV_PCM_RATE_48000 |
4089 SNDRV_PCM_RATE_64000 |
4090 SNDRV_PCM_RATE_88200 |
4091 SNDRV_PCM_RATE_96000),
4092 .rate_min = 32000,
4093 .rate_max = 96000,
4094 .channels_min = 14,
4095 .channels_max = HDSP_MAX_CHANNELS,
4096 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4097 .period_bytes_min = (64 * 4) * 10,
4098 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4099 .periods_min = 2,
4100 .periods_max = 2,
4101 .fifo_size = 0
4102 };
4103
4104 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4105
4106 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_period_sizes = {
4107 .count = ARRAY_SIZE(hdsp_period_sizes),
4108 .list = hdsp_period_sizes,
4109 .mask = 0
4110 };
4111
4112 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4113
4114 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_9632_sample_rates = {
4115 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4116 .list = hdsp_9632_sample_rates,
4117 .mask = 0
4118 };
4119
4120 static int snd_hdsp_hw_rule_in_channels(snd_pcm_hw_params_t *params,
4121 snd_pcm_hw_rule_t *rule)
4122 {
4123 hdsp_t *hdsp = rule->private;
4124 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4125 if (hdsp->io_type == H9632) {
4126 unsigned int list[3];
4127 list[0] = hdsp->qs_in_channels;
4128 list[1] = hdsp->ds_in_channels;
4129 list[2] = hdsp->ss_in_channels;
4130 return snd_interval_list(c, 3, list, 0);
4131 } else {
4132 unsigned int list[2];
4133 list[0] = hdsp->ds_in_channels;
4134 list[1] = hdsp->ss_in_channels;
4135 return snd_interval_list(c, 2, list, 0);
4136 }
4137 }
4138
4139 static int snd_hdsp_hw_rule_out_channels(snd_pcm_hw_params_t *params,
4140 snd_pcm_hw_rule_t *rule)
4141 {
4142 unsigned int list[3];
4143 hdsp_t *hdsp = rule->private;
4144 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4145 if (hdsp->io_type == H9632) {
4146 list[0] = hdsp->qs_out_channels;
4147 list[1] = hdsp->ds_out_channels;
4148 list[2] = hdsp->ss_out_channels;
4149 return snd_interval_list(c, 3, list, 0);
4150 } else {
4151 list[0] = hdsp->ds_out_channels;
4152 list[1] = hdsp->ss_out_channels;
4153 }
4154 return snd_interval_list(c, 2, list, 0);
4155 }
4156
4157 static int snd_hdsp_hw_rule_in_channels_rate(snd_pcm_hw_params_t *params,
4158 snd_pcm_hw_rule_t *rule)
4159 {
4160 hdsp_t *hdsp = rule->private;
4161 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4162 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4163 if (r->min > 96000 && hdsp->io_type == H9632) {
4164 snd_interval_t t = {
4165 .min = hdsp->qs_in_channels,
4166 .max = hdsp->qs_in_channels,
4167 .integer = 1,
4168 };
4169 return snd_interval_refine(c, &t);
4170 } else if (r->min > 48000 && r->max <= 96000) {
4171 snd_interval_t t = {
4172 .min = hdsp->ds_in_channels,
4173 .max = hdsp->ds_in_channels,
4174 .integer = 1,
4175 };
4176 return snd_interval_refine(c, &t);
4177 } else if (r->max < 64000) {
4178 snd_interval_t t = {
4179 .min = hdsp->ss_in_channels,
4180 .max = hdsp->ss_in_channels,
4181 .integer = 1,
4182 };
4183 return snd_interval_refine(c, &t);
4184 }
4185 return 0;
4186 }
4187
4188 static int snd_hdsp_hw_rule_out_channels_rate(snd_pcm_hw_params_t *params,
4189 snd_pcm_hw_rule_t *rule)
4190 {
4191 hdsp_t *hdsp = rule->private;
4192 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4193 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4194 if (r->min > 96000 && hdsp->io_type == H9632) {
4195 snd_interval_t t = {
4196 .min = hdsp->qs_out_channels,
4197 .max = hdsp->qs_out_channels,
4198 .integer = 1,
4199 };
4200 return snd_interval_refine(c, &t);
4201 } else if (r->min > 48000 && r->max <= 96000) {
4202 snd_interval_t t = {
4203 .min = hdsp->ds_out_channels,
4204 .max = hdsp->ds_out_channels,
4205 .integer = 1,
4206 };
4207 return snd_interval_refine(c, &t);
4208 } else if (r->max < 64000) {
4209 snd_interval_t t = {
4210 .min = hdsp->ss_out_channels,
4211 .max = hdsp->ss_out_channels,
4212 .integer = 1,
4213 };
4214 return snd_interval_refine(c, &t);
4215 }
4216 return 0;
4217 }
4218
4219 static int snd_hdsp_hw_rule_rate_out_channels(snd_pcm_hw_params_t *params,
4220 snd_pcm_hw_rule_t *rule)
4221 {
4222 hdsp_t *hdsp = rule->private;
4223 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4224 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4225 if (c->min >= hdsp->ss_out_channels) {
4226 snd_interval_t t = {
4227 .min = 32000,
4228 .max = 48000,
4229 .integer = 1,
4230 };
4231 return snd_interval_refine(r, &t);
4232 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4233 snd_interval_t t = {
4234 .min = 128000,
4235 .max = 192000,
4236 .integer = 1,
4237 };
4238 return snd_interval_refine(r, &t);
4239 } else if (c->max <= hdsp->ds_out_channels) {
4240 snd_interval_t t = {
4241 .min = 64000,
4242 .max = 96000,
4243 .integer = 1,
4244 };
4245 return snd_interval_refine(r, &t);
4246 }
4247 return 0;
4248 }
4249
4250 static int snd_hdsp_hw_rule_rate_in_channels(snd_pcm_hw_params_t *params,
4251 snd_pcm_hw_rule_t *rule)
4252 {
4253 hdsp_t *hdsp = rule->private;
4254 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4255 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4256 if (c->min >= hdsp->ss_in_channels) {
4257 snd_interval_t t = {
4258 .min = 32000,
4259 .max = 48000,
4260 .integer = 1,
4261 };
4262 return snd_interval_refine(r, &t);
4263 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4264 snd_interval_t t = {
4265 .min = 128000,
4266 .max = 192000,
4267 .integer = 1,
4268 };
4269 return snd_interval_refine(r, &t);
4270 } else if (c->max <= hdsp->ds_in_channels) {
4271 snd_interval_t t = {
4272 .min = 64000,
4273 .max = 96000,
4274 .integer = 1,
4275 };
4276 return snd_interval_refine(r, &t);
4277 }
4278 return 0;
4279 }
4280
4281 static int snd_hdsp_playback_open(snd_pcm_substream_t *substream)
4282 {
4283 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4284 snd_pcm_runtime_t *runtime = substream->runtime;
4285
4286 if (hdsp_check_for_iobox (hdsp)) {
4287 return -EIO;
4288 }
4289
4290 if (hdsp_check_for_firmware(hdsp)) {
4291 if (hdsp->state & HDSP_FirmwareCached) {
4292 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4293 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4294 }
4295 } else {
4296 snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4297 }
4298 return -EIO;
4299 }
4300
4301 spin_lock_irq(&hdsp->lock);
4302
4303 snd_pcm_set_sync(substream);
4304
4305 runtime->hw = snd_hdsp_playback_subinfo;
4306 runtime->dma_area = hdsp->playback_buffer;
4307 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4308
4309 if (hdsp->capture_substream == NULL) {
4310 hdsp_stop_audio(hdsp);
4311 hdsp_set_thru(hdsp, -1, 0);
4312 }
4313
4314 hdsp->playback_pid = current->pid;
4315 hdsp->playback_substream = substream;
4316
4317 spin_unlock_irq(&hdsp->lock);
4318
4319 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4320 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4321 if (hdsp->io_type == H9632) {
4322 runtime->hw.channels_min = hdsp->qs_out_channels;
4323 runtime->hw.channels_max = hdsp->ss_out_channels;
4324 runtime->hw.rate_max = 192000;
4325 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4326 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4327 }
4328
4329 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4330 snd_hdsp_hw_rule_out_channels, hdsp,
4331 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4332 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4333 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4334 SNDRV_PCM_HW_PARAM_RATE, -1);
4335 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4336 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4337 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4338
4339 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4340 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4341 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4342 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4343 return 0;
4344 }
4345
4346 static int snd_hdsp_playback_release(snd_pcm_substream_t *substream)
4347 {
4348 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4349
4350 spin_lock_irq(&hdsp->lock);
4351
4352 hdsp->playback_pid = -1;
4353 hdsp->playback_substream = NULL;
4354
4355 spin_unlock_irq(&hdsp->lock);
4356
4357 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4358 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4359 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4360 return 0;
4361 }
4362
4363
4364 static int snd_hdsp_capture_open(snd_pcm_substream_t *substream)
4365 {
4366 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4367 snd_pcm_runtime_t *runtime = substream->runtime;
4368
4369 if (hdsp_check_for_iobox (hdsp)) {
4370 return -EIO;
4371 }
4372
4373 if (hdsp_check_for_firmware(hdsp)) {
4374 if (hdsp->state & HDSP_FirmwareCached) {
4375 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4376 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4377 }
4378 } else {
4379 snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4380 }
4381 return -EIO;
4382 }
4383
4384 spin_lock_irq(&hdsp->lock);
4385
4386 snd_pcm_set_sync(substream);
4387
4388 runtime->hw = snd_hdsp_capture_subinfo;
4389 runtime->dma_area = hdsp->capture_buffer;
4390 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4391
4392 if (hdsp->playback_substream == NULL) {
4393 hdsp_stop_audio(hdsp);
4394 hdsp_set_thru(hdsp, -1, 0);
4395 }
4396
4397 hdsp->capture_pid = current->pid;
4398 hdsp->capture_substream = substream;
4399
4400 spin_unlock_irq(&hdsp->lock);
4401
4402 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4403 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4404 if (hdsp->io_type == H9632) {
4405 runtime->hw.channels_min = hdsp->qs_in_channels;
4406 runtime->hw.channels_max = hdsp->ss_in_channels;
4407 runtime->hw.rate_max = 192000;
4408 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4409 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4410 }
4411 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4412 snd_hdsp_hw_rule_in_channels, hdsp,
4413 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4414 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4415 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4416 SNDRV_PCM_HW_PARAM_RATE, -1);
4417 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4418 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4419 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4420 return 0;
4421 }
4422
4423 static int snd_hdsp_capture_release(snd_pcm_substream_t *substream)
4424 {
4425 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4426
4427 spin_lock_irq(&hdsp->lock);
4428
4429 hdsp->capture_pid = -1;
4430 hdsp->capture_substream = NULL;
4431
4432 spin_unlock_irq(&hdsp->lock);
4433 return 0;
4434 }
4435
4436 static int snd_hdsp_hwdep_dummy_op(snd_hwdep_t *hw, struct file *file)
4437 {
4438 /* we have nothing to initialize but the call is required */
4439 return 0;
4440 }
4441
4442
4443 /* helper functions for copying meter values */
4444 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4445 {
4446 u32 val = readl(src);
4447 return copy_to_user(dest, &val, 4);
4448 }
4449
4450 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4451 {
4452 u32 rms_low, rms_high;
4453 u64 rms;
4454 rms_low = readl(src_low);
4455 rms_high = readl(src_high);
4456 rms = ((u64)rms_high << 32) | rms_low;
4457 return copy_to_user(dest, &rms, 8);
4458 }
4459
4460 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4461 {
4462 u32 rms_low, rms_high;
4463 u64 rms;
4464 rms_low = readl(src_low) & 0xffffff00;
4465 rms_high = readl(src_high) & 0xffffff00;
4466 rms = ((u64)rms_high << 32) | rms_low;
4467 return copy_to_user(dest, &rms, 8);
4468 }
4469
4470 static int hdsp_9652_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4471 {
4472 int doublespeed = 0;
4473 int i, j, channels, ofs;
4474
4475 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4476 doublespeed = 1;
4477 channels = doublespeed ? 14 : 26;
4478 for (i = 0, j = 0; i < 26; ++i) {
4479 if (doublespeed && (i & 4))
4480 continue;
4481 ofs = HDSP_9652_peakBase - j * 4;
4482 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4483 return -EFAULT;
4484 ofs -= channels * 4;
4485 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4486 return -EFAULT;
4487 ofs -= channels * 4;
4488 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4489 return -EFAULT;
4490 ofs = HDSP_9652_rmsBase + j * 8;
4491 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4492 hdsp->iobase + ofs + 4))
4493 return -EFAULT;
4494 ofs += channels * 8;
4495 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4496 hdsp->iobase + ofs + 4))
4497 return -EFAULT;
4498 ofs += channels * 8;
4499 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4500 hdsp->iobase + ofs + 4))
4501 return -EFAULT;
4502 j++;
4503 }
4504 return 0;
4505 }
4506
4507 static int hdsp_9632_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4508 {
4509 int i, j;
4510 hdsp_9632_meters_t __iomem *m;
4511 int doublespeed = 0;
4512
4513 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4514 doublespeed = 1;
4515 m = (hdsp_9632_meters_t __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4516 for (i = 0, j = 0; i < 16; ++i, ++j) {
4517 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4518 return -EFAULT;
4519 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4520 return -EFAULT;
4521 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4522 return -EFAULT;
4523 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4524 &m->input_rms_high[j]))
4525 return -EFAULT;
4526 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4527 &m->playback_rms_high[j]))
4528 return -EFAULT;
4529 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4530 &m->output_rms_high[j]))
4531 return -EFAULT;
4532 if (doublespeed && i == 3) i += 4;
4533 }
4534 return 0;
4535 }
4536
4537 static int hdsp_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4538 {
4539 int i;
4540
4541 for (i = 0; i < 26; i++) {
4542 if (copy_u32_le(&peak_rms->playback_peaks[i],
4543 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4544 return -EFAULT;
4545 if (copy_u32_le(&peak_rms->input_peaks[i],
4546 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4547 return -EFAULT;
4548 }
4549 for (i = 0; i < 28; i++) {
4550 if (copy_u32_le(&peak_rms->output_peaks[i],
4551 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4552 return -EFAULT;
4553 }
4554 for (i = 0; i < 26; ++i) {
4555 if (copy_u64_le(&peak_rms->playback_rms[i],
4556 hdsp->iobase + HDSP_playbackRmsLevel + i * 8,
4557 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4))
4558 return -EFAULT;
4559 if (copy_u64_le(&peak_rms->input_rms[i],
4560 hdsp->iobase + HDSP_inputRmsLevel + i * 8,
4561 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4))
4562 return -EFAULT;
4563 }
4564 return 0;
4565 }
4566
4567 static int snd_hdsp_hwdep_ioctl(snd_hwdep_t *hw, struct file *file, unsigned int cmd, unsigned long arg)
4568 {
4569 hdsp_t *hdsp = (hdsp_t *)hw->private_data;
4570 void __user *argp = (void __user *)arg;
4571
4572 switch (cmd) {
4573 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4574 hdsp_peak_rms_t __user *peak_rms = (hdsp_peak_rms_t __user *)arg;
4575
4576 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4577 snd_printk(KERN_ERR "firmware needs to be uploaded to the card.\n");
4578 return -EINVAL;
4579 }
4580
4581 switch (hdsp->io_type) {
4582 case H9652:
4583 return hdsp_9652_get_peak(hdsp, peak_rms);
4584 case H9632:
4585 return hdsp_9632_get_peak(hdsp, peak_rms);
4586 default:
4587 return hdsp_get_peak(hdsp, peak_rms);
4588 }
4589 }
4590 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4591 hdsp_config_info_t info;
4592 unsigned long flags;
4593 int i;
4594
4595 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4596 snd_printk("Firmware needs to be uploaded to the card.\n");
4597 return -EINVAL;
4598 }
4599 spin_lock_irqsave(&hdsp->lock, flags);
4600 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4601 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4602 if (hdsp->io_type != H9632) {
4603 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4604 }
4605 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4606 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) {
4607 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4608 }
4609 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4610 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4611 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4612 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4613 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4614 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4615 info.system_sample_rate = hdsp->system_sample_rate;
4616 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4617 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4618 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4619 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4620 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4621 info.passthru = (unsigned char)hdsp->passthru;
4622 if (hdsp->io_type == H9632) {
4623 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4624 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4625 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4626 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4627
4628 }
4629 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
4630 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4631 }
4632 spin_unlock_irqrestore(&hdsp->lock, flags);
4633 if (copy_to_user(argp, &info, sizeof(info)))
4634 return -EFAULT;
4635 break;
4636 }
4637 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4638 hdsp_9632_aeb_t h9632_aeb;
4639
4640 if (hdsp->io_type != H9632) return -EINVAL;
4641 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4642 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4643 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4644 return -EFAULT;
4645 break;
4646 }
4647 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4648 hdsp_version_t hdsp_version;
4649 int err;
4650
4651 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4652 if (hdsp->io_type == Undefined) {
4653 if ((err = hdsp_get_iobox_version(hdsp)) < 0) {
4654 return err;
4655 }
4656 }
4657 hdsp_version.io_type = hdsp->io_type;
4658 hdsp_version.firmware_rev = hdsp->firmware_rev;
4659 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) {
4660 return -EFAULT;
4661 }
4662 break;
4663 }
4664 #ifndef HDSP_FW_LOADER
4665 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4666 hdsp_firmware_t __user *firmware;
4667 u32 __user *firmware_data;
4668 int err;
4669
4670 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4671 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4672 if (hdsp->io_type == Undefined) return -EINVAL;
4673
4674 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4675 return -EBUSY;
4676
4677 snd_printk("initializing firmware upload\n");
4678 firmware = (hdsp_firmware_t __user *)argp;
4679
4680 if (get_user(firmware_data, &firmware->firmware_data)) {
4681 return -EFAULT;
4682 }
4683
4684 if (hdsp_check_for_iobox (hdsp)) {
4685 return -EIO;
4686 }
4687
4688 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0) {
4689 return -EFAULT;
4690 }
4691
4692 hdsp->state |= HDSP_FirmwareCached;
4693
4694 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) {
4695 return err;
4696 }
4697
4698 if (!(hdsp->state & HDSP_InitializationComplete)) {
4699 snd_hdsp_initialize_channels(hdsp);
4700
4701 snd_hdsp_initialize_midi_flush(hdsp);
4702
4703 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4704 snd_printk("error creating alsa devices\n");
4705 return err;
4706 }
4707 }
4708 break;
4709 }
4710 #endif
4711 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4712 hdsp_mixer_t __user *mixer = (hdsp_mixer_t __user *)argp;
4713 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4714 return -EFAULT;
4715 break;
4716 }
4717 default:
4718 return -EINVAL;
4719 }
4720 return 0;
4721 }
4722
4723 static snd_pcm_ops_t snd_hdsp_playback_ops = {
4724 .open = snd_hdsp_playback_open,
4725 .close = snd_hdsp_playback_release,
4726 .ioctl = snd_hdsp_ioctl,
4727 .hw_params = snd_hdsp_hw_params,
4728 .prepare = snd_hdsp_prepare,
4729 .trigger = snd_hdsp_trigger,
4730 .pointer = snd_hdsp_hw_pointer,
4731 .copy = snd_hdsp_playback_copy,
4732 .silence = snd_hdsp_hw_silence,
4733 };
4734
4735 static snd_pcm_ops_t snd_hdsp_capture_ops = {
4736 .open = snd_hdsp_capture_open,
4737 .close = snd_hdsp_capture_release,
4738 .ioctl = snd_hdsp_ioctl,
4739 .hw_params = snd_hdsp_hw_params,
4740 .prepare = snd_hdsp_prepare,
4741 .trigger = snd_hdsp_trigger,
4742 .pointer = snd_hdsp_hw_pointer,
4743 .copy = snd_hdsp_capture_copy,
4744 };
4745
4746 static int __devinit snd_hdsp_create_hwdep(snd_card_t *card,
4747 hdsp_t *hdsp)
4748 {
4749 snd_hwdep_t *hw;
4750 int err;
4751
4752 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4753 return err;
4754
4755 hdsp->hwdep = hw;
4756 hw->private_data = hdsp;
4757 strcpy(hw->name, "HDSP hwdep interface");
4758
4759 hw->ops.open = snd_hdsp_hwdep_dummy_op;
4760 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4761 hw->ops.release = snd_hdsp_hwdep_dummy_op;
4762
4763 return 0;
4764 }
4765
4766 static int snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp)
4767 {
4768 snd_pcm_t *pcm;
4769 int err;
4770
4771 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4772 return err;
4773
4774 hdsp->pcm = pcm;
4775 pcm->private_data = hdsp;
4776 strcpy(pcm->name, hdsp->card_name);
4777
4778 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4779 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4780
4781 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4782
4783 return 0;
4784 }
4785
4786 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp)
4787 {
4788 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4789 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4790 }
4791
4792 static int snd_hdsp_enable_io (hdsp_t *hdsp)
4793 {
4794 int i;
4795
4796 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4797 return -EIO;
4798 }
4799
4800 for (i = 0; i < hdsp->max_channels; ++i) {
4801 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4802 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4803 }
4804
4805 return 0;
4806 }
4807
4808 static void snd_hdsp_initialize_channels(hdsp_t *hdsp)
4809 {
4810 int status, aebi_channels, aebo_channels;
4811
4812 switch (hdsp->io_type) {
4813 case Digiface:
4814 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4815 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4816 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4817 break;
4818
4819 case H9652:
4820 hdsp->card_name = "RME Hammerfall HDSP 9652";
4821 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4822 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4823 break;
4824
4825 case H9632:
4826 status = hdsp_read(hdsp, HDSP_statusRegister);
4827 /* HDSP_AEBx bits are low when AEB are connected */
4828 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4829 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4830 hdsp->card_name = "RME Hammerfall HDSP 9632";
4831 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4832 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4833 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4834 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4835 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4836 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4837 break;
4838
4839 case Multiface:
4840 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4841 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4842 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4843 break;
4844
4845 default:
4846 /* should never get here */
4847 break;
4848 }
4849 }
4850
4851 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp)
4852 {
4853 snd_hdsp_flush_midi_input (hdsp, 0);
4854 snd_hdsp_flush_midi_input (hdsp, 1);
4855 }
4856
4857 static int snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp)
4858 {
4859 int err;
4860
4861 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4862 snd_printk("Error creating pcm interface\n");
4863 return err;
4864 }
4865
4866
4867 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4868 snd_printk("Error creating first midi interface\n");
4869 return err;
4870 }
4871
4872
4873 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4874 snd_printk("Error creating second midi interface\n");
4875 return err;
4876 }
4877
4878 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4879 snd_printk("Error creating ctl interface\n");
4880 return err;
4881 }
4882
4883 snd_hdsp_proc_init(hdsp);
4884
4885 hdsp->system_sample_rate = -1;
4886 hdsp->playback_pid = -1;
4887 hdsp->capture_pid = -1;
4888 hdsp->capture_substream = NULL;
4889 hdsp->playback_substream = NULL;
4890
4891 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4892 snd_printk("Error setting default values\n");
4893 return err;
4894 }
4895
4896 if (!(hdsp->state & HDSP_InitializationComplete)) {
4897 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4898 hdsp->port, hdsp->irq);
4899
4900 if ((err = snd_card_register(card)) < 0) {
4901 snd_printk("error registering card\n");
4902 return err;
4903 }
4904 hdsp->state |= HDSP_InitializationComplete;
4905 }
4906
4907 return 0;
4908 }
4909
4910 #ifdef HDSP_FW_LOADER
4911 /* load firmware via hotplug fw loader */
4912 static int __devinit hdsp_request_fw_loader(hdsp_t *hdsp)
4913 {
4914 const char *fwfile;
4915 const struct firmware *fw;
4916 int err;
4917
4918 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4919 return 0;
4920 if (hdsp->io_type == Undefined) {
4921 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4922 return err;
4923 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4924 return 0;
4925 }
4926 if (hdsp_check_for_iobox (hdsp))
4927 return -EIO;
4928
4929 /* caution: max length of firmware filename is 30! */
4930 switch (hdsp->io_type) {
4931 case Multiface:
4932 if (hdsp->firmware_rev == 0xa)
4933 fwfile = "multiface_firmware.bin";
4934 else
4935 fwfile = "multiface_firmware_rev11.bin";
4936 break;
4937 case Digiface:
4938 if (hdsp->firmware_rev == 0xa)
4939 fwfile = "digiface_firmware.bin";
4940 else
4941 fwfile = "digiface_firmware_rev11.bin";
4942 break;
4943 default:
4944 snd_printk(KERN_ERR "hdsp: invalid io_type %d\n", hdsp->io_type);
4945 return -EINVAL;
4946 }
4947
4948 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
4949 snd_printk(KERN_ERR "hdsp: cannot load firmware %s\n", fwfile);
4950 return -ENOENT;
4951 }
4952 if (fw->size < sizeof(hdsp->firmware_cache)) {
4953 snd_printk(KERN_ERR "hdsp: too short firmware size %d (expected %d)\n",
4954 (int)fw->size, (int)sizeof(hdsp->firmware_cache));
4955 release_firmware(fw);
4956 return -EINVAL;
4957 }
4958 #ifdef SNDRV_BIG_ENDIAN
4959 {
4960 int i;
4961 u32 *src = (void *)fw->data;
4962 for (i = 0; i < ARRAY_SIZE(hdsp->firmware_cache); i++, src++)
4963 hdsp->firmware_cache[i] = ((*src & 0x000000ff) << 16) |
4964 ((*src & 0x0000ff00) << 8) |
4965 ((*src & 0x00ff0000) >> 8) |
4966 ((*src & 0xff000000) >> 16);
4967 }
4968 #else
4969 memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache));
4970 #endif
4971 release_firmware(fw);
4972
4973 hdsp->state |= HDSP_FirmwareCached;
4974
4975 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4976 return err;
4977
4978 if (!(hdsp->state & HDSP_InitializationComplete)) {
4979 snd_hdsp_initialize_channels(hdsp);
4980 snd_hdsp_initialize_midi_flush(hdsp);
4981 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4982 snd_printk("error creating alsa devices\n");
4983 return err;
4984 }
4985 }
4986 return 0;
4987 }
4988 #endif
4989
4990 static int __devinit snd_hdsp_create(snd_card_t *card,
4991 hdsp_t *hdsp,
4992 int precise_ptr)
4993 {
4994 struct pci_dev *pci = hdsp->pci;
4995 int err;
4996 int is_9652 = 0;
4997 int is_9632 = 0;
4998
4999 hdsp->irq = -1;
5000 hdsp->state = 0;
5001 hdsp->midi[0].rmidi = NULL;
5002 hdsp->midi[1].rmidi = NULL;
5003 hdsp->midi[0].input = NULL;
5004 hdsp->midi[1].input = NULL;
5005 hdsp->midi[0].output = NULL;
5006 hdsp->midi[1].output = NULL;
5007 spin_lock_init(&hdsp->midi[0].lock);
5008 spin_lock_init(&hdsp->midi[1].lock);
5009 hdsp->iobase = NULL;
5010 hdsp->control_register = 0;
5011 hdsp->control2_register = 0;
5012 hdsp->io_type = Undefined;
5013 hdsp->max_channels = 26;
5014
5015 hdsp->card = card;
5016
5017 spin_lock_init(&hdsp->lock);
5018
5019 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5020
5021 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5022
5023 /* From Martin Bjoernsen :
5024 "It is important that the card's latency timer register in
5025 the PCI configuration space is set to a value much larger
5026 than 0 by the computer's BIOS or the driver.
5027 The windows driver always sets this 8 bit register [...]
5028 to its maximum 255 to avoid problems with some computers."
5029 */
5030 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5031
5032 strcpy(card->driver, "H-DSP");
5033 strcpy(card->mixername, "Xilinx FPGA");
5034
5035 switch (hdsp->firmware_rev & 0xff) {
5036 case 0xa:
5037 case 0xb:
5038 case 0x32:
5039 hdsp->card_name = "RME Hammerfall DSP";
5040 break;
5041
5042 case 0x64:
5043 case 0x65:
5044 case 0x68:
5045 hdsp->card_name = "RME HDSP 9652";
5046 is_9652 = 1;
5047 break;
5048 case 0x96:
5049 case 0x97:
5050 hdsp->card_name = "RME HDSP 9632";
5051 hdsp->max_channels = 16;
5052 is_9632 = 1;
5053 break;
5054 default:
5055 return -ENODEV;
5056 }
5057
5058 if ((err = pci_enable_device(pci)) < 0) {
5059 return err;
5060 }
5061
5062 pci_set_master(hdsp->pci);
5063
5064 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5065 return err;
5066 hdsp->port = pci_resource_start(pci, 0);
5067 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5068 snd_printk("unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5069 return -EBUSY;
5070 }
5071
5072 if (request_irq(pci->irq, snd_hdsp_interrupt, SA_INTERRUPT|SA_SHIRQ, "hdsp", (void *)hdsp)) {
5073 snd_printk("unable to use IRQ %d\n", pci->irq);
5074 return -EBUSY;
5075 }
5076
5077 hdsp->irq = pci->irq;
5078 hdsp->precise_ptr = precise_ptr;
5079
5080 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) {
5081 return err;
5082 }
5083
5084 if (!is_9652 && !is_9632 && hdsp_check_for_iobox (hdsp)) {
5085 /* no iobox connected, we defer initialization */
5086 snd_printk("card initialization pending : waiting for firmware\n");
5087 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5088 return err;
5089 }
5090 return 0;
5091 }
5092
5093 if ((err = snd_hdsp_enable_io(hdsp)) != 0) {
5094 return err;
5095 }
5096
5097 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5098 #ifdef HDSP_FW_LOADER
5099 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5100 return err;
5101 #else
5102 snd_printk("card initialization pending : waiting for firmware\n");
5103 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5104 return err;
5105 }
5106 return 0;
5107 #endif
5108 }
5109
5110 snd_printk("Firmware already loaded, initializing card.\n");
5111
5112 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
5113 hdsp->io_type = Multiface;
5114 } else {
5115 hdsp->io_type = Digiface;
5116 }
5117
5118 if (is_9652) {
5119 hdsp->io_type = H9652;
5120 }
5121
5122 if (is_9632) {
5123 hdsp->io_type = H9632;
5124 }
5125
5126 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5127 return err;
5128 }
5129
5130 snd_hdsp_initialize_channels(hdsp);
5131 snd_hdsp_initialize_midi_flush(hdsp);
5132
5133 hdsp->state |= HDSP_FirmwareLoaded;
5134
5135 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) {
5136 return err;
5137 }
5138
5139 return 0;
5140 }
5141
5142 static int snd_hdsp_free(hdsp_t *hdsp)
5143 {
5144 if (hdsp->port) {
5145 /* stop the audio, and cancel all interrupts */
5146 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5147 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5148 }
5149
5150 if (hdsp->irq >= 0)
5151 free_irq(hdsp->irq, (void *)hdsp);
5152
5153 snd_hdsp_free_buffers(hdsp);
5154
5155 if (hdsp->iobase)
5156 iounmap(hdsp->iobase);
5157
5158 if (hdsp->port)
5159 pci_release_regions(hdsp->pci);
5160
5161 pci_disable_device(hdsp->pci);
5162 return 0;
5163 }
5164
5165 static void snd_hdsp_card_free(snd_card_t *card)
5166 {
5167 hdsp_t *hdsp = (hdsp_t *) card->private_data;
5168
5169 if (hdsp)
5170 snd_hdsp_free(hdsp);
5171 }
5172
5173 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5174 const struct pci_device_id *pci_id)
5175 {
5176 static int dev;
5177 hdsp_t *hdsp;
5178 snd_card_t *card;
5179 int err;
5180
5181 if (dev >= SNDRV_CARDS)
5182 return -ENODEV;
5183 if (!enable[dev]) {
5184 dev++;
5185 return -ENOENT;
5186 }
5187
5188 if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(hdsp_t))))
5189 return -ENOMEM;
5190
5191 hdsp = (hdsp_t *) card->private_data;
5192 card->private_free = snd_hdsp_card_free;
5193 hdsp->dev = dev;
5194 hdsp->pci = pci;
5195 snd_card_set_dev(card, &pci->dev);
5196
5197 if ((err = snd_hdsp_create(card, hdsp, precise_ptr[dev])) < 0) {
5198 snd_card_free(card);
5199 return err;
5200 }
5201
5202 strcpy(card->shortname, "Hammerfall DSP");
5203 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5204 hdsp->port, hdsp->irq);
5205
5206 if ((err = snd_card_register(card)) < 0) {
5207 snd_card_free(card);
5208 return err;
5209 }
5210 pci_set_drvdata(pci, card);
5211 dev++;
5212 return 0;
5213 }
5214
5215 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5216 {
5217 snd_card_free(pci_get_drvdata(pci));
5218 pci_set_drvdata(pci, NULL);
5219 }
5220
5221 static struct pci_driver driver = {
5222 .name = "RME Hammerfall DSP",
5223 .id_table = snd_hdsp_ids,
5224 .probe = snd_hdsp_probe,
5225 .remove = __devexit_p(snd_hdsp_remove),
5226 };
5227
5228 static int __init alsa_card_hdsp_init(void)
5229 {
5230 return pci_module_init(&driver);
5231 }
5232
5233 static void __exit alsa_card_hdsp_exit(void)
5234 {
5235 pci_unregister_driver(&driver);
5236 }
5237
5238 module_init(alsa_card_hdsp_init)
5239 module_exit(alsa_card_hdsp_exit)
5240
|
This page was automatically generated by the
LXR engine.
|