1 /*
2 * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
3 *
4 * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
5 * Pilo Chambert <pilo.c@wanadoo.fr>
6 *
7 * Thanks to : Anders Torger <torger@ludd.luth.se>,
8 * Henk Hesselink <henk@anda.nl>
9 * for writing the digi96-driver
10 * and RME for all informations.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * ****************************************************************************
28 *
29 * Note #1 "Sek'd models" ................................... martin 2002-12-07
30 *
31 * Identical soundcards by Sek'd were labeled:
32 * RME Digi 32 = Sek'd Prodif 32
33 * RME Digi 32 Pro = Sek'd Prodif 96
34 * RME Digi 32/8 = Sek'd Prodif Gold
35 *
36 * ****************************************************************************
37 *
38 * Note #2 "full duplex mode" ............................... martin 2002-12-07
39 *
40 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
41 * in this mode. Rec data and play data are using the same buffer therefore. At
42 * first you have got the playing bits in the buffer and then (after playing
43 * them) they were overwitten by the captured sound of the CS8412/14. Both
44 * modes (play/record) are running harmonically hand in hand in the same buffer
45 * and you have only one start bit plus one interrupt bit to control this
46 * paired action.
47 * This is opposite to the latter rme96 where playing and capturing is totally
48 * separated and so their full duplex mode is supported by alsa (using two
49 * start bits and two interrupts for two different buffers).
50 * But due to the wrong sequence of playing and capturing ALSA shows no solved
51 * full duplex support for the rme32 at the moment. That's bad, but I'm not
52 * able to solve it. Are you motivated enough to solve this problem now? Your
53 * patch would be welcome!
54 *
55 * ****************************************************************************
56 *
57 * "The story after the long seeking" -- tiwai
58 *
59 * Ok, the situation regarding the full duplex is now improved a bit.
60 * In the fullduplex mode (given by the module parameter), the hardware buffer
61 * is split to halves for read and write directions at the DMA pointer.
62 * That is, the half above the current DMA pointer is used for write, and
63 * the half below is used for read. To mangle this strange behavior, an
64 * software intermediate buffer is introduced. This is, of course, not good
65 * from the viewpoint of the data transfer efficiency. However, this allows
66 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
67 *
68 * ****************************************************************************
69 */
70
71
72 #include <sound/driver.h>
73 #include <linux/delay.h>
74 #include <linux/init.h>
75 #include <linux/interrupt.h>
76 #include <linux/pci.h>
77 #include <linux/slab.h>
78 #include <linux/moduleparam.h>
79
80 #include <sound/core.h>
81 #include <sound/info.h>
82 #include <sound/control.h>
83 #include <sound/pcm.h>
84 #include <sound/pcm_params.h>
85 #include <sound/pcm-indirect.h>
86 #include <sound/asoundef.h>
87 #include <sound/initval.h>
88
89 #include <asm/io.h>
90
91 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
92 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
93 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
94 static int fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
95
96 module_param_array(index, int, NULL, 0444);
97 MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
98 module_param_array(id, charp, NULL, 0444);
99 MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
100 module_param_array(enable, bool, NULL, 0444);
101 MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
102 module_param_array(fullduplex, bool, NULL, 0444);
103 MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
104 MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
105 MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
106 MODULE_LICENSE("GPL");
107 MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
108
109 /* Defines for RME Digi32 series */
110 #define RME32_SPDIF_NCHANNELS 2
111
112 /* Playback and capture buffer size */
113 #define RME32_BUFFER_SIZE 0x20000
114
115 /* IO area size */
116 #define RME32_IO_SIZE 0x30000
117
118 /* IO area offsets */
119 #define RME32_IO_DATA_BUFFER 0x0
120 #define RME32_IO_CONTROL_REGISTER 0x20000
121 #define RME32_IO_GET_POS 0x20000
122 #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
123 #define RME32_IO_RESET_POS 0x20100
124
125 /* Write control register bits */
126 #define RME32_WCR_START (1 << 0) /* startbit */
127 #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono
128 Setting the whole card to mono
129 doesn't seem to be very useful.
130 A software-solution can handle
131 full-duplex with one direction in
132 stereo and the other way in mono.
133 So, the hardware should work all
134 the time in stereo! */
135 #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */
136 #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */
137 #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */
138 #define RME32_WCR_FREQ_1 (1 << 5)
139 #define RME32_WCR_INP_0 (1 << 6) /* input switch */
140 #define RME32_WCR_INP_1 (1 << 7)
141 #define RME32_WCR_RESET (1 << 8) /* Reset address */
142 #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */
143 #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */
144 #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
145 #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */
146 #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */
147 #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */
148 #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */
149
150 #define RME32_WCR_BITPOS_FREQ_0 4
151 #define RME32_WCR_BITPOS_FREQ_1 5
152 #define RME32_WCR_BITPOS_INP_0 6
153 #define RME32_WCR_BITPOS_INP_1 7
154
155 /* Read control register bits */
156 #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
157 #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */
158 #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */
159 #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */
160 #define RME32_RCR_FREQ_1 (1 << 28)
161 #define RME32_RCR_FREQ_2 (1 << 29)
162 #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */
163 #define RME32_RCR_IRQ (1 << 31) /* interrupt */
164
165 #define RME32_RCR_BITPOS_F0 27
166 #define RME32_RCR_BITPOS_F1 28
167 #define RME32_RCR_BITPOS_F2 29
168
169 /* Input types */
170 #define RME32_INPUT_OPTICAL 0
171 #define RME32_INPUT_COAXIAL 1
172 #define RME32_INPUT_INTERNAL 2
173 #define RME32_INPUT_XLR 3
174
175 /* Clock modes */
176 #define RME32_CLOCKMODE_SLAVE 0
177 #define RME32_CLOCKMODE_MASTER_32 1
178 #define RME32_CLOCKMODE_MASTER_44 2
179 #define RME32_CLOCKMODE_MASTER_48 3
180
181 /* Block sizes in bytes */
182 #define RME32_BLOCK_SIZE 8192
183
184 /* Software intermediate buffer (max) size */
185 #define RME32_MID_BUFFER_SIZE (1024*1024)
186
187 /* Hardware revisions */
188 #define RME32_32_REVISION 192
189 #define RME32_328_REVISION_OLD 100
190 #define RME32_328_REVISION_NEW 101
191 #define RME32_PRO_REVISION_WITH_8412 192
192 #define RME32_PRO_REVISION_WITH_8414 150
193
194
195 /* PCI vendor/device ID's */
196 #ifndef PCI_VENDOR_ID_XILINX_RME
197 # define PCI_VENDOR_ID_XILINX_RME 0xea60
198 #endif
199 #ifndef PCI_DEVICE_ID_DIGI32
200 # define PCI_DEVICE_ID_DIGI32 0x9896
201 #endif
202 #ifndef PCI_DEVICE_ID_DIGI32_PRO
203 # define PCI_DEVICE_ID_DIGI32_PRO 0x9897
204 #endif
205 #ifndef PCI_DEVICE_ID_DIGI32_8
206 # define PCI_DEVICE_ID_DIGI32_8 0x9898
207 #endif
208
209 typedef struct snd_rme32 {
210 spinlock_t lock;
211 int irq;
212 unsigned long port;
213 void __iomem *iobase;
214
215 u32 wcreg; /* cached write control register value */
216 u32 wcreg_spdif; /* S/PDIF setup */
217 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
218 u32 rcreg; /* cached read control register value */
219
220 u8 rev; /* card revision number */
221
222 snd_pcm_substream_t *playback_substream;
223 snd_pcm_substream_t *capture_substream;
224
225 int playback_frlog; /* log2 of framesize */
226 int capture_frlog;
227
228 size_t playback_periodsize; /* in bytes, zero if not used */
229 size_t capture_periodsize; /* in bytes, zero if not used */
230
231 unsigned int fullduplex_mode;
232 int running;
233
234 snd_pcm_indirect_t playback_pcm;
235 snd_pcm_indirect_t capture_pcm;
236
237 snd_card_t *card;
238 snd_pcm_t *spdif_pcm;
239 snd_pcm_t *adat_pcm;
240 struct pci_dev *pci;
241 snd_kcontrol_t *spdif_ctl;
242 } rme32_t;
243
244 static struct pci_device_id snd_rme32_ids[] = {
245 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_DIGI32,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
247 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_DIGI32_8,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
249 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_DIGI32_PRO,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
251 {0,}
252 };
253
254 MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
255
256 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
257 #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
258
259 static int snd_rme32_playback_prepare(snd_pcm_substream_t * substream);
260
261 static int snd_rme32_capture_prepare(snd_pcm_substream_t * substream);
262
263 static int snd_rme32_pcm_trigger(snd_pcm_substream_t * substream, int cmd);
264
265 static void snd_rme32_proc_init(rme32_t * rme32);
266
267 static int snd_rme32_create_switches(snd_card_t * card, rme32_t * rme32);
268
269 static inline unsigned int snd_rme32_pcm_byteptr(rme32_t * rme32)
270 {
271 return (readl(rme32->iobase + RME32_IO_GET_POS)
272 & RME32_RCR_AUDIO_ADDR_MASK);
273 }
274
275 static int snd_rme32_ratecode(int rate)
276 {
277 switch (rate) {
278 case 32000: return SNDRV_PCM_RATE_32000;
279 case 44100: return SNDRV_PCM_RATE_44100;
280 case 48000: return SNDRV_PCM_RATE_48000;
281 case 64000: return SNDRV_PCM_RATE_64000;
282 case 88200: return SNDRV_PCM_RATE_88200;
283 case 96000: return SNDRV_PCM_RATE_96000;
284 }
285 return 0;
286 }
287
288 /* silence callback for halfduplex mode */
289 static int snd_rme32_playback_silence(snd_pcm_substream_t * substream, int channel, /* not used (interleaved data) */
290 snd_pcm_uframes_t pos,
291 snd_pcm_uframes_t count)
292 {
293 rme32_t *rme32 = snd_pcm_substream_chip(substream);
294 count <<= rme32->playback_frlog;
295 pos <<= rme32->playback_frlog;
296 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
297 return 0;
298 }
299
300 /* copy callback for halfduplex mode */
301 static int snd_rme32_playback_copy(snd_pcm_substream_t * substream, int channel, /* not used (interleaved data) */
302 snd_pcm_uframes_t pos,
303 void __user *src, snd_pcm_uframes_t count)
304 {
305 rme32_t *rme32 = snd_pcm_substream_chip(substream);
306 count <<= rme32->playback_frlog;
307 pos <<= rme32->playback_frlog;
308 if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
309 src, count))
310 return -EFAULT;
311 return 0;
312 }
313
314 /* copy callback for halfduplex mode */
315 static int snd_rme32_capture_copy(snd_pcm_substream_t * substream, int channel, /* not used (interleaved data) */
316 snd_pcm_uframes_t pos,
317 void __user *dst, snd_pcm_uframes_t count)
318 {
319 rme32_t *rme32 = snd_pcm_substream_chip(substream);
320 count <<= rme32->capture_frlog;
321 pos <<= rme32->capture_frlog;
322 if (copy_to_user_fromio(dst,
323 rme32->iobase + RME32_IO_DATA_BUFFER + pos,
324 count))
325 return -EFAULT;
326 return 0;
327 }
328
329 /*
330 * SPDIF I/O capabilites (half-duplex mode)
331 */
332 static snd_pcm_hardware_t snd_rme32_spdif_info = {
333 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
334 SNDRV_PCM_INFO_MMAP_VALID |
335 SNDRV_PCM_INFO_INTERLEAVED |
336 SNDRV_PCM_INFO_PAUSE |
337 SNDRV_PCM_INFO_SYNC_START),
338 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
339 SNDRV_PCM_FMTBIT_S32_LE),
340 .rates = (SNDRV_PCM_RATE_32000 |
341 SNDRV_PCM_RATE_44100 |
342 SNDRV_PCM_RATE_48000),
343 .rate_min = 32000,
344 .rate_max = 48000,
345 .channels_min = 2,
346 .channels_max = 2,
347 .buffer_bytes_max = RME32_BUFFER_SIZE,
348 .period_bytes_min = RME32_BLOCK_SIZE,
349 .period_bytes_max = RME32_BLOCK_SIZE,
350 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
351 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
352 .fifo_size = 0,
353 };
354
355 /*
356 * ADAT I/O capabilites (half-duplex mode)
357 */
358 static snd_pcm_hardware_t snd_rme32_adat_info =
359 {
360 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
361 SNDRV_PCM_INFO_MMAP_VALID |
362 SNDRV_PCM_INFO_INTERLEAVED |
363 SNDRV_PCM_INFO_PAUSE |
364 SNDRV_PCM_INFO_SYNC_START),
365 .formats= SNDRV_PCM_FMTBIT_S16_LE,
366 .rates = (SNDRV_PCM_RATE_44100 |
367 SNDRV_PCM_RATE_48000),
368 .rate_min = 44100,
369 .rate_max = 48000,
370 .channels_min = 8,
371 .channels_max = 8,
372 .buffer_bytes_max = RME32_BUFFER_SIZE,
373 .period_bytes_min = RME32_BLOCK_SIZE,
374 .period_bytes_max = RME32_BLOCK_SIZE,
375 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
376 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
377 .fifo_size = 0,
378 };
379
380 /*
381 * SPDIF I/O capabilites (full-duplex mode)
382 */
383 static snd_pcm_hardware_t snd_rme32_spdif_fd_info = {
384 .info = (SNDRV_PCM_INFO_MMAP |
385 SNDRV_PCM_INFO_MMAP_VALID |
386 SNDRV_PCM_INFO_INTERLEAVED |
387 SNDRV_PCM_INFO_PAUSE |
388 SNDRV_PCM_INFO_SYNC_START),
389 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
390 SNDRV_PCM_FMTBIT_S32_LE),
391 .rates = (SNDRV_PCM_RATE_32000 |
392 SNDRV_PCM_RATE_44100 |
393 SNDRV_PCM_RATE_48000),
394 .rate_min = 32000,
395 .rate_max = 48000,
396 .channels_min = 2,
397 .channels_max = 2,
398 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
399 .period_bytes_min = RME32_BLOCK_SIZE,
400 .period_bytes_max = RME32_BLOCK_SIZE,
401 .periods_min = 2,
402 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
403 .fifo_size = 0,
404 };
405
406 /*
407 * ADAT I/O capabilites (full-duplex mode)
408 */
409 static snd_pcm_hardware_t snd_rme32_adat_fd_info =
410 {
411 .info = (SNDRV_PCM_INFO_MMAP |
412 SNDRV_PCM_INFO_MMAP_VALID |
413 SNDRV_PCM_INFO_INTERLEAVED |
414 SNDRV_PCM_INFO_PAUSE |
415 SNDRV_PCM_INFO_SYNC_START),
416 .formats= SNDRV_PCM_FMTBIT_S16_LE,
417 .rates = (SNDRV_PCM_RATE_44100 |
418 SNDRV_PCM_RATE_48000),
419 .rate_min = 44100,
420 .rate_max = 48000,
421 .channels_min = 8,
422 .channels_max = 8,
423 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
424 .period_bytes_min = RME32_BLOCK_SIZE,
425 .period_bytes_max = RME32_BLOCK_SIZE,
426 .periods_min = 2,
427 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
428 .fifo_size = 0,
429 };
430
431 static void snd_rme32_reset_dac(rme32_t *rme32)
432 {
433 writel(rme32->wcreg | RME32_WCR_PD,
434 rme32->iobase + RME32_IO_CONTROL_REGISTER);
435 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
436 }
437
438 static int snd_rme32_playback_getrate(rme32_t * rme32)
439 {
440 int rate;
441
442 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
443 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
444 switch (rate) {
445 case 1:
446 rate = 32000;
447 break;
448 case 2:
449 rate = 44100;
450 break;
451 case 3:
452 rate = 48000;
453 break;
454 default:
455 return -1;
456 }
457 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
458 }
459
460 static int snd_rme32_capture_getrate(rme32_t * rme32, int *is_adat)
461 {
462 int n;
463
464 *is_adat = 0;
465 if (rme32->rcreg & RME32_RCR_LOCK) {
466 /* ADAT rate */
467 *is_adat = 1;
468 }
469 if (rme32->rcreg & RME32_RCR_ERF) {
470 return -1;
471 }
472
473 /* S/PDIF rate */
474 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
475 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
476 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
477
478 if (RME32_PRO_WITH_8414(rme32))
479 switch (n) { /* supporting the CS8414 */
480 case 0:
481 case 1:
482 case 2:
483 return -1;
484 case 3:
485 return 96000;
486 case 4:
487 return 88200;
488 case 5:
489 return 48000;
490 case 6:
491 return 44100;
492 case 7:
493 return 32000;
494 default:
495 return -1;
496 break;
497 }
498 else
499 switch (n) { /* supporting the CS8412 */
500 case 0:
501 return -1;
502 case 1:
503 return 48000;
504 case 2:
505 return 44100;
506 case 3:
507 return 32000;
508 case 4:
509 return 48000;
510 case 5:
511 return 44100;
512 case 6:
513 return 44056;
514 case 7:
515 return 32000;
516 default:
517 break;
518 }
519 return -1;
520 }
521
522 static int snd_rme32_playback_setrate(rme32_t * rme32, int rate)
523 {
524 int ds;
525
526 ds = rme32->wcreg & RME32_WCR_DS_BM;
527 switch (rate) {
528 case 32000:
529 rme32->wcreg &= ~RME32_WCR_DS_BM;
530 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
531 ~RME32_WCR_FREQ_1;
532 break;
533 case 44100:
534 rme32->wcreg &= ~RME32_WCR_DS_BM;
535 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
536 ~RME32_WCR_FREQ_0;
537 break;
538 case 48000:
539 rme32->wcreg &= ~RME32_WCR_DS_BM;
540 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
541 RME32_WCR_FREQ_1;
542 break;
543 case 64000:
544 if (rme32->pci->device != PCI_DEVICE_ID_DIGI32_PRO)
545 return -EINVAL;
546 rme32->wcreg |= RME32_WCR_DS_BM;
547 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
548 ~RME32_WCR_FREQ_1;
549 break;
550 case 88200:
551 if (rme32->pci->device != PCI_DEVICE_ID_DIGI32_PRO)
552 return -EINVAL;
553 rme32->wcreg |= RME32_WCR_DS_BM;
554 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
555 ~RME32_WCR_FREQ_0;
556 break;
557 case 96000:
558 if (rme32->pci->device != PCI_DEVICE_ID_DIGI32_PRO)
559 return -EINVAL;
560 rme32->wcreg |= RME32_WCR_DS_BM;
561 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
562 RME32_WCR_FREQ_1;
563 break;
564 default:
565 return -EINVAL;
566 }
567 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
568 (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
569 {
570 /* change to/from double-speed: reset the DAC (if available) */
571 snd_rme32_reset_dac(rme32);
572 } else {
573 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
574 }
575 return 0;
576 }
577
578 static int snd_rme32_setclockmode(rme32_t * rme32, int mode)
579 {
580 switch (mode) {
581 case RME32_CLOCKMODE_SLAVE:
582 /* AutoSync */
583 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
584 ~RME32_WCR_FREQ_1;
585 break;
586 case RME32_CLOCKMODE_MASTER_32:
587 /* Internal 32.0kHz */
588 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
589 ~RME32_WCR_FREQ_1;
590 break;
591 case RME32_CLOCKMODE_MASTER_44:
592 /* Internal 44.1kHz */
593 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
594 RME32_WCR_FREQ_1;
595 break;
596 case RME32_CLOCKMODE_MASTER_48:
597 /* Internal 48.0kHz */
598 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
599 RME32_WCR_FREQ_1;
600 break;
601 default:
602 return -EINVAL;
603 }
604 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
605 return 0;
606 }
607
608 static int snd_rme32_getclockmode(rme32_t * rme32)
609 {
610 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
611 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
612 }
613
614 static int snd_rme32_setinputtype(rme32_t * rme32, int type)
615 {
616 switch (type) {
617 case RME32_INPUT_OPTICAL:
618 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
619 ~RME32_WCR_INP_1;
620 break;
621 case RME32_INPUT_COAXIAL:
622 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
623 ~RME32_WCR_INP_1;
624 break;
625 case RME32_INPUT_INTERNAL:
626 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
627 RME32_WCR_INP_1;
628 break;
629 case RME32_INPUT_XLR:
630 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
631 RME32_WCR_INP_1;
632 break;
633 default:
634 return -EINVAL;
635 }
636 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
637 return 0;
638 }
639
640 static int snd_rme32_getinputtype(rme32_t * rme32)
641 {
642 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
643 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
644 }
645
646 static void
647 snd_rme32_setframelog(rme32_t * rme32, int n_channels, int is_playback)
648 {
649 int frlog;
650
651 if (n_channels == 2) {
652 frlog = 1;
653 } else {
654 /* assume 8 channels */
655 frlog = 3;
656 }
657 if (is_playback) {
658 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
659 rme32->playback_frlog = frlog;
660 } else {
661 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
662 rme32->capture_frlog = frlog;
663 }
664 }
665
666 static int snd_rme32_setformat(rme32_t * rme32, int format)
667 {
668 switch (format) {
669 case SNDRV_PCM_FORMAT_S16_LE:
670 rme32->wcreg &= ~RME32_WCR_MODE24;
671 break;
672 case SNDRV_PCM_FORMAT_S32_LE:
673 rme32->wcreg |= RME32_WCR_MODE24;
674 break;
675 default:
676 return -EINVAL;
677 }
678 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
679 return 0;
680 }
681
682 static int
683 snd_rme32_playback_hw_params(snd_pcm_substream_t * substream,
684 snd_pcm_hw_params_t * params)
685 {
686 int err, rate, dummy;
687 rme32_t *rme32 = snd_pcm_substream_chip(substream);
688 snd_pcm_runtime_t *runtime = substream->runtime;
689
690 if (rme32->fullduplex_mode) {
691 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
692 if (err < 0)
693 return err;
694 } else {
695 runtime->dma_area = (void *)(rme32->iobase + RME32_IO_DATA_BUFFER);
696 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
697 runtime->dma_bytes = RME32_BUFFER_SIZE;
698 }
699
700 spin_lock_irq(&rme32->lock);
701 if ((rme32->rcreg & RME32_RCR_KMODE) &&
702 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
703 /* AutoSync */
704 if ((int)params_rate(params) != rate) {
705 spin_unlock_irq(&rme32->lock);
706 return -EIO;
707 }
708 } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
709 spin_unlock_irq(&rme32->lock);
710 return err;
711 }
712 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
713 spin_unlock_irq(&rme32->lock);
714 return err;
715 }
716
717 snd_rme32_setframelog(rme32, params_channels(params), 1);
718 if (rme32->capture_periodsize != 0) {
719 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
720 spin_unlock_irq(&rme32->lock);
721 return -EBUSY;
722 }
723 }
724 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
725 /* S/PDIF setup */
726 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
727 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
728 rme32->wcreg |= rme32->wcreg_spdif_stream;
729 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
730 }
731 spin_unlock_irq(&rme32->lock);
732
733 return 0;
734 }
735
736 static int
737 snd_rme32_capture_hw_params(snd_pcm_substream_t * substream,
738 snd_pcm_hw_params_t * params)
739 {
740 int err, isadat, rate;
741 rme32_t *rme32 = snd_pcm_substream_chip(substream);
742 snd_pcm_runtime_t *runtime = substream->runtime;
743
744 if (rme32->fullduplex_mode) {
745 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
746 if (err < 0)
747 return err;
748 } else {
749 runtime->dma_area = (void *)rme32->iobase + RME32_IO_DATA_BUFFER;
750 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
751 runtime->dma_bytes = RME32_BUFFER_SIZE;
752 }
753
754 spin_lock_irq(&rme32->lock);
755 /* enable AutoSync for record-preparing */
756 rme32->wcreg |= RME32_WCR_AUTOSYNC;
757 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
758
759 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
760 spin_unlock_irq(&rme32->lock);
761 return err;
762 }
763 if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
764 spin_unlock_irq(&rme32->lock);
765 return err;
766 }
767 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
768 if ((int)params_rate(params) != rate) {
769 spin_unlock_irq(&rme32->lock);
770 return -EIO;
771 }
772 if ((isadat && runtime->hw.channels_min == 2) ||
773 (!isadat && runtime->hw.channels_min == 8)) {
774 spin_unlock_irq(&rme32->lock);
775 return -EIO;
776 }
777 }
778 /* AutoSync off for recording */
779 rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
780 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
781
782 snd_rme32_setframelog(rme32, params_channels(params), 0);
783 if (rme32->playback_periodsize != 0) {
784 if (params_period_size(params) << rme32->capture_frlog !=
785 rme32->playback_periodsize) {
786 spin_unlock_irq(&rme32->lock);
787 return -EBUSY;
788 }
789 }
790 rme32->capture_periodsize =
791 params_period_size(params) << rme32->capture_frlog;
792 spin_unlock_irq(&rme32->lock);
793
794 return 0;
795 }
796
797 static int snd_rme32_pcm_hw_free(snd_pcm_substream_t * substream)
798 {
799 rme32_t *rme32 = snd_pcm_substream_chip(substream);
800 if (! rme32->fullduplex_mode)
801 return 0;
802 return snd_pcm_lib_free_pages(substream);
803 }
804
805 static void snd_rme32_pcm_start(rme32_t * rme32, int from_pause)
806 {
807 if (!from_pause) {
808 writel(0, rme32->iobase + RME32_IO_RESET_POS);
809 }
810
811 rme32->wcreg |= RME32_WCR_START;
812 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
813 }
814
815 static void snd_rme32_pcm_stop(rme32_t * rme32, int to_pause)
816 {
817 /*
818 * Check if there is an unconfirmed IRQ, if so confirm it, or else
819 * the hardware will not stop generating interrupts
820 */
821 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
822 if (rme32->rcreg & RME32_RCR_IRQ) {
823 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
824 }
825 rme32->wcreg &= ~RME32_WCR_START;
826 if (rme32->wcreg & RME32_WCR_SEL)
827 rme32->wcreg |= RME32_WCR_MUTE;
828 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
829 if (! to_pause)
830 writel(0, rme32->iobase + RME32_IO_RESET_POS);
831 }
832
833 static irqreturn_t
834 snd_rme32_interrupt(int irq, void *dev_id, struct pt_regs *regs)
835 {
836 rme32_t *rme32 = (rme32_t *) dev_id;
837
838 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
839 if (!(rme32->rcreg & RME32_RCR_IRQ)) {
840 return IRQ_NONE;
841 } else {
842 if (rme32->capture_substream) {
843 snd_pcm_period_elapsed(rme32->capture_substream);
844 }
845 if (rme32->playback_substream) {
846 snd_pcm_period_elapsed(rme32->playback_substream);
847 }
848 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
849 }
850 return IRQ_HANDLED;
851 }
852
853 static unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
854
855
856 static snd_pcm_hw_constraint_list_t hw_constraints_period_bytes = {
857 .count = ARRAY_SIZE(period_bytes),
858 .list = period_bytes,
859 .mask = 0
860 };
861
862 static void snd_rme32_set_buffer_constraint(rme32_t *rme32, snd_pcm_runtime_t *runtime)
863 {
864 if (! rme32->fullduplex_mode) {
865 snd_pcm_hw_constraint_minmax(runtime,
866 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
867 RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
868 snd_pcm_hw_constraint_list(runtime, 0,
869 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
870 &hw_constraints_period_bytes);
871 }
872 }
873
874 static int snd_rme32_playback_spdif_open(snd_pcm_substream_t * substream)
875 {
876 int rate, dummy;
877 rme32_t *rme32 = snd_pcm_substream_chip(substream);
878 snd_pcm_runtime_t *runtime = substream->runtime;
879
880 snd_pcm_set_sync(substream);
881
882 spin_lock_irq(&rme32->lock);
883 if (rme32->playback_substream != NULL) {
884 spin_unlock_irq(&rme32->lock);
885 return -EBUSY;
886 }
887 rme32->wcreg &= ~RME32_WCR_ADAT;
888 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
889 rme32->playback_substream = substream;
890 spin_unlock_irq(&rme32->lock);
891
892 if (rme32->fullduplex_mode)
893 runtime->hw = snd_rme32_spdif_fd_info;
894 else
895 runtime->hw = snd_rme32_spdif_info;
896 if (rme32->pci->device == PCI_DEVICE_ID_DIGI32_PRO) {
897 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
898 runtime->hw.rate_max = 96000;
899 }
900 if ((rme32->rcreg & RME32_RCR_KMODE) &&
901 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
902 /* AutoSync */
903 runtime->hw.rates = snd_rme32_ratecode(rate);
904 runtime->hw.rate_min = rate;
905 runtime->hw.rate_max = rate;
906 }
907
908 snd_rme32_set_buffer_constraint(rme32, runtime);
909
910 rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
911 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
912 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
913 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
914 return 0;
915 }
916
917 static int snd_rme32_capture_spdif_open(snd_pcm_substream_t * substream)
918 {
919 int isadat, rate;
920 rme32_t *rme32 = snd_pcm_substream_chip(substream);
921 snd_pcm_runtime_t *runtime = substream->runtime;
922
923 snd_pcm_set_sync(substream);
924
925 spin_lock_irq(&rme32->lock);
926 if (rme32->capture_substream != NULL) {
927 spin_unlock_irq(&rme32->lock);
928 return -EBUSY;
929 }
930 rme32->capture_substream = substream;
931 spin_unlock_irq(&rme32->lock);
932
933 if (rme32->fullduplex_mode)
934 runtime->hw = snd_rme32_spdif_fd_info;
935 else
936 runtime->hw = snd_rme32_spdif_info;
937 if (RME32_PRO_WITH_8414(rme32)) {
938 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
939 runtime->hw.rate_max = 96000;
940 }
941 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
942 if (isadat) {
943 return -EIO;
944 }
945 runtime->hw.rates = snd_rme32_ratecode(rate);
946 runtime->hw.rate_min = rate;
947 runtime->hw.rate_max = rate;
948 }
949
950 snd_rme32_set_buffer_constraint(rme32, runtime);
951
952 return 0;
953 }
954
955 static int
956 snd_rme32_playback_adat_open(snd_pcm_substream_t *substream)
957 {
958 int rate, dummy;
959 rme32_t *rme32 = snd_pcm_substream_chip(substream);
960 snd_pcm_runtime_t *runtime = substream->runtime;
961
962 snd_pcm_set_sync(substream);
963
964 spin_lock_irq(&rme32->lock);
965 if (rme32->playback_substream != NULL) {
966 spin_unlock_irq(&rme32->lock);
967 return -EBUSY;
968 }
969 rme32->wcreg |= RME32_WCR_ADAT;
970 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
971 rme32->playback_substream = substream;
972 spin_unlock_irq(&rme32->lock);
973
974 if (rme32->fullduplex_mode)
975 runtime->hw = snd_rme32_adat_fd_info;
976 else
977 runtime->hw = snd_rme32_adat_info;
978 if ((rme32->rcreg & RME32_RCR_KMODE) &&
979 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
980 /* AutoSync */
981 runtime->hw.rates = snd_rme32_ratecode(rate);
982 runtime->hw.rate_min = rate;
983 runtime->hw.rate_max = rate;
984 }
985
986 snd_rme32_set_buffer_constraint(rme32, runtime);
987 return 0;
988 }
989
990 static int
991 snd_rme32_capture_adat_open(snd_pcm_substream_t *substream)
992 {
993 int isadat, rate;
994 rme32_t *rme32 = snd_pcm_substream_chip(substream);
995 snd_pcm_runtime_t *runtime = substream->runtime;
996
997 if (rme32->fullduplex_mode)
998 runtime->hw = snd_rme32_adat_fd_info;
999 else
1000 runtime->hw = snd_rme32_adat_info;
1001 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
1002 if (!isadat) {
1003 return -EIO;
1004 }
1005 runtime->hw.rates = snd_rme32_ratecode(rate);
1006 runtime->hw.rate_min = rate;
1007 runtime->hw.rate_max = rate;
1008 }
1009
1010 snd_pcm_set_sync(substream);
1011
1012 spin_lock_irq(&rme32->lock);
1013 if (rme32->capture_substream != NULL) {
1014 spin_unlock_irq(&rme32->lock);
1015 return -EBUSY;
1016 }
1017 rme32->capture_substream = substream;
1018 spin_unlock_irq(&rme32->lock);
1019
1020 snd_rme32_set_buffer_constraint(rme32, runtime);
1021 return 0;
1022 }
1023
1024 static int snd_rme32_playback_close(snd_pcm_substream_t * substream)
1025 {
1026 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1027 int spdif = 0;
1028
1029 spin_lock_irq(&rme32->lock);
1030 rme32->playback_substream = NULL;
1031 rme32->playback_periodsize = 0;
1032 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1033 spin_unlock_irq(&rme32->lock);
1034 if (spdif) {
1035 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1036 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1037 SNDRV_CTL_EVENT_MASK_INFO,
1038 &rme32->spdif_ctl->id);
1039 }
1040 return 0;
1041 }
1042
1043 static int snd_rme32_capture_close(snd_pcm_substream_t * substream)
1044 {
1045 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1046
1047 spin_lock_irq(&rme32->lock);
1048 rme32->capture_substream = NULL;
1049 rme32->capture_periodsize = 0;
1050 spin_unlock(&rme32->lock);
1051 return 0;
1052 }
1053
1054 static int snd_rme32_playback_prepare(snd_pcm_substream_t * substream)
1055 {
1056 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1057
1058 spin_lock_irq(&rme32->lock);
1059 if (rme32->fullduplex_mode) {
1060 memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1061 rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1062 rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1063 } else {
1064 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1065 }
1066 if (rme32->wcreg & RME32_WCR_SEL)
1067 rme32->wcreg &= ~RME32_WCR_MUTE;
1068 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1069 spin_unlock_irq(&rme32->lock);
1070 return 0;
1071 }
1072
1073 static int snd_rme32_capture_prepare(snd_pcm_substream_t * substream)
1074 {
1075 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1076
1077 spin_lock_irq(&rme32->lock);
1078 if (rme32->fullduplex_mode) {
1079 memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1080 rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1081 rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1082 rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1083 } else {
1084 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1085 }
1086 spin_unlock_irq(&rme32->lock);
1087 return 0;
1088 }
1089
1090 static int
1091 snd_rme32_pcm_trigger(snd_pcm_substream_t * substream, int cmd)
1092 {
1093 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1094 struct list_head *pos;
1095 snd_pcm_substream_t *s;
1096
1097 spin_lock(&rme32->lock);
1098 snd_pcm_group_for_each(pos, substream) {
1099 s = snd_pcm_group_substream_entry(pos);
1100 if (s != rme32->playback_substream &&
1101 s != rme32->capture_substream)
1102 continue;
1103 switch (cmd) {
1104 case SNDRV_PCM_TRIGGER_START:
1105 rme32->running |= (1 << s->stream);
1106 if (rme32->fullduplex_mode) {
1107 /* remember the current DMA position */
1108 if (s == rme32->playback_substream) {
1109 rme32->playback_pcm.hw_io =
1110 rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1111 } else {
1112 rme32->capture_pcm.hw_io =
1113 rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1114 }
1115 }
1116 break;
1117 case SNDRV_PCM_TRIGGER_STOP:
1118 rme32->running &= ~(1 << s->stream);
1119 break;
1120 }
1121 snd_pcm_trigger_done(s, substream);
1122 }
1123
1124 /* prefill playback buffer */
1125 if (cmd == SNDRV_PCM_TRIGGER_START && rme32->fullduplex_mode) {
1126 snd_pcm_group_for_each(pos, substream) {
1127 s = snd_pcm_group_substream_entry(pos);
1128 if (s == rme32->playback_substream) {
1129 s->ops->ack(s);
1130 break;
1131 }
1132 }
1133 }
1134
1135 switch (cmd) {
1136 case SNDRV_PCM_TRIGGER_START:
1137 if (rme32->running && ! RME32_ISWORKING(rme32))
1138 snd_rme32_pcm_start(rme32, 0);
1139 break;
1140 case SNDRV_PCM_TRIGGER_STOP:
1141 if (! rme32->running && RME32_ISWORKING(rme32))
1142 snd_rme32_pcm_stop(rme32, 0);
1143 break;
1144 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1145 if (rme32->running && RME32_ISWORKING(rme32))
1146 snd_rme32_pcm_stop(rme32, 1);
1147 break;
1148 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1149 if (rme32->running && ! RME32_ISWORKING(rme32))
1150 snd_rme32_pcm_start(rme32, 1);
1151 break;
1152 }
1153 spin_unlock(&rme32->lock);
1154 return 0;
1155 }
1156
1157 /* pointer callback for halfduplex mode */
1158 static snd_pcm_uframes_t
1159 snd_rme32_playback_pointer(snd_pcm_substream_t * substream)
1160 {
1161 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1162 return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1163 }
1164
1165 static snd_pcm_uframes_t
1166 snd_rme32_capture_pointer(snd_pcm_substream_t * substream)
1167 {
1168 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1169 return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1170 }
1171
1172
1173 /* ack and pointer callbacks for fullduplex mode */
1174 static void snd_rme32_pb_trans_copy(snd_pcm_substream_t *substream,
1175 snd_pcm_indirect_t *rec, size_t bytes)
1176 {
1177 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1178 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1179 substream->runtime->dma_area + rec->sw_data, bytes);
1180 }
1181
1182 static int snd_rme32_playback_fd_ack(snd_pcm_substream_t *substream)
1183 {
1184 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1185 snd_pcm_indirect_t *rec, *cprec;
1186 unsigned long flags;
1187
1188 rec = &rme32->playback_pcm;
1189 cprec = &rme32->capture_pcm;
1190 spin_lock_irqsave(&rme32->lock, flags);
1191 rec->hw_queue_size = RME32_BUFFER_SIZE;
1192 if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1193 rec->hw_queue_size -= cprec->hw_ready;
1194 spin_unlock_irqrestore(&rme32->lock, flags);
1195 snd_pcm_indirect_playback_transfer(substream, rec,
1196 snd_rme32_pb_trans_copy);
1197 return 0;
1198 }
1199
1200 static void snd_rme32_cp_trans_copy(snd_pcm_substream_t *substream,
1201 snd_pcm_indirect_t *rec, size_t bytes)
1202 {
1203 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1204 memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1205 rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1206 bytes);
1207 }
1208
1209 static int snd_rme32_capture_fd_ack(snd_pcm_substream_t *substream)
1210 {
1211 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1212 snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1213 snd_rme32_cp_trans_copy);
1214 return 0;
1215 }
1216
1217 static snd_pcm_uframes_t
1218 snd_rme32_playback_fd_pointer(snd_pcm_substream_t * substream)
1219 {
1220 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1221 return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1222 snd_rme32_pcm_byteptr(rme32));
1223 }
1224
1225 static snd_pcm_uframes_t
1226 snd_rme32_capture_fd_pointer(snd_pcm_substream_t * substream)
1227 {
1228 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1229 return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1230 snd_rme32_pcm_byteptr(rme32));
1231 }
1232
1233 /* for halfduplex mode */
1234 static snd_pcm_ops_t snd_rme32_playback_spdif_ops = {
1235 .open = snd_rme32_playback_spdif_open,
1236 .close = snd_rme32_playback_close,
1237 .ioctl = snd_pcm_lib_ioctl,
1238 .hw_params = snd_rme32_playback_hw_params,
1239 .hw_free = snd_rme32_pcm_hw_free,
1240 .prepare = snd_rme32_playback_prepare,
1241 .trigger = snd_rme32_pcm_trigger,
1242 .pointer = snd_rme32_playback_pointer,
1243 .copy = snd_rme32_playback_copy,
1244 .silence = snd_rme32_playback_silence,
1245 .mmap = snd_pcm_lib_mmap_iomem,
1246 };
1247
1248 static snd_pcm_ops_t snd_rme32_capture_spdif_ops = {
1249 .open = snd_rme32_capture_spdif_open,
1250 .close = snd_rme32_capture_close,
1251 .ioctl = snd_pcm_lib_ioctl,
1252 .hw_params = snd_rme32_capture_hw_params,
1253 .hw_free = snd_rme32_pcm_hw_free,
1254 .prepare = snd_rme32_capture_prepare,
1255 .trigger = snd_rme32_pcm_trigger,
1256 .pointer = snd_rme32_capture_pointer,
1257 .copy = snd_rme32_capture_copy,
1258 .mmap = snd_pcm_lib_mmap_iomem,
1259 };
1260
1261 static snd_pcm_ops_t snd_rme32_playback_adat_ops = {
1262 .open = snd_rme32_playback_adat_open,
1263 .close = snd_rme32_playback_close,
1264 .ioctl = snd_pcm_lib_ioctl,
1265 .hw_params = snd_rme32_playback_hw_params,
1266 .prepare = snd_rme32_playback_prepare,
1267 .trigger = snd_rme32_pcm_trigger,
1268 .pointer = snd_rme32_playback_pointer,
1269 .copy = snd_rme32_playback_copy,
1270 .silence = snd_rme32_playback_silence,
1271 .mmap = snd_pcm_lib_mmap_iomem,
1272 };
1273
1274 static snd_pcm_ops_t snd_rme32_capture_adat_ops = {
1275 .open = snd_rme32_capture_adat_open,
1276 .close = snd_rme32_capture_close,
1277 .ioctl = snd_pcm_lib_ioctl,
1278 .hw_params = snd_rme32_capture_hw_params,
1279 .prepare = snd_rme32_capture_prepare,
1280 .trigger = snd_rme32_pcm_trigger,
1281 .pointer = snd_rme32_capture_pointer,
1282 .copy = snd_rme32_capture_copy,
1283 .mmap = snd_pcm_lib_mmap_iomem,
1284 };
1285
1286 /* for fullduplex mode */
1287 static snd_pcm_ops_t snd_rme32_playback_spdif_fd_ops = {
1288 .open = snd_rme32_playback_spdif_open,
1289 .close = snd_rme32_playback_close,
1290 .ioctl = snd_pcm_lib_ioctl,
1291 .hw_params = snd_rme32_playback_hw_params,
1292 .hw_free = snd_rme32_pcm_hw_free,
1293 .prepare = snd_rme32_playback_prepare,
1294 .trigger = snd_rme32_pcm_trigger,
1295 .pointer = snd_rme32_playback_fd_pointer,
1296 .ack = snd_rme32_playback_fd_ack,
1297 };
1298
1299 static snd_pcm_ops_t snd_rme32_capture_spdif_fd_ops = {
1300 .open = snd_rme32_capture_spdif_open,
1301 .close = snd_rme32_capture_close,
1302 .ioctl = snd_pcm_lib_ioctl,
1303 .hw_params = snd_rme32_capture_hw_params,
1304 .hw_free = snd_rme32_pcm_hw_free,
1305 .prepare = snd_rme32_capture_prepare,
1306 .trigger = snd_rme32_pcm_trigger,
1307 .pointer = snd_rme32_capture_fd_pointer,
1308 .ack = snd_rme32_capture_fd_ack,
1309 };
1310
1311 static snd_pcm_ops_t snd_rme32_playback_adat_fd_ops = {
1312 .open = snd_rme32_playback_adat_open,
1313 .close = snd_rme32_playback_close,
1314 .ioctl = snd_pcm_lib_ioctl,
1315 .hw_params = snd_rme32_playback_hw_params,
1316 .prepare = snd_rme32_playback_prepare,
1317 .trigger = snd_rme32_pcm_trigger,
1318 .pointer = snd_rme32_playback_fd_pointer,
1319 .ack = snd_rme32_playback_fd_ack,
1320 };
1321
1322 static snd_pcm_ops_t snd_rme32_capture_adat_fd_ops = {
1323 .open = snd_rme32_capture_adat_open,
1324 .close = snd_rme32_capture_close,
1325 .ioctl = snd_pcm_lib_ioctl,
1326 .hw_params = snd_rme32_capture_hw_params,
1327 .prepare = snd_rme32_capture_prepare,
1328 .trigger = snd_rme32_pcm_trigger,
1329 .pointer = snd_rme32_capture_fd_pointer,
1330 .ack = snd_rme32_capture_fd_ack,
1331 };
1332
1333 static void snd_rme32_free(void *private_data)
1334 {
1335 rme32_t *rme32 = (rme32_t *) private_data;
1336
1337 if (rme32 == NULL) {
1338 return;
1339 }
1340 if (rme32->irq >= 0) {
1341 snd_rme32_pcm_stop(rme32, 0);
1342 free_irq(rme32->irq, (void *) rme32);
1343 rme32->irq = -1;
1344 }
1345 if (rme32->iobase) {
1346 iounmap(rme32->iobase);
1347 rme32->iobase = NULL;
1348 }
1349 if (rme32->port) {
1350 pci_release_regions(rme32->pci);
1351 rme32->port = 0;
1352 }
1353 pci_disable_device(rme32->pci);
1354 }
1355
1356 static void snd_rme32_free_spdif_pcm(snd_pcm_t * pcm)
1357 {
1358 rme32_t *rme32 = (rme32_t *) pcm->private_data;
1359 rme32->spdif_pcm = NULL;
1360 }
1361
1362 static void
1363 snd_rme32_free_adat_pcm(snd_pcm_t *pcm)
1364 {
1365 rme32_t *rme32 = (rme32_t *) pcm->private_data;
1366 rme32->adat_pcm = NULL;
1367 }
1368
1369 static int __devinit snd_rme32_create(rme32_t * rme32)
1370 {
1371 struct pci_dev *pci = rme32->pci;
1372 int err;
1373
1374 rme32->irq = -1;
1375 spin_lock_init(&rme32->lock);
1376
1377 if ((err = pci_enable_device(pci)) < 0)
1378 return err;
1379
1380 if ((err = pci_request_regions(pci, "RME32")) < 0)
1381 return err;
1382 rme32->port = pci_resource_start(rme32->pci, 0);
1383
1384 if (request_irq(pci->irq, snd_rme32_interrupt, SA_INTERRUPT | SA_SHIRQ, "RME32", (void *) rme32)) {
1385 snd_printk("unable to grab IRQ %d\n", pci->irq);
1386 return -EBUSY;
1387 }
1388 rme32->irq = pci->irq;
1389
1390 if ((rme32->iobase = ioremap_nocache(rme32->port, RME32_IO_SIZE)) == 0) {
1391 snd_printk("unable to remap memory region 0x%lx-0x%lx\n",
1392 rme32->port, rme32->port + RME32_IO_SIZE - 1);
1393 return -ENOMEM;
1394 }
1395
1396 /* read the card's revision number */
1397 pci_read_config_byte(pci, 8, &rme32->rev);
1398
1399 /* set up ALSA pcm device for S/PDIF */
1400 if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
1401 return err;
1402 }
1403 rme32->spdif_pcm->private_data = rme32;
1404 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1405 strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1406 if (rme32->fullduplex_mode) {
1407 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1408 &snd_rme32_playback_spdif_fd_ops);
1409 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1410 &snd_rme32_capture_spdif_fd_ops);
1411 snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1412 snd_dma_continuous_data(GFP_KERNEL),
1413 0, RME32_MID_BUFFER_SIZE);
1414 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1415 } else {
1416 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1417 &snd_rme32_playback_spdif_ops);
1418 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1419 &snd_rme32_capture_spdif_ops);
1420 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1421 }
1422
1423 /* set up ALSA pcm device for ADAT */
1424 if ((pci->device == PCI_DEVICE_ID_DIGI32) ||
1425 (pci->device == PCI_DEVICE_ID_DIGI32_PRO)) {
1426 /* ADAT is not available on DIGI32 and DIGI32 Pro */
1427 rme32->adat_pcm = NULL;
1428 }
1429 else {
1430 if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1431 1, 1, &rme32->adat_pcm)) < 0)
1432 {
1433 return err;
1434 }
1435 rme32->adat_pcm->private_data = rme32;
1436 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1437 strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1438 if (rme32->fullduplex_mode) {
1439 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1440 &snd_rme32_playback_adat_fd_ops);
1441 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1442 &snd_rme32_capture_adat_fd_ops);
1443 snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1444 snd_dma_continuous_data(GFP_KERNEL),
1445 0, RME32_MID_BUFFER_SIZE);
1446 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1447 } else {
1448 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1449 &snd_rme32_playback_adat_ops);
1450 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1451 &snd_rme32_capture_adat_ops);
1452 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1453 }
1454 }
1455
1456
1457 rme32->playback_periodsize = 0;
1458 rme32->capture_periodsize = 0;
1459
1460 /* make sure playback/capture is stopped, if by some reason active */
1461 snd_rme32_pcm_stop(rme32, 0);
1462
1463 /* reset DAC */
1464 snd_rme32_reset_dac(rme32);
1465
1466 /* reset buffer pointer */
1467 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1468
1469 /* set default values in registers */
1470 rme32->wcreg = RME32_WCR_SEL | /* normal playback */
1471 RME32_WCR_INP_0 | /* input select */
1472 RME32_WCR_MUTE; /* muting on */
1473 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1474
1475
1476 /* init switch interface */
1477 if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
1478 return err;
1479 }
1480
1481 /* init proc interface */
1482 snd_rme32_proc_init(rme32);
1483
1484 rme32->capture_substream = NULL;
1485 rme32->playback_substream = NULL;
1486
1487 return 0;
1488 }
1489
1490 /*
1491 * proc interface
1492 */
1493
1494 static void
1495 snd_rme32_proc_read(snd_info_entry_t * entry, snd_info_buffer_t * buffer)
1496 {
1497 int n;
1498 rme32_t *rme32 = (rme32_t *) entry->private_data;
1499
1500 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1501
1502 snd_iprintf(buffer, rme32->card->longname);
1503 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1504
1505 snd_iprintf(buffer, "\nGeneral settings\n");
1506 if (rme32->fullduplex_mode)
1507 snd_iprintf(buffer, " Full-duplex mode\n");
1508 else
1509 snd_iprintf(buffer, " Half-duplex mode\n");
1510 if (RME32_PRO_WITH_8414(rme32)) {
1511 snd_iprintf(buffer, " receiver: CS8414\n");
1512 } else {
1513 snd_iprintf(buffer, " receiver: CS8412\n");
1514 }
1515 if (rme32->wcreg & RME32_WCR_MODE24) {
1516 snd_iprintf(buffer, " format: 24 bit");
1517 } else {
1518 snd_iprintf(buffer, " format: 16 bit");
1519 }
1520 if (rme32->wcreg & RME32_WCR_MONO) {
1521 snd_iprintf(buffer, ", Mono\n");
1522 } else {
1523 snd_iprintf(buffer, ", Stereo\n");
1524 }
1525
1526 snd_iprintf(buffer, "\nInput settings\n");
1527 switch (snd_rme32_getinputtype(rme32)) {
1528 case RME32_INPUT_OPTICAL:
1529 snd_iprintf(buffer, " input: optical");
1530 break;
1531 case RME32_INPUT_COAXIAL:
1532 snd_iprintf(buffer, " input: coaxial");
1533 break;
1534 case RME32_INPUT_INTERNAL:
1535 snd_iprintf(buffer, " input: internal");
1536 break;
1537 case RME32_INPUT_XLR:
1538 snd_iprintf(buffer, " input: XLR");
1539 break;
1540 }
1541 if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1542 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1543 } else {
1544 if (n) {
1545 snd_iprintf(buffer, " (8 channels)\n");
1546 } else {
1547 snd_iprintf(buffer, " (2 channels)\n");
1548 }
1549 snd_iprintf(buffer, " sample rate: %d Hz\n",
1550 snd_rme32_capture_getrate(rme32, &n));
1551 }
1552
1553 snd_iprintf(buffer, "\nOutput settings\n");
1554 if (rme32->wcreg & RME32_WCR_SEL) {
1555 snd_iprintf(buffer, " output signal: normal playback");
1556 } else {
1557 snd_iprintf(buffer, " output signal: same as input");
1558 }
1559 if (rme32->wcreg & RME32_WCR_MUTE) {
1560 snd_iprintf(buffer, " (muted)\n");
1561 } else {
1562 snd_iprintf(buffer, "\n");
1563 }
1564
1565 /* master output frequency */
1566 if (!
1567 ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1568 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1569 snd_iprintf(buffer, " sample rate: %d Hz\n",
1570 snd_rme32_playback_getrate(rme32));
1571 }
1572 if (rme32->rcreg & RME32_RCR_KMODE) {
1573 snd_iprintf(buffer, " sample clock source: AutoSync\n");
1574 } else {
1575 snd_iprintf(buffer, " sample clock source: Internal\n");
1576 }
1577 if (rme32->wcreg & RME32_WCR_PRO) {
1578 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1579 } else {
1580 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1581 }
1582 if (rme32->wcreg & RME32_WCR_EMP) {
1583 snd_iprintf(buffer, " emphasis: on\n");
1584 } else {
1585 snd_iprintf(buffer, " emphasis: off\n");
1586 }
1587 }
1588
1589 static void __devinit snd_rme32_proc_init(rme32_t * rme32)
1590 {
1591 snd_info_entry_t *entry;
1592
1593 if (! snd_card_proc_new(rme32->card, "rme32", &entry))
1594 snd_info_set_text_ops(entry, rme32, 1024, snd_rme32_proc_read);
1595 }
1596
1597 /*
1598 * control interface
1599 */
1600
1601 static int
1602 snd_rme32_info_loopback_control(snd_kcontrol_t * kcontrol,
1603 snd_ctl_elem_info_t * uinfo)
1604 {
1605 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1606 uinfo->count = 1;
1607 uinfo->value.integer.min = 0;
1608 uinfo->value.integer.max = 1;
1609 return 0;
1610 }
1611 static int
1612 snd_rme32_get_loopback_control(snd_kcontrol_t * kcontrol,
1613 snd_ctl_elem_value_t * ucontrol)
1614 {
1615 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1616
1617 spin_lock_irq(&rme32->lock);
1618 ucontrol->value.integer.value[0] =
1619 rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1620 spin_unlock_irq(&rme32->lock);
1621 return 0;
1622 }
1623 static int
1624 snd_rme32_put_loopback_control(snd_kcontrol_t * kcontrol,
1625 snd_ctl_elem_value_t * ucontrol)
1626 {
1627 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1628 unsigned int val;
1629 int change;
1630
1631 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1632 spin_lock_irq(&rme32->lock);
1633 val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1634 change = val != rme32->wcreg;
1635 if (ucontrol->value.integer.value[0])
1636 val &= ~RME32_WCR_MUTE;
1637 else
1638 val |= RME32_WCR_MUTE;
1639 rme32->wcreg = val;
1640 writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1641 spin_unlock_irq(&rme32->lock);
1642 return change;
1643 }
1644
1645 static int
1646 snd_rme32_info_inputtype_control(snd_kcontrol_t * kcontrol,
1647 snd_ctl_elem_info_t * uinfo)
1648 {
1649 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1650 static char *texts[4] = { "Optical", "Coaxial", "Internal", "XLR" };
1651
1652 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1653 uinfo->count = 1;
1654 switch (rme32->pci->device) {
1655 case PCI_DEVICE_ID_DIGI32:
1656 case PCI_DEVICE_ID_DIGI32_8:
1657 uinfo->value.enumerated.items = 3;
1658 break;
1659 case PCI_DEVICE_ID_DIGI32_PRO:
1660 uinfo->value.enumerated.items = 4;
1661 break;
1662 default:
1663 snd_BUG();
1664 break;
1665 }
1666 if (uinfo->value.enumerated.item >
1667 uinfo->value.enumerated.items - 1) {
1668 uinfo->value.enumerated.item =
1669 uinfo->value.enumerated.items - 1;
1670 }
1671 strcpy(uinfo->value.enumerated.name,
1672 texts[uinfo->value.enumerated.item]);
1673 return 0;
1674 }
1675 static int
1676 snd_rme32_get_inputtype_control(snd_kcontrol_t * kcontrol,
1677 snd_ctl_elem_value_t * ucontrol)
1678 {
1679 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1680 unsigned int items = 3;
1681
1682 spin_lock_irq(&rme32->lock);
1683 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1684
1685 switch (rme32->pci->device) {
1686 case PCI_DEVICE_ID_DIGI32:
1687 case PCI_DEVICE_ID_DIGI32_8:
1688 items = 3;
1689 break;
1690 case PCI_DEVICE_ID_DIGI32_PRO:
1691 items = 4;
1692 break;
1693 default:
1694 snd_BUG();
1695 break;
1696 }
1697 if (ucontrol->value.enumerated.item[0] >= items) {
1698 ucontrol->value.enumerated.item[0] = items - 1;
1699 }
1700
1701 spin_unlock_irq(&rme32->lock);
1702 return 0;
1703 }
1704 static int
1705 snd_rme32_put_inputtype_control(snd_kcontrol_t * kcontrol,
1706 snd_ctl_elem_value_t * ucontrol)
1707 {
1708 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1709 unsigned int val;
1710 int change, items = 3;
1711
1712 switch (rme32->pci->device) {
1713 case PCI_DEVICE_ID_DIGI32:
1714 case PCI_DEVICE_ID_DIGI32_8:
1715 items = 3;
1716 break;
1717 case PCI_DEVICE_ID_DIGI32_PRO:
1718 items = 4;
1719 break;
1720 default:
1721 snd_BUG();
1722 break;
1723 }
1724 val = ucontrol->value.enumerated.item[0] % items;
1725
1726 spin_lock_irq(&rme32->lock);
1727 change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1728 snd_rme32_setinputtype(rme32, val);
1729 spin_unlock_irq(&rme32->lock);
1730 return change;
1731 }
1732
1733 static int
1734 snd_rme32_info_clockmode_control(snd_kcontrol_t * kcontrol,
1735 snd_ctl_elem_info_t * uinfo)
1736 {
1737 static char *texts[4] = { "AutoSync",
1738 "Internal 32.0kHz",
1739 "Internal 44.1kHz",
1740 "Internal 48.0kHz" };
1741
1742 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1743 uinfo->count = 1;
1744 uinfo->value.enumerated.items = 4;
1745 if (uinfo->value.enumerated.item > 3) {
1746 uinfo->value.enumerated.item = 3;
1747 }
1748 strcpy(uinfo->value.enumerated.name,
1749 texts[uinfo->value.enumerated.item]);
1750 return 0;
1751 }
1752 static int
1753 snd_rme32_get_clockmode_control(snd_kcontrol_t * kcontrol,
1754 snd_ctl_elem_value_t * ucontrol)
1755 {
1756 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1757
1758 spin_lock_irq(&rme32->lock);
1759 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1760 spin_unlock_irq(&rme32->lock);
1761 return 0;
1762 }
1763 static int
1764 snd_rme32_put_clockmode_control(snd_kcontrol_t * kcontrol,
1765 snd_ctl_elem_value_t * ucontrol)
1766 {
1767 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1768 unsigned int val;
1769 int change;
1770
1771 val = ucontrol->value.enumerated.item[0] % 3;
1772 spin_lock_irq(&rme32->lock);
1773 change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1774 snd_rme32_setclockmode(rme32, val);
1775 spin_unlock_irq(&rme32->lock);
1776 return change;
1777 }
1778
1779 static u32 snd_rme32_convert_from_aes(snd_aes_iec958_t * aes)
1780 {
1781 u32 val = 0;
1782 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1783 if (val & RME32_WCR_PRO)
1784 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1785 else
1786 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1787 return val;
1788 }
1789
1790 static void snd_rme32_convert_to_aes(snd_aes_iec958_t * aes, u32 val)
1791 {
1792 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1793 if (val & RME32_WCR_PRO)
1794 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1795 else
1796 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1797 }
1798
1799 static int snd_rme32_control_spdif_info(snd_kcontrol_t * kcontrol,
1800 snd_ctl_elem_info_t * uinfo)
1801 {
1802 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1803 uinfo->count = 1;
1804 return 0;
1805 }
1806
1807 static int snd_rme32_control_spdif_get(snd_kcontrol_t * kcontrol,
1808 snd_ctl_elem_value_t * ucontrol)
1809 {
1810 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1811
1812 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1813 rme32->wcreg_spdif);
1814 return 0;
1815 }
1816
1817 static int snd_rme32_control_spdif_put(snd_kcontrol_t * kcontrol,
1818 snd_ctl_elem_value_t * ucontrol)
1819 {
1820 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1821 int change;
1822 u32 val;
1823
1824 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1825 spin_lock_irq(&rme32->lock);
1826 change = val != rme32->wcreg_spdif;
1827 rme32->wcreg_spdif = val;
1828 spin_unlock_irq(&rme32->lock);
1829 return change;
1830 }
1831
1832 static int snd_rme32_control_spdif_stream_info(snd_kcontrol_t * kcontrol,
1833 snd_ctl_elem_info_t * uinfo)
1834 {
1835 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1836 uinfo->count = 1;
1837 return 0;
1838 }
1839
1840 static int snd_rme32_control_spdif_stream_get(snd_kcontrol_t * kcontrol,
1841 snd_ctl_elem_value_t *
1842 ucontrol)
1843 {
1844 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1845
1846 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1847 rme32->wcreg_spdif_stream);
1848 return 0;
1849 }
1850
1851 static int snd_rme32_control_spdif_stream_put(snd_kcontrol_t * kcontrol,
1852 snd_ctl_elem_value_t *
1853 ucontrol)
1854 {
1855 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1856 int change;
1857 u32 val;
1858
1859 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1860 spin_lock_irq(&rme32->lock);
1861 change = val != rme32->wcreg_spdif_stream;
1862 rme32->wcreg_spdif_stream = val;
1863 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1864 rme32->wcreg |= val;
1865 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1866 spin_unlock_irq(&rme32->lock);
1867 return change;
1868 }
1869
1870 static int snd_rme32_control_spdif_mask_info(snd_kcontrol_t * kcontrol,
1871 snd_ctl_elem_info_t * uinfo)
1872 {
1873 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1874 uinfo->count = 1;
1875 return 0;
1876 }
1877
1878 static int snd_rme32_control_spdif_mask_get(snd_kcontrol_t * kcontrol,
1879 snd_ctl_elem_value_t *
1880 ucontrol)
1881 {
1882 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1883 return 0;
1884 }
1885
1886 static snd_kcontrol_new_t snd_rme32_controls[] = {
1887 {
1888 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1889 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1890 .info = snd_rme32_control_spdif_info,
1891 .get = snd_rme32_control_spdif_get,
1892 .put = snd_rme32_control_spdif_put
1893 },
1894 {
1895 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1896 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1897 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1898 .info = snd_rme32_control_spdif_stream_info,
1899 .get = snd_rme32_control_spdif_stream_get,
1900 .put = snd_rme32_control_spdif_stream_put
1901 },
1902 {
1903 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1904 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1905 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1906 .info = snd_rme32_control_spdif_mask_info,
1907 .get = snd_rme32_control_spdif_mask_get,
1908 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1909 },
1910 {
1911 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1912 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1913 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1914 .info = snd_rme32_control_spdif_mask_info,
1915 .get = snd_rme32_control_spdif_mask_get,
1916 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1917 },
1918 {
1919 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1920 .name = "Input Connector",
1921 .info = snd_rme32_info_inputtype_control,
1922 .get = snd_rme32_get_inputtype_control,
1923 .put = snd_rme32_put_inputtype_control
1924 },
1925 {
1926 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1927 .name = "Loopback Input",
1928 .info = snd_rme32_info_loopback_control,
1929 .get = snd_rme32_get_loopback_control,
1930 .put = snd_rme32_put_loopback_control
1931 },
1932 {
1933 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1934 .name = "Sample Clock Source",
1935 .info = snd_rme32_info_clockmode_control,
1936 .get = snd_rme32_get_clockmode_control,
1937 .put = snd_rme32_put_clockmode_control
1938 }
1939 };
1940
1941 static int snd_rme32_create_switches(snd_card_t * card, rme32_t * rme32)
1942 {
1943 int idx, err;
1944 snd_kcontrol_t *kctl;
1945
1946 for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1947 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
1948 return err;
1949 if (idx == 1) /* IEC958 (S/PDIF) Stream */
1950 rme32->spdif_ctl = kctl;
1951 }
1952
1953 return 0;
1954 }
1955
1956 /*
1957 * Card initialisation
1958 */
1959
1960 static void snd_rme32_card_free(snd_card_t * card)
1961 {
1962 snd_rme32_free(card->private_data);
1963 }
1964
1965 static int __devinit
1966 snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1967 {
1968 static int dev;
1969 rme32_t *rme32;
1970 snd_card_t *card;
1971 int err;
1972
1973 if (dev >= SNDRV_CARDS) {
1974 return -ENODEV;
1975 }
1976 if (!enable[dev]) {
1977 dev++;
1978 return -ENOENT;
1979 }
1980
1981 if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
1982 sizeof(rme32_t))) == NULL)
1983 return -ENOMEM;
1984 card->private_free = snd_rme32_card_free;
1985 rme32 = (rme32_t *) card->private_data;
1986 rme32->card = card;
1987 rme32->pci = pci;
1988 snd_card_set_dev(card, &pci->dev);
1989 if (fullduplex[dev])
1990 rme32->fullduplex_mode = 1;
1991 if ((err = snd_rme32_create(rme32)) < 0) {
1992 snd_card_free(card);
1993 return err;
1994 }
1995
1996 strcpy(card->driver, "Digi32");
1997 switch (rme32->pci->device) {
1998 case PCI_DEVICE_ID_DIGI32:
1999 strcpy(card->shortname, "RME Digi32");
2000 break;
2001 case PCI_DEVICE_ID_DIGI32_8:
2002 strcpy(card->shortname, "RME Digi32/8");
2003 break;
2004 case PCI_DEVICE_ID_DIGI32_PRO:
2005 strcpy(card->shortname, "RME Digi32 PRO");
2006 break;
2007 }
2008 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
2009 card->shortname, rme32->rev, rme32->port, rme32->irq);
2010
2011 if ((err = snd_card_register(card)) < 0) {
2012 snd_card_free(card);
2013 return err;
2014 }
2015 pci_set_drvdata(pci, card);
2016 dev++;
2017 return 0;
2018 }
2019
2020 static void __devexit snd_rme32_remove(struct pci_dev *pci)
2021 {
2022 snd_card_free(pci_get_drvdata(pci));
2023 pci_set_drvdata(pci, NULL);
2024 }
2025
2026 static struct pci_driver driver = {
2027 .name = "RME Digi32",
2028 .id_table = snd_rme32_ids,
2029 .probe = snd_rme32_probe,
2030 .remove = __devexit_p(snd_rme32_remove),
2031 };
2032
2033 static int __init alsa_card_rme32_init(void)
2034 {
2035 return pci_module_init(&driver);
2036 }
2037
2038 static void __exit alsa_card_rme32_exit(void)
2039 {
2040 pci_unregister_driver(&driver);
2041 }
2042
2043 module_init(alsa_card_rme32_init)
2044 module_exit(alsa_card_rme32_exit)
2045
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