1 /*
2 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
3 * Abramo Bagnara <abramo@alsa-project.org>
4 * Cirrus Logic, Inc.
5 * Routines for control of Cirrus Logic CS461x chips
6 *
7 * KNOWN BUGS:
8 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
9 * and the SPDIF get somewhat "distorcionated", or/and left right channel
10 * are swapped. To get around this problem when it happens, mute and unmute
11 * the SPDIF input mixer controll.
12 * - On the Hercules Game Theater XP the amplifier are sometimes turned
13 * off on inadecuate moments which causes distorcions on sound.
14 *
15 * TODO:
16 * - Secondary CODEC on some soundcards
17 * - SPDIF input support for other sample rates then 48khz
18 * - Posibility to mix the SPDIF output with analog sources.
19 * - PCM channels for Center and LFE on secondary codec
20 *
21 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
22 * is default configuration), no SPDIF, no secondary codec, no
23 * multi channel PCM. But known to work.
24 *
25 * FINALLY: A credit to the developers Tom and Jordan
26 * at Cirrus for have helping me out with the DSP, however we
27 * still don't have sufficient documentation and technical
28 * references to be able to implement all fancy feutures
29 * supported by the cs46xx DSP's.
30 * Benny <benny@hostmobility.com>
31 *
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License as published by
34 * the Free Software Foundation; either version 2 of the License, or
35 * (at your option) any later version.
36 *
37 * This program is distributed in the hope that it will be useful,
38 * but WITHOUT ANY WARRANTY; without even the implied warranty of
39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40 * GNU General Public License for more details.
41 *
42 * You should have received a copy of the GNU General Public License
43 * along with this program; if not, write to the Free Software
44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 *
46 */
47
48 #include <sound/driver.h>
49 #include <linux/delay.h>
50 #include <linux/pci.h>
51 #include <linux/pm.h>
52 #include <linux/init.h>
53 #include <linux/interrupt.h>
54 #include <linux/slab.h>
55 #include <linux/gameport.h>
56
57 #include <sound/core.h>
58 #include <sound/control.h>
59 #include <sound/info.h>
60 #include <sound/pcm.h>
61 #include <sound/pcm_params.h>
62 #include <sound/cs46xx.h>
63
64 #include <asm/io.h>
65
66 #include "cs46xx_lib.h"
67 #include "dsp_spos.h"
68
69 static void amp_voyetra(cs46xx_t *chip, int change);
70
71 #ifdef CONFIG_SND_CS46XX_NEW_DSP
72 static snd_pcm_ops_t snd_cs46xx_playback_rear_ops;
73 static snd_pcm_ops_t snd_cs46xx_playback_indirect_rear_ops;
74 static snd_pcm_ops_t snd_cs46xx_playback_clfe_ops;
75 static snd_pcm_ops_t snd_cs46xx_playback_indirect_clfe_ops;
76 static snd_pcm_ops_t snd_cs46xx_playback_iec958_ops;
77 static snd_pcm_ops_t snd_cs46xx_playback_indirect_iec958_ops;
78 #endif
79
80 static snd_pcm_ops_t snd_cs46xx_playback_ops;
81 static snd_pcm_ops_t snd_cs46xx_playback_indirect_ops;
82 static snd_pcm_ops_t snd_cs46xx_capture_ops;
83 static snd_pcm_ops_t snd_cs46xx_capture_indirect_ops;
84
85 static unsigned short snd_cs46xx_codec_read(cs46xx_t *chip,
86 unsigned short reg,
87 int codec_index)
88 {
89 int count;
90 unsigned short result,tmp;
91 u32 offset = 0;
92 snd_assert ( (codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
93 (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
94 return -EINVAL);
95
96 chip->active_ctrl(chip, 1);
97
98 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
99 offset = CS46XX_SECONDARY_CODEC_OFFSET;
100
101 /*
102 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
103 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
104 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
105 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
106 * 5. if DCV not cleared, break and return error
107 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
108 */
109
110 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
111
112 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
113 if ((tmp & ACCTL_VFRM) == 0) {
114 snd_printk(KERN_WARNING "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp);
115 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
116 msleep(50);
117 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
118 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
119
120 }
121
122 /*
123 * Setup the AC97 control registers on the CS461x to send the
124 * appropriate command to the AC97 to perform the read.
125 * ACCAD = Command Address Register = 46Ch
126 * ACCDA = Command Data Register = 470h
127 * ACCTL = Control Register = 460h
128 * set DCV - will clear when process completed
129 * set CRW - Read command
130 * set VFRM - valid frame enabled
131 * set ESYN - ASYNC generation enabled
132 * set RSTN - ARST# inactive, AC97 codec not reset
133 */
134
135 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
136 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
137 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
138 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
139 ACCTL_VFRM | ACCTL_ESYN |
140 ACCTL_RSTN);
141 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
142 ACCTL_VFRM | ACCTL_ESYN |
143 ACCTL_RSTN);
144 } else {
145 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
146 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
147 ACCTL_RSTN);
148 }
149
150 /*
151 * Wait for the read to occur.
152 */
153 for (count = 0; count < 1000; count++) {
154 /*
155 * First, we want to wait for a short time.
156 */
157 udelay(10);
158 /*
159 * Now, check to see if the read has completed.
160 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
161 */
162 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
163 goto ok1;
164 }
165
166 snd_printk("AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
167 result = 0xffff;
168 goto end;
169
170 ok1:
171 /*
172 * Wait for the valid status bit to go active.
173 */
174 for (count = 0; count < 100; count++) {
175 /*
176 * Read the AC97 status register.
177 * ACSTS = Status Register = 464h
178 * VSTS - Valid Status
179 */
180 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
181 goto ok2;
182 udelay(10);
183 }
184
185 snd_printk("AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg);
186 result = 0xffff;
187 goto end;
188
189 ok2:
190 /*
191 * Read the data returned from the AC97 register.
192 * ACSDA = Status Data Register = 474h
193 */
194 #if 0
195 printk("e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
196 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
197 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
198 #endif
199
200 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
201 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
202 end:
203 chip->active_ctrl(chip, -1);
204 return result;
205 }
206
207 static unsigned short snd_cs46xx_ac97_read(ac97_t * ac97,
208 unsigned short reg)
209 {
210 cs46xx_t *chip = ac97->private_data;
211 unsigned short val;
212 int codec_index = ac97->num;
213
214 snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
215 codec_index == CS46XX_SECONDARY_CODEC_INDEX,
216 return 0xffff);
217
218 val = snd_cs46xx_codec_read(chip, reg, codec_index);
219
220 return val;
221 }
222
223
224 static void snd_cs46xx_codec_write(cs46xx_t *chip,
225 unsigned short reg,
226 unsigned short val,
227 int codec_index)
228 {
229 int count;
230
231 snd_assert ((codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
232 (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
233 return);
234
235 chip->active_ctrl(chip, 1);
236
237 /*
238 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
239 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
240 * 3. Write ACCTL = Control Register = 460h for initiating the write
241 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
242 * 5. if DCV not cleared, break and return error
243 */
244
245 /*
246 * Setup the AC97 control registers on the CS461x to send the
247 * appropriate command to the AC97 to perform the read.
248 * ACCAD = Command Address Register = 46Ch
249 * ACCDA = Command Data Register = 470h
250 * ACCTL = Control Register = 460h
251 * set DCV - will clear when process completed
252 * reset CRW - Write command
253 * set VFRM - valid frame enabled
254 * set ESYN - ASYNC generation enabled
255 * set RSTN - ARST# inactive, AC97 codec not reset
256 */
257 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
258 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
259 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
260
261 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
262 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
263 ACCTL_ESYN | ACCTL_RSTN);
264 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
265 ACCTL_ESYN | ACCTL_RSTN);
266 } else {
267 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
268 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
269 }
270
271 for (count = 0; count < 4000; count++) {
272 /*
273 * First, we want to wait for a short time.
274 */
275 udelay(10);
276 /*
277 * Now, check to see if the write has completed.
278 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
279 */
280 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
281 goto end;
282 }
283 }
284 snd_printk("AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val);
285 end:
286 chip->active_ctrl(chip, -1);
287 }
288
289 static void snd_cs46xx_ac97_write(ac97_t *ac97,
290 unsigned short reg,
291 unsigned short val)
292 {
293 cs46xx_t *chip = ac97->private_data;
294 int codec_index = ac97->num;
295
296 snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
297 codec_index == CS46XX_SECONDARY_CODEC_INDEX,
298 return);
299
300 snd_cs46xx_codec_write(chip, reg, val, codec_index);
301 }
302
303
304 /*
305 * Chip initialization
306 */
307
308 int snd_cs46xx_download(cs46xx_t *chip,
309 u32 *src,
310 unsigned long offset,
311 unsigned long len)
312 {
313 void __iomem *dst;
314 unsigned int bank = offset >> 16;
315 offset = offset & 0xffff;
316
317 snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
318 dst = chip->region.idx[bank+1].remap_addr + offset;
319 len /= sizeof(u32);
320
321 /* writel already converts 32-bit value to right endianess */
322 while (len-- > 0) {
323 writel(*src++, dst);
324 dst += sizeof(u32);
325 }
326 return 0;
327 }
328
329 #ifdef CONFIG_SND_CS46XX_NEW_DSP
330
331 #include "imgs/cwc4630.h"
332 #include "imgs/cwcasync.h"
333 #include "imgs/cwcsnoop.h"
334 #include "imgs/cwcbinhack.h"
335 #include "imgs/cwcdma.h"
336
337 int snd_cs46xx_clear_BA1(cs46xx_t *chip,
338 unsigned long offset,
339 unsigned long len)
340 {
341 void __iomem *dst;
342 unsigned int bank = offset >> 16;
343 offset = offset & 0xffff;
344
345 snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
346 dst = chip->region.idx[bank+1].remap_addr + offset;
347 len /= sizeof(u32);
348
349 /* writel already converts 32-bit value to right endianess */
350 while (len-- > 0) {
351 writel(0, dst);
352 dst += sizeof(u32);
353 }
354 return 0;
355 }
356
357 #else /* old DSP image */
358
359 #include "cs46xx_image.h"
360
361 int snd_cs46xx_download_image(cs46xx_t *chip)
362 {
363 int idx, err;
364 unsigned long offset = 0;
365
366 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
367 if ((err = snd_cs46xx_download(chip,
368 &BA1Struct.map[offset],
369 BA1Struct.memory[idx].offset,
370 BA1Struct.memory[idx].size)) < 0)
371 return err;
372 offset += BA1Struct.memory[idx].size >> 2;
373 }
374 return 0;
375 }
376 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
377
378 /*
379 * Chip reset
380 */
381
382 static void snd_cs46xx_reset(cs46xx_t *chip)
383 {
384 int idx;
385
386 /*
387 * Write the reset bit of the SP control register.
388 */
389 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
390
391 /*
392 * Write the control register.
393 */
394 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
395
396 /*
397 * Clear the trap registers.
398 */
399 for (idx = 0; idx < 8; idx++) {
400 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
401 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
402 }
403 snd_cs46xx_poke(chip, BA1_DREG, 0);
404
405 /*
406 * Set the frame timer to reflect the number of cycles per frame.
407 */
408 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
409 }
410
411 static int cs46xx_wait_for_fifo(cs46xx_t * chip,int retry_timeout)
412 {
413 u32 i, status = 0;
414 /*
415 * Make sure the previous FIFO write operation has completed.
416 */
417 for(i = 0; i < 50; i++){
418 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
419
420 if( !(status & SERBST_WBSY) )
421 break;
422
423 mdelay(retry_timeout);
424 }
425
426 if(status & SERBST_WBSY) {
427 snd_printk( KERN_ERR "cs46xx: failure waiting for FIFO command to complete\n");
428
429 return -EINVAL;
430 }
431
432 return 0;
433 }
434
435 static void snd_cs46xx_clear_serial_FIFOs(cs46xx_t *chip)
436 {
437 int idx, powerdown = 0;
438 unsigned int tmp;
439
440 /*
441 * See if the devices are powered down. If so, we must power them up first
442 * or they will not respond.
443 */
444 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
445 if (!(tmp & CLKCR1_SWCE)) {
446 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
447 powerdown = 1;
448 }
449
450 /*
451 * We want to clear out the serial port FIFOs so we don't end up playing
452 * whatever random garbage happens to be in them. We fill the sample FIFOS
453 * with zero (silence).
454 */
455 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
456
457 /*
458 * Fill all 256 sample FIFO locations.
459 */
460 for (idx = 0; idx < 0xFF; idx++) {
461 /*
462 * Make sure the previous FIFO write operation has completed.
463 */
464 if (cs46xx_wait_for_fifo(chip,1)) {
465 snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx);
466
467 if (powerdown)
468 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
469
470 break;
471 }
472 /*
473 * Write the serial port FIFO index.
474 */
475 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
476 /*
477 * Tell the serial port to load the new value into the FIFO location.
478 */
479 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
480 }
481 /*
482 * Now, if we powered up the devices, then power them back down again.
483 * This is kinda ugly, but should never happen.
484 */
485 if (powerdown)
486 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
487 }
488
489 static void snd_cs46xx_proc_start(cs46xx_t *chip)
490 {
491 int cnt;
492
493 /*
494 * Set the frame timer to reflect the number of cycles per frame.
495 */
496 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
497 /*
498 * Turn on the run, run at frame, and DMA enable bits in the local copy of
499 * the SP control register.
500 */
501 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
502 /*
503 * Wait until the run at frame bit resets itself in the SP control
504 * register.
505 */
506 for (cnt = 0; cnt < 25; cnt++) {
507 udelay(50);
508 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
509 break;
510 }
511
512 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
513 snd_printk("SPCR_RUNFR never reset\n");
514 }
515
516 static void snd_cs46xx_proc_stop(cs46xx_t *chip)
517 {
518 /*
519 * Turn off the run, run at frame, and DMA enable bits in the local copy of
520 * the SP control register.
521 */
522 snd_cs46xx_poke(chip, BA1_SPCR, 0);
523 }
524
525 /*
526 * Sample rate routines
527 */
528
529 #define GOF_PER_SEC 200
530
531 static void snd_cs46xx_set_play_sample_rate(cs46xx_t *chip, unsigned int rate)
532 {
533 unsigned long flags;
534 unsigned int tmp1, tmp2;
535 unsigned int phiIncr;
536 unsigned int correctionPerGOF, correctionPerSec;
537
538 /*
539 * Compute the values used to drive the actual sample rate conversion.
540 * The following formulas are being computed, using inline assembly
541 * since we need to use 64 bit arithmetic to compute the values:
542 *
543 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
544 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
545 * GOF_PER_SEC)
546 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
547 * GOF_PER_SEC * correctionPerGOF
548 *
549 * i.e.
550 *
551 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
552 * correctionPerGOF:correctionPerSec =
553 * dividend:remainder(ulOther / GOF_PER_SEC)
554 */
555 tmp1 = rate << 16;
556 phiIncr = tmp1 / 48000;
557 tmp1 -= phiIncr * 48000;
558 tmp1 <<= 10;
559 phiIncr <<= 10;
560 tmp2 = tmp1 / 48000;
561 phiIncr += tmp2;
562 tmp1 -= tmp2 * 48000;
563 correctionPerGOF = tmp1 / GOF_PER_SEC;
564 tmp1 -= correctionPerGOF * GOF_PER_SEC;
565 correctionPerSec = tmp1;
566
567 /*
568 * Fill in the SampleRateConverter control block.
569 */
570 spin_lock_irqsave(&chip->reg_lock, flags);
571 snd_cs46xx_poke(chip, BA1_PSRC,
572 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
573 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
574 spin_unlock_irqrestore(&chip->reg_lock, flags);
575 }
576
577 static void snd_cs46xx_set_capture_sample_rate(cs46xx_t *chip, unsigned int rate)
578 {
579 unsigned long flags;
580 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
581 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
582 unsigned int frameGroupLength, cnt;
583
584 /*
585 * We can only decimate by up to a factor of 1/9th the hardware rate.
586 * Correct the value if an attempt is made to stray outside that limit.
587 */
588 if ((rate * 9) < 48000)
589 rate = 48000 / 9;
590
591 /*
592 * We can not capture at at rate greater than the Input Rate (48000).
593 * Return an error if an attempt is made to stray outside that limit.
594 */
595 if (rate > 48000)
596 rate = 48000;
597
598 /*
599 * Compute the values used to drive the actual sample rate conversion.
600 * The following formulas are being computed, using inline assembly
601 * since we need to use 64 bit arithmetic to compute the values:
602 *
603 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
604 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
605 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
606 * GOF_PER_SEC)
607 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
608 * GOF_PER_SEC * correctionPerGOF
609 * initialDelay = ceil((24 * Fs,in) / Fs,out)
610 *
611 * i.e.
612 *
613 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
614 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
615 * correctionPerGOF:correctionPerSec =
616 * dividend:remainder(ulOther / GOF_PER_SEC)
617 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
618 */
619
620 tmp1 = rate << 16;
621 coeffIncr = tmp1 / 48000;
622 tmp1 -= coeffIncr * 48000;
623 tmp1 <<= 7;
624 coeffIncr <<= 7;
625 coeffIncr += tmp1 / 48000;
626 coeffIncr ^= 0xFFFFFFFF;
627 coeffIncr++;
628 tmp1 = 48000 << 16;
629 phiIncr = tmp1 / rate;
630 tmp1 -= phiIncr * rate;
631 tmp1 <<= 10;
632 phiIncr <<= 10;
633 tmp2 = tmp1 / rate;
634 phiIncr += tmp2;
635 tmp1 -= tmp2 * rate;
636 correctionPerGOF = tmp1 / GOF_PER_SEC;
637 tmp1 -= correctionPerGOF * GOF_PER_SEC;
638 correctionPerSec = tmp1;
639 initialDelay = ((48000 * 24) + rate - 1) / rate;
640
641 /*
642 * Fill in the VariDecimate control block.
643 */
644 spin_lock_irqsave(&chip->reg_lock, flags);
645 snd_cs46xx_poke(chip, BA1_CSRC,
646 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
647 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
648 snd_cs46xx_poke(chip, BA1_CD,
649 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
650 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
651 spin_unlock_irqrestore(&chip->reg_lock, flags);
652
653 /*
654 * Figure out the frame group length for the write back task. Basically,
655 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
656 * the output sample rate.
657 */
658 frameGroupLength = 1;
659 for (cnt = 2; cnt <= 64; cnt *= 2) {
660 if (((rate / cnt) * cnt) != rate)
661 frameGroupLength *= 2;
662 }
663 if (((rate / 3) * 3) != rate) {
664 frameGroupLength *= 3;
665 }
666 for (cnt = 5; cnt <= 125; cnt *= 5) {
667 if (((rate / cnt) * cnt) != rate)
668 frameGroupLength *= 5;
669 }
670
671 /*
672 * Fill in the WriteBack control block.
673 */
674 spin_lock_irqsave(&chip->reg_lock, flags);
675 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
676 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
677 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
678 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
679 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
680 spin_unlock_irqrestore(&chip->reg_lock, flags);
681 }
682
683 /*
684 * PCM part
685 */
686
687 static void snd_cs46xx_pb_trans_copy(snd_pcm_substream_t *substream,
688 snd_pcm_indirect_t *rec, size_t bytes)
689 {
690 snd_pcm_runtime_t *runtime = substream->runtime;
691 cs46xx_pcm_t * cpcm = runtime->private_data;
692 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
693 }
694
695 static int snd_cs46xx_playback_transfer(snd_pcm_substream_t *substream)
696 {
697 snd_pcm_runtime_t *runtime = substream->runtime;
698 cs46xx_pcm_t * cpcm = runtime->private_data;
699 snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy);
700 return 0;
701 }
702
703 static void snd_cs46xx_cp_trans_copy(snd_pcm_substream_t *substream,
704 snd_pcm_indirect_t *rec, size_t bytes)
705 {
706 cs46xx_t *chip = snd_pcm_substream_chip(substream);
707 snd_pcm_runtime_t *runtime = substream->runtime;
708 memcpy(runtime->dma_area + rec->sw_data,
709 chip->capt.hw_buf.area + rec->hw_data, bytes);
710 }
711
712 static int snd_cs46xx_capture_transfer(snd_pcm_substream_t *substream)
713 {
714 cs46xx_t *chip = snd_pcm_substream_chip(substream);
715 snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy);
716 return 0;
717 }
718
719 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(snd_pcm_substream_t * substream)
720 {
721 cs46xx_t *chip = snd_pcm_substream_chip(substream);
722 size_t ptr;
723 cs46xx_pcm_t *cpcm = substream->runtime->private_data;
724 snd_assert (cpcm->pcm_channel,return -ENXIO);
725
726 #ifdef CONFIG_SND_CS46XX_NEW_DSP
727 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
728 #else
729 ptr = snd_cs46xx_peek(chip, BA1_PBA);
730 #endif
731 ptr -= cpcm->hw_buf.addr;
732 return ptr >> cpcm->shift;
733 }
734
735 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(snd_pcm_substream_t * substream)
736 {
737 cs46xx_t *chip = snd_pcm_substream_chip(substream);
738 size_t ptr;
739 cs46xx_pcm_t *cpcm = substream->runtime->private_data;
740
741 #ifdef CONFIG_SND_CS46XX_NEW_DSP
742 snd_assert (cpcm->pcm_channel,return -ENXIO);
743 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
744 #else
745 ptr = snd_cs46xx_peek(chip, BA1_PBA);
746 #endif
747 ptr -= cpcm->hw_buf.addr;
748 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
749 }
750
751 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(snd_pcm_substream_t * substream)
752 {
753 cs46xx_t *chip = snd_pcm_substream_chip(substream);
754 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
755 return ptr >> chip->capt.shift;
756 }
757
758 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(snd_pcm_substream_t * substream)
759 {
760 cs46xx_t *chip = snd_pcm_substream_chip(substream);
761 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
762 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
763 }
764
765 static int snd_cs46xx_playback_trigger(snd_pcm_substream_t * substream,
766 int cmd)
767 {
768 cs46xx_t *chip = snd_pcm_substream_chip(substream);
769 /*snd_pcm_runtime_t *runtime = substream->runtime;*/
770 int result = 0;
771
772 #ifdef CONFIG_SND_CS46XX_NEW_DSP
773 cs46xx_pcm_t *cpcm = substream->runtime->private_data;
774 if (! cpcm->pcm_channel) {
775 return -ENXIO;
776 }
777 #endif
778 switch (cmd) {
779 case SNDRV_PCM_TRIGGER_START:
780 case SNDRV_PCM_TRIGGER_RESUME:
781 #ifdef CONFIG_SND_CS46XX_NEW_DSP
782 /* magic value to unmute PCM stream playback volume */
783 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
784 SCBVolumeCtrl) << 2, 0x80008000);
785
786 if (cpcm->pcm_channel->unlinked)
787 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
788
789 if (substream->runtime->periods != CS46XX_FRAGS)
790 snd_cs46xx_playback_transfer(substream);
791 #else
792 spin_lock(&chip->reg_lock);
793 if (substream->runtime->periods != CS46XX_FRAGS)
794 snd_cs46xx_playback_transfer(substream);
795 { unsigned int tmp;
796 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
797 tmp &= 0x0000ffff;
798 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
799 }
800 spin_unlock(&chip->reg_lock);
801 #endif
802 break;
803 case SNDRV_PCM_TRIGGER_STOP:
804 case SNDRV_PCM_TRIGGER_SUSPEND:
805 #ifdef CONFIG_SND_CS46XX_NEW_DSP
806 /* magic mute channel */
807 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
808 SCBVolumeCtrl) << 2, 0xffffffff);
809
810 if (!cpcm->pcm_channel->unlinked)
811 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
812 #else
813 spin_lock(&chip->reg_lock);
814 { unsigned int tmp;
815 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
816 tmp &= 0x0000ffff;
817 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
818 }
819 spin_unlock(&chip->reg_lock);
820 #endif
821 break;
822 default:
823 result = -EINVAL;
824 break;
825 }
826
827 return result;
828 }
829
830 static int snd_cs46xx_capture_trigger(snd_pcm_substream_t * substream,
831 int cmd)
832 {
833 cs46xx_t *chip = snd_pcm_substream_chip(substream);
834 unsigned int tmp;
835 int result = 0;
836
837 spin_lock(&chip->reg_lock);
838 switch (cmd) {
839 case SNDRV_PCM_TRIGGER_START:
840 case SNDRV_PCM_TRIGGER_RESUME:
841 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
842 tmp &= 0xffff0000;
843 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
844 break;
845 case SNDRV_PCM_TRIGGER_STOP:
846 case SNDRV_PCM_TRIGGER_SUSPEND:
847 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
848 tmp &= 0xffff0000;
849 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
850 break;
851 default:
852 result = -EINVAL;
853 break;
854 }
855 spin_unlock(&chip->reg_lock);
856
857 return result;
858 }
859
860 #ifdef CONFIG_SND_CS46XX_NEW_DSP
861 static int _cs46xx_adjust_sample_rate (cs46xx_t *chip, cs46xx_pcm_t *cpcm,
862 int sample_rate)
863 {
864
865 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
866 if ( cpcm->pcm_channel == NULL) {
867 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
868 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
869 if (cpcm->pcm_channel == NULL) {
870 snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n");
871 return -ENOMEM;
872 }
873 cpcm->pcm_channel->sample_rate = sample_rate;
874 } else
875 /* if sample rate is changed */
876 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
877 int unlinked = cpcm->pcm_channel->unlinked;
878 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
879
880 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
881 cpcm->hw_buf.addr,
882 cpcm->pcm_channel_id)) == NULL) {
883 snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n");
884 return -ENOMEM;
885 }
886
887 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
888 cpcm->pcm_channel->sample_rate = sample_rate;
889 }
890
891 return 0;
892 }
893 #endif
894
895
896 static int snd_cs46xx_playback_hw_params(snd_pcm_substream_t * substream,
897 snd_pcm_hw_params_t * hw_params)
898 {
899 snd_pcm_runtime_t *runtime = substream->runtime;
900 cs46xx_pcm_t *cpcm;
901 int err;
902 #ifdef CONFIG_SND_CS46XX_NEW_DSP
903 cs46xx_t *chip = snd_pcm_substream_chip(substream);
904 int sample_rate = params_rate(hw_params);
905 int period_size = params_period_bytes(hw_params);
906 #endif
907 cpcm = runtime->private_data;
908
909 #ifdef CONFIG_SND_CS46XX_NEW_DSP
910 snd_assert (sample_rate != 0, return -ENXIO);
911
912 down (&chip->spos_mutex);
913
914 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
915 up (&chip->spos_mutex);
916 return -ENXIO;
917 }
918
919 snd_assert (cpcm->pcm_channel != NULL);
920 if (!cpcm->pcm_channel) {
921 up (&chip->spos_mutex);
922 return -ENXIO;
923 }
924
925
926 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
927 up (&chip->spos_mutex);
928 return -EINVAL;
929 }
930
931 snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
932 period_size, params_periods(hw_params),
933 params_buffer_bytes(hw_params));
934 #endif
935
936 if (params_periods(hw_params) == CS46XX_FRAGS) {
937 if (runtime->dma_area != cpcm->hw_buf.area)
938 snd_pcm_lib_free_pages(substream);
939 runtime->dma_area = cpcm->hw_buf.area;
940 runtime->dma_addr = cpcm->hw_buf.addr;
941 runtime->dma_bytes = cpcm->hw_buf.bytes;
942
943
944 #ifdef CONFIG_SND_CS46XX_NEW_DSP
945 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
946 substream->ops = &snd_cs46xx_playback_ops;
947 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
948 substream->ops = &snd_cs46xx_playback_rear_ops;
949 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
950 substream->ops = &snd_cs46xx_playback_clfe_ops;
951 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
952 substream->ops = &snd_cs46xx_playback_iec958_ops;
953 } else {
954 snd_assert(0);
955 }
956 #else
957 substream->ops = &snd_cs46xx_playback_ops;
958 #endif
959
960 } else {
961 if (runtime->dma_area == cpcm->hw_buf.area) {
962 runtime->dma_area = NULL;
963 runtime->dma_addr = 0;
964 runtime->dma_bytes = 0;
965 }
966 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
967 #ifdef CONFIG_SND_CS46XX_NEW_DSP
968 up (&chip->spos_mutex);
969 #endif
970 return err;
971 }
972
973 #ifdef CONFIG_SND_CS46XX_NEW_DSP
974 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
975 substream->ops = &snd_cs46xx_playback_indirect_ops;
976 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
977 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
978 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
979 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
980 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
981 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
982 } else {
983 snd_assert(0);
984 }
985 #else
986 substream->ops = &snd_cs46xx_playback_indirect_ops;
987 #endif
988
989 }
990
991 #ifdef CONFIG_SND_CS46XX_NEW_DSP
992 up (&chip->spos_mutex);
993 #endif
994
995 return 0;
996 }
997
998 static int snd_cs46xx_playback_hw_free(snd_pcm_substream_t * substream)
999 {
1000 /*cs46xx_t *chip = snd_pcm_substream_chip(substream);*/
1001 snd_pcm_runtime_t *runtime = substream->runtime;
1002 cs46xx_pcm_t *cpcm;
1003
1004 cpcm = runtime->private_data;
1005
1006 /* if play_back open fails, then this function
1007 is called and cpcm can actually be NULL here */
1008 if (!cpcm) return -ENXIO;
1009
1010 if (runtime->dma_area != cpcm->hw_buf.area)
1011 snd_pcm_lib_free_pages(substream);
1012
1013 runtime->dma_area = NULL;
1014 runtime->dma_addr = 0;
1015 runtime->dma_bytes = 0;
1016
1017 return 0;
1018 }
1019
1020 static int snd_cs46xx_playback_prepare(snd_pcm_substream_t * substream)
1021 {
1022 unsigned int tmp;
1023 unsigned int pfie;
1024 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1025 snd_pcm_runtime_t *runtime = substream->runtime;
1026 cs46xx_pcm_t *cpcm;
1027
1028 cpcm = runtime->private_data;
1029
1030 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1031 snd_assert (cpcm->pcm_channel != NULL, return -ENXIO);
1032
1033 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1034 pfie &= ~0x0000f03f;
1035 #else
1036 /* old dsp */
1037 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1038 pfie &= ~0x0000f03f;
1039 #endif
1040
1041 cpcm->shift = 2;
1042 /* if to convert from stereo to mono */
1043 if (runtime->channels == 1) {
1044 cpcm->shift--;
1045 pfie |= 0x00002000;
1046 }
1047 /* if to convert from 8 bit to 16 bit */
1048 if (snd_pcm_format_width(runtime->format) == 8) {
1049 cpcm->shift--;
1050 pfie |= 0x00001000;
1051 }
1052 /* if to convert to unsigned */
1053 if (snd_pcm_format_unsigned(runtime->format))
1054 pfie |= 0x00008000;
1055
1056 /* Never convert byte order when sample stream is 8 bit */
1057 if (snd_pcm_format_width(runtime->format) != 8) {
1058 /* convert from big endian to little endian */
1059 if (snd_pcm_format_big_endian(runtime->format))
1060 pfie |= 0x00004000;
1061 }
1062
1063 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1064 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1065 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1066
1067 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1068
1069 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1070 tmp &= ~0x000003ff;
1071 tmp |= (4 << cpcm->shift) - 1;
1072 /* playback transaction count register */
1073 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1074
1075 /* playback format && interrupt enable */
1076 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1077 #else
1078 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1079 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1080 tmp &= ~0x000003ff;
1081 tmp |= (4 << cpcm->shift) - 1;
1082 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1083 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1084 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1085 #endif
1086
1087 return 0;
1088 }
1089
1090 static int snd_cs46xx_capture_hw_params(snd_pcm_substream_t * substream,
1091 snd_pcm_hw_params_t * hw_params)
1092 {
1093 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1094 snd_pcm_runtime_t *runtime = substream->runtime;
1095 int err;
1096
1097 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1098 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1099 #endif
1100 if (runtime->periods == CS46XX_FRAGS) {
1101 if (runtime->dma_area != chip->capt.hw_buf.area)
1102 snd_pcm_lib_free_pages(substream);
1103 runtime->dma_area = chip->capt.hw_buf.area;
1104 runtime->dma_addr = chip->capt.hw_buf.addr;
1105 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1106 substream->ops = &snd_cs46xx_capture_ops;
1107 } else {
1108 if (runtime->dma_area == chip->capt.hw_buf.area) {
1109 runtime->dma_area = NULL;
1110 runtime->dma_addr = 0;
1111 runtime->dma_bytes = 0;
1112 }
1113 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1114 return err;
1115 substream->ops = &snd_cs46xx_capture_indirect_ops;
1116 }
1117
1118 return 0;
1119 }
1120
1121 static int snd_cs46xx_capture_hw_free(snd_pcm_substream_t * substream)
1122 {
1123 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1124 snd_pcm_runtime_t *runtime = substream->runtime;
1125
1126 if (runtime->dma_area != chip->capt.hw_buf.area)
1127 snd_pcm_lib_free_pages(substream);
1128 runtime->dma_area = NULL;
1129 runtime->dma_addr = 0;
1130 runtime->dma_bytes = 0;
1131
1132 return 0;
1133 }
1134
1135 static int snd_cs46xx_capture_prepare(snd_pcm_substream_t * substream)
1136 {
1137 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1138 snd_pcm_runtime_t *runtime = substream->runtime;
1139
1140 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1141 chip->capt.shift = 2;
1142 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1143 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1144 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1145 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1146
1147 return 0;
1148 }
1149
1150 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1151 {
1152 cs46xx_t *chip = dev_id;
1153 u32 status1;
1154 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1155 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1156 u32 status2;
1157 int i;
1158 cs46xx_pcm_t *cpcm = NULL;
1159 #endif
1160
1161 /*
1162 * Read the Interrupt Status Register to clear the interrupt
1163 */
1164 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1165 if ((status1 & 0x7fffffff) == 0) {
1166 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1167 return IRQ_NONE;
1168 }
1169
1170 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1171 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1172
1173 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1174 if (i <= 15) {
1175 if ( status1 & (1 << i) ) {
1176 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1177 if (chip->capt.substream)
1178 snd_pcm_period_elapsed(chip->capt.substream);
1179 } else {
1180 if (ins->pcm_channels[i].active &&
1181 ins->pcm_channels[i].private_data &&
1182 !ins->pcm_channels[i].unlinked) {
1183 cpcm = ins->pcm_channels[i].private_data;
1184 snd_pcm_period_elapsed(cpcm->substream);
1185 }
1186 }
1187 }
1188 } else {
1189 if ( status2 & (1 << (i - 16))) {
1190 if (ins->pcm_channels[i].active &&
1191 ins->pcm_channels[i].private_data &&
1192 !ins->pcm_channels[i].unlinked) {
1193 cpcm = ins->pcm_channels[i].private_data;
1194 snd_pcm_period_elapsed(cpcm->substream);
1195 }
1196 }
1197 }
1198 }
1199
1200 #else
1201 /* old dsp */
1202 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1203 if (chip->playback_pcm->substream)
1204 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1205 }
1206 if ((status1 & HISR_VC1) && chip->pcm) {
1207 if (chip->capt.substream)
1208 snd_pcm_period_elapsed(chip->capt.substream);
1209 }
1210 #endif
1211
1212 if ((status1 & HISR_MIDI) && chip->rmidi) {
1213 unsigned char c;
1214
1215 spin_lock(&chip->reg_lock);
1216 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1217 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1218 if ((chip->midcr & MIDCR_RIE) == 0)
1219 continue;
1220 spin_unlock(&chip->reg_lock);
1221 snd_rawmidi_receive(chip->midi_input, &c, 1);
1222 spin_lock(&chip->reg_lock);
1223 }
1224 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1225 if ((chip->midcr & MIDCR_TIE) == 0)
1226 break;
1227 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1228 chip->midcr &= ~MIDCR_TIE;
1229 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1230 break;
1231 }
1232 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1233 }
1234 spin_unlock(&chip->reg_lock);
1235 }
1236 /*
1237 * EOI to the PCI part....reenables interrupts
1238 */
1239 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1240
1241 return IRQ_HANDLED;
1242 }
1243
1244 static snd_pcm_hardware_t snd_cs46xx_playback =
1245 {
1246 .info = (SNDRV_PCM_INFO_MMAP |
1247 SNDRV_PCM_INFO_INTERLEAVED |
1248 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1249 SNDRV_PCM_INFO_RESUME),
1250 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1251 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1252 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1253 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1254 .rate_min = 5500,
1255 .rate_max = 48000,
1256 .channels_min = 1,
1257 .channels_max = 2,
1258 .buffer_bytes_max = (256 * 1024),
1259 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1260 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1261 .periods_min = CS46XX_FRAGS,
1262 .periods_max = 1024,
1263 .fifo_size = 0,
1264 };
1265
1266 static snd_pcm_hardware_t snd_cs46xx_capture =
1267 {
1268 .info = (SNDRV_PCM_INFO_MMAP |
1269 SNDRV_PCM_INFO_INTERLEAVED |
1270 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1271 SNDRV_PCM_INFO_RESUME),
1272 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1273 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1274 .rate_min = 5500,
1275 .rate_max = 48000,
1276 .channels_min = 2,
1277 .channels_max = 2,
1278 .buffer_bytes_max = (256 * 1024),
1279 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1280 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1281 .periods_min = CS46XX_FRAGS,
1282 .periods_max = 1024,
1283 .fifo_size = 0,
1284 };
1285
1286 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1287
1288 static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1289
1290 static snd_pcm_hw_constraint_list_t hw_constraints_period_sizes = {
1291 .count = ARRAY_SIZE(period_sizes),
1292 .list = period_sizes,
1293 .mask = 0
1294 };
1295
1296 #endif
1297
1298 static void snd_cs46xx_pcm_free_substream(snd_pcm_runtime_t *runtime)
1299 {
1300 cs46xx_pcm_t * cpcm = runtime->private_data;
1301 kfree(cpcm);
1302 }
1303
1304 static int _cs46xx_playback_open_channel (snd_pcm_substream_t * substream,int pcm_channel_id)
1305 {
1306 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1307 cs46xx_pcm_t * cpcm;
1308 snd_pcm_runtime_t *runtime = substream->runtime;
1309
1310 cpcm = kcalloc(1, sizeof(*cpcm), GFP_KERNEL);
1311 if (cpcm == NULL)
1312 return -ENOMEM;
1313 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1314 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1315 kfree(cpcm);
1316 return -ENOMEM;
1317 }
1318
1319 runtime->hw = snd_cs46xx_playback;
1320 runtime->private_data = cpcm;
1321 runtime->private_free = snd_cs46xx_pcm_free_substream;
1322
1323 cpcm->substream = substream;
1324 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1325 down (&chip->spos_mutex);
1326 cpcm->pcm_channel = NULL;
1327 cpcm->pcm_channel_id = pcm_channel_id;
1328
1329
1330 snd_pcm_hw_constraint_list(runtime, 0,
1331 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1332 &hw_constraints_period_sizes);
1333
1334 up (&chip->spos_mutex);
1335 #else
1336 chip->playback_pcm = cpcm; /* HACK */
1337 #endif
1338
1339 if (chip->accept_valid)
1340 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1341 chip->active_ctrl(chip, 1);
1342
1343 return 0;
1344 }
1345
1346 static int snd_cs46xx_playback_open(snd_pcm_substream_t * substream)
1347 {
1348 snd_printdd("open front channel\n");
1349 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1350 }
1351
1352 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1353 static int snd_cs46xx_playback_open_rear(snd_pcm_substream_t * substream)
1354 {
1355 snd_printdd("open rear channel\n");
1356
1357 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1358 }
1359
1360 static int snd_cs46xx_playback_open_clfe(snd_pcm_substream_t * substream)
1361 {
1362 snd_printdd("open center - LFE channel\n");
1363
1364 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1365 }
1366
1367 static int snd_cs46xx_playback_open_iec958(snd_pcm_substream_t * substream)
1368 {
1369 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1370
1371 snd_printdd("open raw iec958 channel\n");
1372
1373 down (&chip->spos_mutex);
1374 cs46xx_iec958_pre_open (chip);
1375 up (&chip->spos_mutex);
1376
1377 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1378 }
1379
1380 static int snd_cs46xx_playback_close(snd_pcm_substream_t * substream);
1381
1382 static int snd_cs46xx_playback_close_iec958(snd_pcm_substream_t * substream)
1383 {
1384 int err;
1385 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1386
1387 snd_printdd("close raw iec958 channel\n");
1388
1389 err = snd_cs46xx_playback_close(substream);
1390
1391 down (&chip->spos_mutex);
1392 cs46xx_iec958_post_close (chip);
1393 up (&chip->spos_mutex);
1394
1395 return err;
1396 }
1397 #endif
1398
1399 static int snd_cs46xx_capture_open(snd_pcm_substream_t * substream)
1400 {
1401 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1402
1403 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1404 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1405 return -ENOMEM;
1406 chip->capt.substream = substream;
1407 substream->runtime->hw = snd_cs46xx_capture;
1408
1409 if (chip->accept_valid)
1410 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1411
1412 chip->active_ctrl(chip, 1);
1413
1414 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1415 snd_pcm_hw_constraint_list(substream->runtime, 0,
1416 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1417 &hw_constraints_period_sizes);
1418 #endif
1419 return 0;
1420 }
1421
1422 static int snd_cs46xx_playback_close(snd_pcm_substream_t * substream)
1423 {
1424 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1425 snd_pcm_runtime_t *runtime = substream->runtime;
1426 cs46xx_pcm_t * cpcm;
1427
1428 cpcm = runtime->private_data;
1429
1430 /* when playback_open fails, then cpcm can be NULL */
1431 if (!cpcm) return -ENXIO;
1432
1433 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1434 down (&chip->spos_mutex);
1435 if (cpcm->pcm_channel) {
1436 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1437 cpcm->pcm_channel = NULL;
1438 }
1439 up (&chip->spos_mutex);
1440 #else
1441 chip->playback_pcm = NULL;
1442 #endif
1443
1444 cpcm->substream = NULL;
1445 snd_dma_free_pages(&cpcm->hw_buf);
1446 chip->active_ctrl(chip, -1);
1447
1448 return 0;
1449 }
1450
1451 static int snd_cs46xx_capture_close(snd_pcm_substream_t * substream)
1452 {
1453 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1454
1455 chip->capt.substream = NULL;
1456 snd_dma_free_pages(&chip->capt.hw_buf);
1457 chip->active_ctrl(chip, -1);
1458
1459 return 0;
1460 }
1461
1462 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1463 static snd_pcm_ops_t snd_cs46xx_playback_rear_ops = {
1464 .open = snd_cs46xx_playback_open_rear,
1465 .close = snd_cs46xx_playback_close,
1466 .ioctl = snd_pcm_lib_ioctl,
1467 .hw_params = snd_cs46xx_playback_hw_params,
1468 .hw_free = snd_cs46xx_playback_hw_free,
1469 .prepare = snd_cs46xx_playback_prepare,
1470 .trigger = snd_cs46xx_playback_trigger,
1471 .pointer = snd_cs46xx_playback_direct_pointer,
1472 };
1473
1474 static snd_pcm_ops_t snd_cs46xx_playback_indirect_rear_ops = {
1475 .open = snd_cs46xx_playback_open_rear,
1476 .close = snd_cs46xx_playback_close,
1477 .ioctl = snd_pcm_lib_ioctl,
1478 .hw_params = snd_cs46xx_playback_hw_params,
1479 .hw_free = snd_cs46xx_playback_hw_free,
1480 .prepare = snd_cs46xx_playback_prepare,
1481 .trigger = snd_cs46xx_playback_trigger,
1482 .pointer = snd_cs46xx_playback_indirect_pointer,
1483 .ack = snd_cs46xx_playback_transfer,
1484 };
1485
1486 static snd_pcm_ops_t snd_cs46xx_playback_clfe_ops = {
1487 .open = snd_cs46xx_playback_open_clfe,
1488 .close = snd_cs46xx_playback_close,
1489 .ioctl = snd_pcm_lib_ioctl,
1490 .hw_params = snd_cs46xx_playback_hw_params,
1491 .hw_free = snd_cs46xx_playback_hw_free,
1492 .prepare = snd_cs46xx_playback_prepare,
1493 .trigger = snd_cs46xx_playback_trigger,
1494 .pointer = snd_cs46xx_playback_direct_pointer,
1495 };
1496
1497 static snd_pcm_ops_t snd_cs46xx_playback_indirect_clfe_ops = {
1498 .open = snd_cs46xx_playback_open_clfe,
1499 .close = snd_cs46xx_playback_close,
1500 .ioctl = snd_pcm_lib_ioctl,
1501 .hw_params = snd_cs46xx_playback_hw_params,
1502 .hw_free = snd_cs46xx_playback_hw_free,
1503 .prepare = snd_cs46xx_playback_prepare,
1504 .trigger = snd_cs46xx_playback_trigger,
1505 .pointer = snd_cs46xx_playback_indirect_pointer,
1506 .ack = snd_cs46xx_playback_transfer,
1507 };
1508
1509 static snd_pcm_ops_t snd_cs46xx_playback_iec958_ops = {
1510 .open = snd_cs46xx_playback_open_iec958,
1511 .close = snd_cs46xx_playback_close_iec958,
1512 .ioctl = snd_pcm_lib_ioctl,
1513 .hw_params = snd_cs46xx_playback_hw_params,
1514 .hw_free = snd_cs46xx_playback_hw_free,
1515 .prepare = snd_cs46xx_playback_prepare,
1516 .trigger = snd_cs46xx_playback_trigger,
1517 .pointer = snd_cs46xx_playback_direct_pointer,
1518 };
1519
1520 static snd_pcm_ops_t snd_cs46xx_playback_indirect_iec958_ops = {
1521 .open = snd_cs46xx_playback_open_iec958,
1522 .close = snd_cs46xx_playback_close_iec958,
1523 .ioctl = snd_pcm_lib_ioctl,
1524 .hw_params = snd_cs46xx_playback_hw_params,
1525 .hw_free = snd_cs46xx_playback_hw_free,
1526 .prepare = snd_cs46xx_playback_prepare,
1527 .trigger = snd_cs46xx_playback_trigger,
1528 .pointer = snd_cs46xx_playback_indirect_pointer,
1529 .ack = snd_cs46xx_playback_transfer,
1530 };
1531
1532 #endif
1533
1534 static snd_pcm_ops_t snd_cs46xx_playback_ops = {
1535 .open = snd_cs46xx_playback_open,
1536 .close = snd_cs46xx_playback_close,
1537 .ioctl = snd_pcm_lib_ioctl,
1538 .hw_params = snd_cs46xx_playback_hw_params,
1539 .hw_free = snd_cs46xx_playback_hw_free,
1540 .prepare = snd_cs46xx_playback_prepare,
1541 .trigger = snd_cs46xx_playback_trigger,
1542 .pointer = snd_cs46xx_playback_direct_pointer,
1543 };
1544
1545 static snd_pcm_ops_t snd_cs46xx_playback_indirect_ops = {
1546 .open = snd_cs46xx_playback_open,
1547 .close = snd_cs46xx_playback_close,
1548 .ioctl = snd_pcm_lib_ioctl,
1549 .hw_params = snd_cs46xx_playback_hw_params,
1550 .hw_free = snd_cs46xx_playback_hw_free,
1551 .prepare = snd_cs46xx_playback_prepare,
1552 .trigger = snd_cs46xx_playback_trigger,
1553 .pointer = snd_cs46xx_playback_indirect_pointer,
1554 .ack = snd_cs46xx_playback_transfer,
1555 };
1556
1557 static snd_pcm_ops_t snd_cs46xx_capture_ops = {
1558 .open = snd_cs46xx_capture_open,
1559 .close = snd_cs46xx_capture_close,
1560 .ioctl = snd_pcm_lib_ioctl,
1561 .hw_params = snd_cs46xx_capture_hw_params,
1562 .hw_free = snd_cs46xx_capture_hw_free,
1563 .prepare = snd_cs46xx_capture_prepare,
1564 .trigger = snd_cs46xx_capture_trigger,
1565 .pointer = snd_cs46xx_capture_direct_pointer,
1566 };
1567
1568 static snd_pcm_ops_t snd_cs46xx_capture_indirect_ops = {
1569 .open = snd_cs46xx_capture_open,
1570 .close = snd_cs46xx_capture_close,
1571 .ioctl = snd_pcm_lib_ioctl,
1572 .hw_params = snd_cs46xx_capture_hw_params,
1573 .hw_free = snd_cs46xx_capture_hw_free,
1574 .prepare = snd_cs46xx_capture_prepare,
1575 .trigger = snd_cs46xx_capture_trigger,
1576 .pointer = snd_cs46xx_capture_indirect_pointer,
1577 .ack = snd_cs46xx_capture_transfer,
1578 };
1579
1580 static void snd_cs46xx_pcm_free(snd_pcm_t *pcm)
1581 {
1582 cs46xx_t *chip = pcm->private_data;
1583 chip->pcm = NULL;
1584 snd_pcm_lib_preallocate_free_for_all(pcm);
1585 }
1586
1587 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1588 static void snd_cs46xx_pcm_rear_free(snd_pcm_t *pcm)
1589 {
1590 cs46xx_t *chip = pcm->private_data;
1591 chip->pcm_rear = NULL;
1592 snd_pcm_lib_preallocate_free_for_all(pcm);
1593 }
1594
1595 static void snd_cs46xx_pcm_center_lfe_free(snd_pcm_t *pcm)
1596 {
1597 cs46xx_t *chip = pcm->private_data;
1598 chip->pcm_center_lfe = NULL;
1599 snd_pcm_lib_preallocate_free_for_all(pcm);
1600 }
1601
1602 static void snd_cs46xx_pcm_iec958_free(snd_pcm_t *pcm)
1603 {
1604 cs46xx_t *chip = pcm->private_data;
1605 chip->pcm_iec958 = NULL;
1606 snd_pcm_lib_preallocate_free_for_all(pcm);
1607 }
1608
1609 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1610 #else
1611 #define MAX_PLAYBACK_CHANNELS 1
1612 #endif
1613
1614 int __devinit snd_cs46xx_pcm(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1615 {
1616 snd_pcm_t *pcm;
1617 int err;
1618
1619 if (rpcm)
1620 *rpcm = NULL;
1621 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1622 return err;
1623
1624 pcm->private_data = chip;
1625 pcm->private_free = snd_cs46xx_pcm_free;
1626
1627 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1628 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1629
1630 /* global setup */
1631 pcm->info_flags = 0;
1632 strcpy(pcm->name, "CS46xx");
1633 chip->pcm = pcm;
1634
1635 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1636 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1637
1638 if (rpcm)
1639 *rpcm = pcm;
1640
1641 return 0;
1642 }
1643
1644
1645 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1646 int __devinit snd_cs46xx_pcm_rear(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1647 {
1648 snd_pcm_t *pcm;
1649 int err;
1650
1651 if (rpcm)
1652 *rpcm = NULL;
1653
1654 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1655 return err;
1656
1657 pcm->private_data = chip;
1658 pcm->private_free = snd_cs46xx_pcm_rear_free;
1659
1660 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1661
1662 /* global setup */
1663 pcm->info_flags = 0;
1664 strcpy(pcm->name, "CS46xx - Rear");
1665 chip->pcm_rear = pcm;
1666
1667 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1668 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1669
1670 if (rpcm)
1671 *rpcm = pcm;
1672
1673 return 0;
1674 }
1675
1676 int __devinit snd_cs46xx_pcm_center_lfe(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1677 {
1678 snd_pcm_t *pcm;
1679 int err;
1680
1681 if (rpcm)
1682 *rpcm = NULL;
1683
1684 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1685 return err;
1686
1687 pcm->private_data = chip;
1688 pcm->private_free = snd_cs46xx_pcm_center_lfe_free;
1689
1690 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1691
1692 /* global setup */
1693 pcm->info_flags = 0;
1694 strcpy(pcm->name, "CS46xx - Center LFE");
1695 chip->pcm_center_lfe = pcm;
1696
1697 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1698 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1699
1700 if (rpcm)
1701 *rpcm = pcm;
1702
1703 return 0;
1704 }
1705
1706 int __devinit snd_cs46xx_pcm_iec958(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1707 {
1708 snd_pcm_t *pcm;
1709 int err;
1710
1711 if (rpcm)
1712 *rpcm = NULL;
1713
1714 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1715 return err;
1716
1717 pcm->private_data = chip;
1718 pcm->private_free = snd_cs46xx_pcm_iec958_free;
1719
1720 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1721
1722 /* global setup */
1723 pcm->info_flags = 0;
1724 strcpy(pcm->name, "CS46xx - IEC958");
1725 chip->pcm_rear = pcm;
1726
1727 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1728 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1729
1730 if (rpcm)
1731 *rpcm = pcm;
1732
1733 return 0;
1734 }
1735 #endif
1736
1737 /*
1738 * Mixer routines
1739 */
1740 static void snd_cs46xx_mixer_free_ac97_bus(ac97_bus_t *bus)
1741 {
1742 cs46xx_t *chip = bus->private_data;
1743
1744 chip->ac97_bus = NULL;
1745 }
1746
1747 static void snd_cs46xx_mixer_free_ac97(ac97_t *ac97)
1748 {
1749 cs46xx_t *chip = ac97->private_data;
1750
1751 snd_assert ((ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) ||
1752 (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]),
1753 return);
1754
1755 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1756 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1757 chip->eapd_switch = NULL;
1758 }
1759 else
1760 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1761 }
1762
1763 static int snd_cs46xx_vol_info(snd_kcontrol_t *kcontrol,
1764 snd_ctl_elem_info_t *uinfo)
1765 {
1766 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1767 uinfo->count = 2;
1768 uinfo->value.integer.min = 0;
1769 uinfo->value.integer.max = 0x7fff;
1770 return 0;
1771 }
1772
1773 static int snd_cs46xx_vol_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1774 {
1775 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1776 int reg = kcontrol->private_value;
1777 unsigned int val = snd_cs46xx_peek(chip, reg);
1778 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1779 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1780 return 0;
1781 }
1782
1783 static int snd_cs46xx_vol_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1784 {
1785 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1786 int reg = kcontrol->private_value;
1787 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1788 (0xffff - ucontrol->value.integer.value[1]));
1789 unsigned int old = snd_cs46xx_peek(chip, reg);
1790 int change = (old != val);
1791
1792 if (change) {
1793 snd_cs46xx_poke(chip, reg, val);
1794 }
1795
1796 return change;
1797 }
1798
1799 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1800
1801 static int snd_cs46xx_vol_dac_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1802 {
1803 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1804
1805 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1806 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1807
1808 return 0;
1809 }
1810
1811 static int snd_cs46xx_vol_dac_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1812 {
1813 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1814 int change = 0;
1815
1816 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1817 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1818 cs46xx_dsp_set_dac_volume(chip,
1819 ucontrol->value.integer.value[0],
1820 ucontrol->value.integer.value[1]);
1821 change = 1;
1822 }
1823
1824 return change;
1825 }
1826
1827 #if 0
1828 static int snd_cs46xx_vol_iec958_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1829 {
1830 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1831
1832 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1833 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1834 return 0;
1835 }
1836
1837 static int snd_cs46xx_vol_iec958_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1838 {
1839 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1840 int change = 0;
1841
1842 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1843 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1844 cs46xx_dsp_set_iec958_volume (chip,
1845 ucontrol->value.integer.value[0],
1846 ucontrol->value.integer.value[1]);
1847 change = 1;
1848 }
1849
1850 return change;
1851 }
1852 #endif
1853
1854 static int snd_mixer_boolean_info(snd_kcontrol_t *kcontrol,
1855 snd_ctl_elem_info_t *uinfo)
1856 {
1857 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1858 uinfo->count = 1;
1859 uinfo->value.integer.min = 0;
1860 uinfo->value.integer.max = 1;
1861 return 0;
1862 }
1863
1864 static int snd_cs46xx_iec958_get(snd_kcontrol_t *kcontrol,
1865 snd_ctl_elem_value_t *ucontrol)
1866 {
1867 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1868 int reg = kcontrol->private_value;
1869
1870 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1871 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1872 else
1873 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1874
1875 return 0;
1876 }
1877
1878 static int snd_cs46xx_iec958_put(snd_kcontrol_t *kcontrol,
1879 snd_ctl_elem_value_t *ucontrol)
1880 {
1881 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1882 int change, res;
1883
1884 switch (kcontrol->private_value) {
1885 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1886 down (&chip->spos_mutex);
1887 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1888 if (ucontrol->value.integer.value[0] && !change)
1889 cs46xx_dsp_enable_spdif_out(chip);
1890 else if (change && !ucontrol->value.integer.value[0])
1891 cs46xx_dsp_disable_spdif_out(chip);
1892
1893 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1894 up (&chip->spos_mutex);
1895 break;
1896 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1897 change = chip->dsp_spos_instance->spdif_status_in;
1898 if (ucontrol->value.integer.value[0] && !change) {
1899 cs46xx_dsp_enable_spdif_in(chip);
1900 /* restore volume */
1901 }
1902 else if (change && !ucontrol->value.integer.value[0])
1903 cs46xx_dsp_disable_spdif_in(chip);
1904
1905 res = (change != chip->dsp_spos_instance->spdif_status_in);
1906 break;
1907 default:
1908 res = -EINVAL;
1909 snd_assert(0, (void)0);
1910 }
1911
1912 return res;
1913 }
1914
1915 static int snd_cs46xx_adc_capture_get(snd_kcontrol_t *kcontrol,
1916 snd_ctl_elem_value_t *ucontrol)
1917 {
1918 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1919 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1920
1921 if (ins->adc_input != NULL)
1922 ucontrol->value.integer.value[0] = 1;
1923 else
1924 ucontrol->value.integer.value[0] = 0;
1925
1926 return 0;
1927 }
1928
1929 static int snd_cs46xx_adc_capture_put(snd_kcontrol_t *kcontrol,
1930 snd_ctl_elem_value_t *ucontrol)
1931 {
1932 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1933 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1934 int change = 0;
1935
1936 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
1937 cs46xx_dsp_enable_adc_capture(chip);
1938 change = 1;
1939 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
1940 cs46xx_dsp_disable_adc_capture(chip);
1941 change = 1;
1942 }
1943 return change;
1944 }
1945
1946 static int snd_cs46xx_pcm_capture_get(snd_kcontrol_t *kcontrol,
1947 snd_ctl_elem_value_t *ucontrol)
1948 {
1949 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1950 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1951
1952 if (ins->pcm_input != NULL)
1953 ucontrol->value.integer.value[0] = 1;
1954 else
1955 ucontrol->value.integer.value[0] = 0;
1956
1957 return 0;
1958 }
1959
1960
1961 static int snd_cs46xx_pcm_capture_put(snd_kcontrol_t *kcontrol,
1962 snd_ctl_elem_value_t *ucontrol)
1963 {
1964 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1965 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1966 int change = 0;
1967
1968 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
1969 cs46xx_dsp_enable_pcm_capture(chip);
1970 change = 1;
1971 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
1972 cs46xx_dsp_disable_pcm_capture(chip);
1973 change = 1;
1974 }
1975
1976 return change;
1977 }
1978
1979 static int snd_herc_spdif_select_get(snd_kcontrol_t *kcontrol,
1980 snd_ctl_elem_value_t *ucontrol)
1981 {
1982 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1983
1984 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1985
1986 if (val1 & EGPIODR_GPOE0)
1987 ucontrol->value.integer.value[0] = 1;
1988 else
1989 ucontrol->value.integer.value[0] = 0;
1990
1991 return 0;
1992 }
1993
1994 /*
1995 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
1996 */
1997 static int snd_herc_spdif_select_put(snd_kcontrol_t *kcontrol,
1998 snd_ctl_elem_value_t *ucontrol)
1999 {
2000 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2001 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2002 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2003
2004 if (ucontrol->value.integer.value[0]) {
2005 /* optical is default */
2006 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2007 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
2008 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2009 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2010 } else {
2011 /* coaxial */
2012 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2013 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2014 }
2015
2016 /* checking diff from the EGPIO direction register
2017 should be enough */
2018 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2019 }
2020
2021
2022 static int snd_cs46xx_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2023 {
2024 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2025 uinfo->count = 1;
2026 return 0;
2027 }
2028
2029 static int snd_cs46xx_spdif_default_get(snd_kcontrol_t * kcontrol,
2030 snd_ctl_elem_value_t * ucontrol)
2031 {
2032 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2033 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2034
2035 down (&chip->spos_mutex);
2036 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2037 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2038 ucontrol->value.iec958.status[2] = 0;
2039 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2040 up (&chip->spos_mutex);
2041
2042 return 0;
2043 }
2044
2045 static int snd_cs46xx_spdif_default_put(snd_kcontrol_t * kcontrol,
2046 snd_ctl_elem_value_t * ucontrol)
2047 {
2048 cs46xx_t * chip = snd_kcontrol_chip(kcontrol);
2049 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2050 unsigned int val;
2051 int change;
2052
2053 down (&chip->spos_mutex);
2054 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2055 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2056 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2057 /* left and right validity bit */
2058 (1 << 13) | (1 << 12);
2059
2060
2061 change = (unsigned int)ins->spdif_csuv_default != val;
2062 ins->spdif_csuv_default = val;
2063
2064 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2065 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2066
2067 up (&chip->spos_mutex);
2068
2069 return change;
2070 }
2071
2072 static int snd_cs46xx_spdif_mask_get(snd_kcontrol_t * kcontrol,
2073 snd_ctl_elem_value_t * ucontrol)
2074 {
2075 ucontrol->value.iec958.status[0] = 0xff;
2076 ucontrol->value.iec958.status[1] = 0xff;
2077 ucontrol->value.iec958.status[2] = 0x00;
2078 ucontrol->value.iec958.status[3] = 0xff;
2079 return 0;
2080 }
2081
2082 static int snd_cs46xx_spdif_stream_get(snd_kcontrol_t * kcontrol,
2083 snd_ctl_elem_value_t * ucontrol)
2084 {
2085 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2086 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2087
2088 down (&chip->spos_mutex);
2089 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2090 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2091 ucontrol->value.iec958.status[2] = 0;
2092 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2093 up (&chip->spos_mutex);
2094
2095 return 0;
2096 }
2097
2098 static int snd_cs46xx_spdif_stream_put(snd_kcontrol_t * kcontrol,
2099 snd_ctl_elem_value_t * ucontrol)
2100 {
2101 cs46xx_t * chip = snd_kcontrol_chip(kcontrol);
2102 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2103 unsigned int val;
2104 int change;
2105
2106 down (&chip->spos_mutex);
2107 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2108 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2109 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2110 /* left and right validity bit */
2111 (1 << 13) | (1 << 12);
2112
2113
2114 change = ins->spdif_csuv_stream != val;
2115 ins->spdif_csuv_stream = val;
2116
2117 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2118 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2119
2120 up (&chip->spos_mutex);
2121
2122 return change;
2123 }
2124
2125 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2126
2127
2128 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2129 static int snd_cs46xx_egpio_select_info(snd_kcontrol_t *kcontrol,
2130 snd_ctl_elem_info_t *uinfo)
2131 {
2132 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2133 uinfo->count = 1;
2134 uinfo->value.integer.min = 0;
2135 uinfo->value.integer.max = 8;
2136 return 0;
2137 }
2138
2139 static int snd_cs46xx_egpio_select_get(snd_kcontrol_t *kcontrol,
2140 snd_ctl_elem_value_t *ucontrol)
2141 {
2142 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2143 ucontrol->value.integer.value[0] = chip->current_gpio;
2144
2145 return 0;
2146 }
2147
2148 static int snd_cs46xx_egpio_select_put(snd_kcontrol_t *kcontrol,
2149 snd_ctl_elem_value_t *ucontrol)
2150 {
2151 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2152 int change = (chip->current_gpio != ucontrol->value.integer.value[0]);
2153 chip->current_gpio = ucontrol->value.integer.value[0];
2154
2155 return change;
2156 }
2157
2158
2159 static int snd_cs46xx_egpio_get(snd_kcontrol_t *kcontrol,
2160 snd_ctl_elem_value_t *ucontrol)
2161 {
2162 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2163 int reg = kcontrol->private_value;
2164
2165 snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2166 ucontrol->value.integer.value[0] =
2167 (snd_cs46xx_peekBA0(chip, reg) & (1 << chip->current_gpio)) ? 1 : 0;
2168
2169 return 0;
2170 }
2171
2172 static int snd_cs46xx_egpio_put(snd_kcontrol_t *kcontrol,
2173 snd_ctl_elem_value_t *ucontrol)
2174 {
2175 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2176 int reg = kcontrol->private_value;
2177 int val = snd_cs46xx_peekBA0(chip, reg);
2178 int oldval = val;
2179 snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2180
2181 if (ucontrol->value.integer.value[0])
2182 val |= (1 << chip->current_gpio);
2183 else
2184 val &= ~(1 << chip->current_gpio);
2185
2186 snd_cs46xx_pokeBA0(chip, reg,val);
2187 snd_printdd ("put: val %08x oldval %08x\n",val,oldval);
2188
2189 return (oldval != val);
2190 }
2191 #endif /* CONFIG_SND_CS46XX_DEBUG_GPIO */
2192
2193 static snd_kcontrol_new_t snd_cs46xx_controls[] __devinitdata = {
2194 {
2195 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2196 .name = "DAC Volume",
2197 .info = snd_cs46xx_vol_info,
2198 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2199 .get = snd_cs46xx_vol_get,
2200 .put = snd_cs46xx_vol_put,
2201 .private_value = BA1_PVOL,
2202 #else
2203 .get = snd_cs46xx_vol_dac_get,
2204 .put = snd_cs46xx_vol_dac_put,
2205 #endif
2206 },
2207
2208 {
2209 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2210 .name = "ADC Volume",
2211 .info = snd_cs46xx_vol_info,
2212 .get = snd_cs46xx_vol_get,
2213 .put = snd_cs46xx_vol_put,
2214 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2215 .private_value = BA1_CVOL,
2216 #else
2217 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2218 #endif
2219 },
2220 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2221 {
2222 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2223 .name = "ADC Capture Switch",
2224 .info = snd_mixer_boolean_info,
2225 .get = snd_cs46xx_adc_capture_get,
2226 .put = snd_cs46xx_adc_capture_put
2227 },
2228 {
2229 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2230 .name = "DAC Capture Switch",
2231 .info = snd_mixer_boolean_info,
2232 .get = snd_cs46xx_pcm_capture_get,
2233 .put = snd_cs46xx_pcm_capture_put
2234 },
2235 {
2236 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2237 .name = "IEC958 Output Switch",
2238 .info = snd_mixer_boolean_info,
2239 .get = snd_cs46xx_iec958_get,
2240 .put = snd_cs46xx_iec958_put,
2241 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2242 },
2243 {
2244 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2245 .name = "IEC958 Input Switch",
2246 .info = snd_mixer_boolean_info,
2247 .get = snd_cs46xx_iec958_get,
2248 .put = snd_cs46xx_iec958_put,
2249 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2250 },
2251 #if 0
2252 /* Input IEC958 volume does not work for the moment. (Benny) */
2253 {
2254 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2255 .name = "IEC958 Input Volume",
2256 .info = snd_cs46xx_vol_info,
2257 .get = snd_cs46xx_vol_iec958_get,
2258 .put = snd_cs46xx_vol_iec958_put,
2259 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2260 },
2261 #endif
2262 {
2263 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2264 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2265 .info = snd_cs46xx_spdif_info,
2266 .get = snd_cs46xx_spdif_default_get,
2267 .put = snd_cs46xx_spdif_default_put,
2268 },
2269 {
2270 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2271 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2272 .info = snd_cs46xx_spdif_info,
2273 .get = snd_cs46xx_spdif_mask_get,
2274 .access = SNDRV_CTL_ELEM_ACCESS_READ
2275 },
2276 {
2277 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2278 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2279 .info = snd_cs46xx_spdif_info,
2280 .get = snd_cs46xx_spdif_stream_get,
2281 .put = snd_cs46xx_spdif_stream_put
2282 },
2283
2284 #endif
2285 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2286 {
2287 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2288 .name = "EGPIO select",
2289 .info = snd_cs46xx_egpio_select_info,
2290 .get = snd_cs46xx_egpio_select_get,
2291 .put = snd_cs46xx_egpio_select_put,
2292 .private_value = 0,
2293 },
2294 {
2295 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2296 .name = "EGPIO Input/Output",
2297 .info = snd_mixer_boolean_info,
2298 .get = snd_cs46xx_egpio_get,
2299 .put = snd_cs46xx_egpio_put,
2300 .private_value = BA0_EGPIODR,
2301 },
2302 {
2303 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2304 .name = "EGPIO CMOS/Open drain",
2305 .info = snd_mixer_boolean_info,
2306 .get = snd_cs46xx_egpio_get,
2307 .put = snd_cs46xx_egpio_put,
2308 .private_value = BA0_EGPIOPTR,
2309 },
2310 {
2311 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2312 .name = "EGPIO On/Off",
2313 .info = snd_mixer_boolean_info,
2314 .get = snd_cs46xx_egpio_get,
2315 .put = snd_cs46xx_egpio_put,
2316 .private_value = BA0_EGPIOSR,
2317 },
2318 #endif
2319 };
2320
2321 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2322 /* set primary cs4294 codec into Extended Audio Mode */
2323 static int snd_cs46xx_front_dup_get(snd_kcontrol_t *kcontrol,
2324 snd_ctl_elem_value_t *ucontrol)
2325 {
2326 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2327 unsigned short val;
2328 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2329 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2330 return 0;
2331 }
2332
2333 static int snd_cs46xx_front_dup_put(snd_kcontrol_t *kcontrol,
2334 snd_ctl_elem_value_t *ucontrol)
2335 {
2336 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2337 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2338 AC97_CSR_ACMODE, 0x200,
2339 ucontrol->value.integer.value[0] ? 0 : 0x200);
2340 }
2341
2342 static snd_kcontrol_new_t snd_cs46xx_front_dup_ctl = {
2343 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2344 .name = "Duplicate Front",
2345 .info = snd_mixer_boolean_info,
2346 .get = snd_cs46xx_front_dup_get,
2347 .put = snd_cs46xx_front_dup_put,
2348 };
2349 #endif
2350
2351 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2352 /* Only available on the Hercules Game Theater XP soundcard */
2353 static snd_kcontrol_new_t snd_hercules_controls[] __devinitdata = {
2354 {
2355 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2356 .name = "Optical/Coaxial SPDIF Input Switch",
2357 .info = snd_mixer_boolean_info,
2358 .get = snd_herc_spdif_select_get,
2359 .put = snd_herc_spdif_select_put,
2360 },
2361 };
2362
2363
2364 static void snd_cs46xx_codec_reset (ac97_t * ac97)
2365 {
2366 unsigned long end_time;
2367 int err;
2368
2369 /* reset to defaults */
2370 snd_ac97_write(ac97, AC97_RESET, 0);
2371
2372 /* set the desired CODEC mode */
2373 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2374 snd_printdd("cs46xx: CODOEC1 mode %04x\n",0x0);
2375 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x0);
2376 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2377 snd_printdd("cs46xx: CODOEC2 mode %04x\n",0x3);
2378 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x3);
2379 } else {
2380 snd_assert(0); /* should never happen ... */
2381 }
2382
2383 udelay(50);
2384
2385 /* it's necessary to wait awhile until registers are accessible after RESET */
2386 /* because the PCM or MASTER volume registers can be modified, */
2387 /* the REC_GAIN register is used for tests */
2388 end_time = jiffies + HZ;
2389 do {
2390 unsigned short ext_mid;
2391
2392 /* use preliminary reads to settle the communication */
2393 snd_ac97_read(ac97, AC97_RESET);
2394 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2395 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2396 /* modem? */
2397 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2398 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2399 return;
2400
2401 /* test if we can write to the record gain volume register */
2402 snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x8a05);
2403 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2404 return;
2405
2406 set_current_state(TASK_UNINTERRUPTIBLE);
2407 schedule_timeout(HZ/100);
2408 } while (time_after_eq(end_time, jiffies));
2409
2410 snd_printk("CS46xx secondary codec dont respond!\n");
2411 }
2412 #endif
2413
2414 static int __devinit cs46xx_detect_codec(cs46xx_t *chip, int codec)
2415 {
2416 int idx, err;
2417 ac97_template_t ac97;
2418
2419 memset(&ac97, 0, sizeof(ac97));
2420 ac97.private_data = chip;
2421 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2422 ac97.num = codec;
2423 if (chip->amplifier_ctrl == amp_voyetra)
2424 ac97.scaps = AC97_SCAP_INV_EAPD;
2425
2426 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2427 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2428 udelay(10);
2429 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2430 snd_printdd("snd_cs46xx: seconadry codec not present\n");
2431 return -ENXIO;
2432 }
2433 }
2434
2435 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2436 for (idx = 0; idx < 100; ++idx) {
2437 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2438 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2439 return err;
2440 }
2441 set_current_state(TASK_INTERRUPTIBLE);
2442 schedule_timeout(HZ/100);
2443 }
2444 snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec);
2445 return -ENXIO;
2446 }
2447
2448 int __devinit snd_cs46xx_mixer(cs46xx_t *chip)
2449 {
2450 snd_card_t *card = chip->card;
2451 snd_ctl_elem_id_t id;
2452 int err;
2453 unsigned int idx;
2454 static ac97_bus_ops_t ops = {
2455 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2456 .reset = snd_cs46xx_codec_reset,
2457 #endif
2458 .write = snd_cs46xx_ac97_write,
2459 .read = snd_cs46xx_ac97_read,
2460 };
2461
2462 /* detect primary codec */
2463 chip->nr_ac97_codecs = 0;
2464 snd_printdd("snd_cs46xx: detecting primary codec\n");
2465 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2466 return err;
2467 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2468
2469 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2470 return -ENXIO;
2471 chip->nr_ac97_codecs = 1;
2472
2473 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2474 snd_printdd("snd_cs46xx: detecting seconadry codec\n");
2475 /* try detect a secondary codec */
2476 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2477 chip->nr_ac97_codecs = 2;
2478 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2479
2480 /* add cs4630 mixer controls */
2481 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2482 snd_kcontrol_t *kctl;
2483 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2484 if ((err = snd_ctl_add(card, kctl)) < 0)
2485 return err;
2486 }
2487
2488 /* get EAPD mixer switch (for voyetra hack) */
2489 memset(&id, 0, sizeof(id));
2490 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2491 strcpy(id.name, "External Amplifier");
2492 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2493
2494 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2495 if (chip->nr_ac97_codecs == 1) {
2496 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2497 if (id2 == 0x592b || id2 == 0x592d) {
2498 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2499 if (err < 0)
2500 return err;
2501 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2502 AC97_CSR_ACMODE, 0x200);
2503 }
2504 }
2505 /* do soundcard specific mixer setup */
2506 if (chip->mixer_init) {
2507 snd_printdd ("calling chip->mixer_init(chip);\n");
2508 chip->mixer_init(chip);
2509 }
2510 #endif
2511
2512 /* turn on amplifier */
2513 chip->amplifier_ctrl(chip, 1);
2514
2515 return 0;
2516 }
2517
2518 /*
2519 * RawMIDI interface
2520 */
2521
2522 static void snd_cs46xx_midi_reset(cs46xx_t *chip)
2523 {
2524 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2525 udelay(100);
2526 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2527 }
2528
2529 static int snd_cs46xx_midi_input_open(snd_rawmidi_substream_t * substream)
2530 {
2531 cs46xx_t *chip = substream->rmidi->private_data;
2532
2533 chip->active_ctrl(chip, 1);
2534 spin_lock_irq(&chip->reg_lock);
2535 chip->uartm |= CS46XX_MODE_INPUT;
2536 chip->midcr |= MIDCR_RXE;
2537 chip->midi_input = substream;
2538 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2539 snd_cs46xx_midi_reset(chip);
2540 } else {
2541 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2542 }
2543 spin_unlock_irq(&chip->reg_lock);
2544 return 0;
2545 }
2546
2547 static int snd_cs46xx_midi_input_close(snd_rawmidi_substream_t * substream)
2548 {
2549 cs46xx_t *chip = substream->rmidi->private_data;
2550
2551 spin_lock_irq(&chip->reg_lock);
2552 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2553 chip->midi_input = NULL;
2554 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2555 snd_cs46xx_midi_reset(chip);
2556 } else {
2557 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2558 }
2559 chip->uartm &= ~CS46XX_MODE_INPUT;
2560 spin_unlock_irq(&chip->reg_lock);
2561 chip->active_ctrl(chip, -1);
2562 return 0;
2563 }
2564
2565 static int snd_cs46xx_midi_output_open(snd_rawmidi_substream_t * substream)
2566 {
2567 cs46xx_t *chip = substream->rmidi->private_data;
2568
2569 chip->active_ctrl(chip, 1);
2570
2571 spin_lock_irq(&chip->reg_lock);
2572 chip->uartm |= CS46XX_MODE_OUTPUT;
2573 chip->midcr |= MIDCR_TXE;
2574 chip->midi_output = substream;
2575 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2576 snd_cs46xx_midi_reset(chip);
2577 } else {
2578 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2579 }
2580 spin_unlock_irq(&chip->reg_lock);
2581 return 0;
2582 }
2583
2584 static int snd_cs46xx_midi_output_close(snd_rawmidi_substream_t * substream)
2585 {
2586 cs46xx_t *chip = substream->rmidi->private_data;
2587
2588 spin_lock_irq(&chip->reg_lock);
2589 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2590 chip->midi_output = NULL;
2591 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2592 snd_cs46xx_midi_reset(chip);
2593 } else {
2594 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2595 }
2596 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2597 spin_unlock_irq(&chip->reg_lock);
2598 chip->active_ctrl(chip, -1);
2599 return 0;
2600 }
2601
2602 static void snd_cs46xx_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2603 {
2604 unsigned long flags;
2605 cs46xx_t *chip = substream->rmidi->private_data;
2606
2607 spin_lock_irqsave(&chip->reg_lock, flags);
2608 if (up) {
2609 if ((chip->midcr & MIDCR_RIE) == 0) {
2610 chip->midcr |= MIDCR_RIE;
2611 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2612 }
2613 } else {
2614 if (chip->midcr & MIDCR_RIE) {
2615 chip->midcr &= ~MIDCR_RIE;
2616 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2617 }
2618 }
2619 spin_unlock_irqrestore(&chip->reg_lock, flags);
2620 }
2621
2622 static void snd_cs46xx_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2623 {
2624 unsigned long flags;
2625 cs46xx_t *chip = substream->rmidi->private_data;
2626 unsigned char byte;
2627
2628 spin_lock_irqsave(&chip->reg_lock, flags);
2629 if (up) {
2630 if ((chip->midcr & MIDCR_TIE) == 0) {
2631 chip->midcr |= MIDCR_TIE;
2632 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2633 while ((chip->midcr & MIDCR_TIE) &&
2634 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2635 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2636 chip->midcr &= ~MIDCR_TIE;
2637 } else {
2638 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2639 }
2640 }
2641 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2642 }
2643 } else {
2644 if (chip->midcr & MIDCR_TIE) {
2645 chip->midcr &= ~MIDCR_TIE;
2646 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2647 }
2648 }
2649 spin_unlock_irqrestore(&chip->reg_lock, flags);
2650 }
2651
2652 static snd_rawmidi_ops_t snd_cs46xx_midi_output =
2653 {
2654 .open = snd_cs46xx_midi_output_open,
2655 .close = snd_cs46xx_midi_output_close,
2656 .trigger = snd_cs46xx_midi_output_trigger,
2657 };
2658
2659 static snd_rawmidi_ops_t snd_cs46xx_midi_input =
2660 {
2661 .open = snd_cs46xx_midi_input_open,
2662 .close = snd_cs46xx_midi_input_close,
2663 .trigger = snd_cs46xx_midi_input_trigger,
2664 };
2665
2666 int __devinit snd_cs46xx_midi(cs46xx_t *chip, int device, snd_rawmidi_t **rrawmidi)
2667 {
2668 snd_rawmidi_t *rmidi;
2669 int err;
2670
2671 if (rrawmidi)
2672 *rrawmidi = NULL;
2673 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2674 return err;
2675 strcpy(rmidi->name, "CS46XX");
2676 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2677 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2678 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2679 rmidi->private_data = chip;
2680 chip->rmidi = rmidi;
2681 if (rrawmidi)
2682 *rrawmidi = NULL;
2683 return 0;
2684 }
2685
2686
2687 /*
2688 * gameport interface
2689 */
2690
2691 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2692
2693 typedef struct snd_cs46xx_gameport {
2694 struct gameport info;
2695 cs46xx_t *chip;
2696 } cs46xx_gameport_t;
2697
2698 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2699 {
2700 cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2701 cs46xx_t *chip;
2702 snd_assert(gp, return);
2703 chip = gp->chip;
2704 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2705 }
2706
2707 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2708 {
2709 cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2710 cs46xx_t *chip;
2711 snd_assert(gp, return 0);
2712 chip = gp->chip;
2713 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2714 }
2715
2716 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2717 {
2718 cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2719 cs46xx_t *chip;
2720 unsigned js1, js2, jst;
2721
2722 snd_assert(gp, return 0);
2723 chip = gp->chip;
2724
2725 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2726 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2727 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2728
2729 *buttons = (~jst >> 4) & 0x0F;
2730
2731 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2732 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2733 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2734 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2735
2736 for(jst=0;jst<4;++jst)
2737 if(axes[jst]==0xFFFF) axes[jst] = -1;
2738 return 0;
2739 }
2740
2741 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2742 {
2743 switch (mode) {
2744 case GAMEPORT_MODE_COOKED:
2745 return 0;
2746 case GAMEPORT_MODE_RAW:
2747 return 0;
2748 default:
2749 return -1;
2750 }
2751 return 0;
2752 }
2753
2754 void __devinit snd_cs46xx_gameport(cs46xx_t *chip)
2755 {
2756 cs46xx_gameport_t *gp;
2757 gp = kmalloc(sizeof(*gp), GFP_KERNEL);
2758 if (! gp) {
2759 snd_printk("cannot allocate gameport area\n");
2760 return;
2761 }
2762 memset(gp, 0, sizeof(*gp));
2763 gp->info.open = snd_cs46xx_gameport_open;
2764 gp->info.read = snd_cs46xx_gameport_read;
2765 gp->info.trigger = snd_cs46xx_gameport_trigger;
2766 gp->info.cooked_read = snd_cs46xx_gameport_cooked_read;
2767 gp->chip = chip;
2768 chip->gameport = gp;
2769
2770 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2771 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2772 gameport_register_port(&gp->info);
2773 }
2774
2775 #else
2776
2777 void __devinit snd_cs46xx_gameport(cs46xx_t *chip)
2778 {
2779 }
2780
2781 #endif /* CONFIG_GAMEPORT */
2782
2783 /*
2784 * proc interface
2785 */
2786
2787 static long snd_cs46xx_io_read(snd_info_entry_t *entry, void *file_private_data,
2788 struct file *file, char __user *buf,
2789 unsigned long count, unsigned long pos)
2790 {
2791 long size;
2792 snd_cs46xx_region_t *region = (snd_cs46xx_region_t *)entry->private_data;
2793
2794 size = count;
2795 if (pos + (size_t)size > region->size)
2796 size = region->size - pos;
2797 if (size > 0) {
2798 if (copy_to_user_fromio(buf, region->remap_addr + pos, size))
2799 return -EFAULT;
2800 }
2801 return size;
2802 }
2803
2804 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2805 .read = snd_cs46xx_io_read,
2806 };
2807
2808 static int __devinit snd_cs46xx_proc_init(snd_card_t * card, cs46xx_t *chip)
2809 {
2810 snd_info_entry_t *entry;
2811 int idx;
2812
2813 for (idx = 0; idx < 5; idx++) {
2814 snd_cs46xx_region_t *region = &chip->region.idx[idx];
2815 if (! snd_card_proc_new(card, region->name, &entry)) {
2816 entry->content = SNDRV_INFO_CONTENT_DATA;
2817 entry->private_data = chip;
2818 entry->c.ops = &snd_cs46xx_proc_io_ops;
2819 entry->size = region->size;
2820 entry->mode = S_IFREG | S_IRUSR;
2821 }
2822 }
2823 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2824 cs46xx_dsp_proc_init(card, chip);
2825 #endif
2826 return 0;
2827 }
2828
2829 static int snd_cs46xx_proc_done(cs46xx_t *chip)
2830 {
2831 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2832 cs46xx_dsp_proc_done(chip);
2833 #endif
2834 return 0;
2835 }
2836
2837 /*
2838 * stop the h/w
2839 */
2840 static void snd_cs46xx_hw_stop(cs46xx_t *chip)
2841 {
2842 unsigned int tmp;
2843
2844 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2845 tmp &= ~0x0000f03f;
2846 tmp |= 0x00000010;
2847 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2848
2849 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2850 tmp &= ~0x0000003f;
2851 tmp |= 0x00000011;
2852 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2853
2854 /*
2855 * Stop playback DMA.
2856 */
2857 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2858 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2859
2860 /*
2861 * Stop capture DMA.
2862 */
2863 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2864 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2865
2866 /*
2867 * Reset the processor.
2868 */
2869 snd_cs46xx_reset(chip);
2870
2871 snd_cs46xx_proc_stop(chip);
2872
2873 /*
2874 * Power down the PLL.
2875 */
2876 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2877
2878 /*
2879 * Turn off the Processor by turning off the software clock enable flag in
2880 * the clock control register.
2881 */
2882 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2883 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2884 }
2885
2886
2887 static int snd_cs46xx_free(cs46xx_t *chip)
2888 {
2889 int idx;
2890
2891 snd_assert(chip != NULL, return -EINVAL);
2892
2893 if (chip->active_ctrl)
2894 chip->active_ctrl(chip, 1);
2895
2896 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2897 if (chip->gameport) {
2898 gameport_unregister_port(&chip->gameport->info);
2899 kfree(chip->gameport);
2900 }
2901 #endif
2902
2903 if (chip->amplifier_ctrl)
2904 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2905
2906 snd_cs46xx_proc_done(chip);
2907
2908 if (chip->region.idx[0].resource)
2909 snd_cs46xx_hw_stop(chip);
2910
2911 for (idx = 0; idx < 5; idx++) {
2912 snd_cs46xx_region_t *region = &chip->region.idx[idx];
2913 if (region->remap_addr)
2914 iounmap(region->remap_addr);
2915 if (region->resource) {
2916 release_resource(region->resource);
2917 kfree_nocheck(region->resource);
2918 }
2919 }
2920 if (chip->irq >= 0)
2921 free_irq(chip->irq, (void *)chip);
2922
2923 if (chip->active_ctrl)
2924 chip->active_ctrl(chip, -chip->amplifier);
2925
2926 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2927 if (chip->dsp_spos_instance) {
2928 cs46xx_dsp_spos_destroy(chip);
2929 chip->dsp_spos_instance = NULL;
2930 }
2931 #endif
2932
2933 pci_disable_device(chip->pci);
2934 kfree(chip);
2935 return 0;
2936 }
2937
2938 static int snd_cs46xx_dev_free(snd_device_t *device)
2939 {
2940 cs46xx_t *chip = device->device_data;
2941 return snd_cs46xx_free(chip);
2942 }
2943
2944 /*
2945 * initialize chip
2946 */
2947 static int snd_cs46xx_chip_init(cs46xx_t *chip)
2948 {
2949 int timeout;
2950
2951 /*
2952 * First, blast the clock control register to zero so that the PLL starts
2953 * out in a known state, and blast the master serial port control register
2954 * to zero so that the serial ports also start out in a known state.
2955 */
2956 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2957 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2958
2959 /*
2960 * If we are in AC97 mode, then we must set the part to a host controlled
2961 * AC-link. Otherwise, we won't be able to bring up the link.
2962 */
2963 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2964 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2965 SERACC_TWO_CODECS); /* 2.00 dual codecs */
2966 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2967 #else
2968 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2969 #endif
2970
2971 /*
2972 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2973 * spec) and then drive it high. This is done for non AC97 modes since
2974 * there might be logic external to the CS461x that uses the ARST# line
2975 * for a reset.
2976 */
2977 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2978 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2979 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2980 #endif
2981 udelay(50);
2982 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2983 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2984 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2985 #endif
2986
2987 /*
2988 * The first thing we do here is to enable sync generation. As soon
2989 * as we start receiving bit clock, we'll start producing the SYNC
2990 * signal.
2991 */
2992 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2993 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2994 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2995 #endif
2996
2997 /*
2998 * Now wait for a short while to allow the AC97 part to start
2999 * generating bit clock (so we don't try to start the PLL without an
3000 * input clock).
3001 */
3002 mdelay(10);
3003
3004 /*
3005 * Set the serial port timing configuration, so that
3006 * the clock control circuit gets its clock from the correct place.
3007 */
3008 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3009
3010 /*
3011 * Write the selected clock control setup to the hardware. Do not turn on
3012 * SWCE yet (if requested), so that the devices clocked by the output of
3013 * PLL are not clocked until the PLL is stable.
3014 */
3015 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3016 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3017 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3018
3019 /*
3020 * Power up the PLL.
3021 */
3022 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3023
3024 /*
3025 * Wait until the PLL has stabilized.
3026 */
3027 set_current_state(TASK_UNINTERRUPTIBLE);
3028 schedule_timeout(HZ/10); /* 100ms */
3029
3030 /*
3031 * Turn on clocking of the core so that we can setup the serial ports.
3032 */
3033 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3034
3035 /*
3036 * Enable FIFO Host Bypass
3037 */
3038 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3039
3040 /*
3041 * Fill the serial port FIFOs with silence.
3042 */
3043 snd_cs46xx_clear_serial_FIFOs(chip);
3044
3045 /*
3046 * Set the serial port FIFO pointer to the first sample in the FIFO.
3047 */
3048 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3049
3050 /*
3051 * Write the serial port configuration to the part. The master
3052 * enable bit is not set until all other values have been written.
3053 */
3054 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3055 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3056 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3057
3058
3059 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3060 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3061 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3062 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3063 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3064 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3065 #endif
3066
3067 mdelay(5);
3068
3069
3070 /*
3071 * Wait for the codec ready signal from the AC97 codec.
3072 */
3073 timeout = 150;
3074 while (timeout-- > 0) {
3075 /*
3076 * Read the AC97 status register to see if we've seen a CODEC READY
3077 * signal from the AC97 codec.
3078 */
3079 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3080 goto ok1;
3081 set_current_state(TASK_UNINTERRUPTIBLE);
3082 schedule_timeout((HZ+99)/100);
3083 }
3084
3085
3086 snd_printk("create - never read codec ready from AC'97\n");
3087 snd_printk("it is not probably bug, try to use CS4236 driver\n");
3088 return -EIO;
3089 ok1:
3090 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3091 {
3092 int count;
3093 for (count = 0; count < 150; count++) {
3094 /* First, we want to wait for a short time. */
3095 udelay(25);
3096
3097 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3098 break;
3099 }
3100
3101 /*
3102 * Make sure CODEC is READY.
3103 */
3104 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3105 snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
3106 }
3107 #endif
3108
3109 /*
3110 * Assert the vaid frame signal so that we can start sending commands
3111 * to the AC97 codec.
3112 */
3113 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3114 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3115 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3116 #endif
3117
3118
3119 /*
3120 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3121 * the codec is pumping ADC data across the AC-link.
3122 */
3123 timeout = 150;
3124 while (timeout-- > 0) {
3125 /*
3126 * Read the input slot valid register and see if input slots 3 and
3127 * 4 are valid yet.
3128 */
3129 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3130 goto ok2;
3131 set_current_state(TASK_UNINTERRUPTIBLE);
3132 schedule_timeout((HZ+99)/100);
3133 }
3134
3135 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3136 snd_printk("create - never read ISV3 & ISV4 from AC'97\n");
3137 return -EIO;
3138 #else
3139 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3140 Reloading the driver may help, if there's other soundcards
3141 with the same problem I would like to know. (Benny) */
3142
3143 snd_printk("ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
3144 snd_printk(" Try reloading the ALSA driver, if you find something\n");
3145 snd_printk(" broken or not working on your soundcard upon\n");
3146 snd_printk(" this message please report to alsa-devel@lists.sourceforge.net\n");
3147
3148 return -EIO;
3149 #endif
3150 ok2:
3151
3152 /*
3153 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3154 * commense the transfer of digital audio data to the AC97 codec.
3155 */
3156
3157 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3158
3159
3160 /*
3161 * Power down the DAC and ADC. We will power them up (if) when we need
3162 * them.
3163 */
3164 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3165
3166 /*
3167 * Turn off the Processor by turning off the software clock enable flag in
3168 * the clock control register.
3169 */
3170 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3171 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3172
3173 return 0;
3174 }
3175
3176 /*
3177 * start and load DSP
3178 */
3179 int __devinit snd_cs46xx_start_dsp(cs46xx_t *chip)
3180 {
3181 unsigned int tmp;
3182 /*
3183 * Reset the processor.
3184 */
3185 snd_cs46xx_reset(chip);
3186 /*
3187 * Download the image to the processor.
3188 */
3189 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3190 #if 0
3191 if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) {
3192 snd_printk(KERN_ERR "image download error\n");
3193 return -EIO;
3194 }
3195 #endif
3196
3197 if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) {
3198 snd_printk(KERN_ERR "image download error [cwc4630]\n");
3199 return -EIO;
3200 }
3201
3202 if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) {
3203 snd_printk(KERN_ERR "image download error [cwcasync]\n");
3204 return -EIO;
3205 }
3206
3207 if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) {
3208 snd_printk(KERN_ERR "image download error [cwcsnoop]\n");
3209 return -EIO;
3210 }
3211
3212 if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) {
3213 snd_printk(KERN_ERR "image download error [cwcbinhack]\n");
3214 return -EIO;
3215 }
3216
3217 if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) {
3218 snd_printk(KERN_ERR "image download error [cwcdma]\n");
3219 return -EIO;
3220 }
3221
3222 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3223 return -EIO;
3224 #else
3225 /* old image */
3226 if (snd_cs46xx_download_image(chip) < 0) {
3227 snd_printk("image download error\n");
3228 return -EIO;
3229 }
3230
3231 /*
3232 * Stop playback DMA.
3233 */
3234 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3235 chip->play_ctl = tmp & 0xffff0000;
3236 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3237 #endif
3238
3239 /*
3240 * Stop capture DMA.
3241 */
3242 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3243 chip->capt.ctl = tmp & 0x0000ffff;
3244 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3245
3246 mdelay(5);
3247
3248 snd_cs46xx_set_play_sample_rate(chip, 8000);
3249 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3250
3251 snd_cs46xx_proc_start(chip);
3252
3253 /*
3254 * Enable interrupts on the part.
3255 */
3256 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3257
3258 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3259 tmp &= ~0x0000f03f;
3260 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3261
3262 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3263 tmp &= ~0x0000003f;
3264 tmp |= 0x00000001;
3265 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3266
3267 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3268 /* set the attenuation to 0dB */
3269 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3270 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3271 #endif
3272
3273 return 0;
3274 }
3275
3276
3277 /*
3278 * AMP control - null AMP
3279 */
3280
3281 static void amp_none(cs46xx_t *chip, int change)
3282 {
3283 }
3284
3285 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3286 static int voyetra_setup_eapd_slot(cs46xx_t *chip)
3287 {
3288
3289 u32 idx, valid_slots,tmp,powerdown = 0;
3290 u16 modem_power,pin_config,logic_type;
3291
3292 snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
3293
3294 /*
3295 * See if the devices are powered down. If so, we must power them up first
3296 * or they will not respond.
3297 */
3298 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3299
3300 if (!(tmp & CLKCR1_SWCE)) {
3301 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3302 powerdown = 1;
3303 }
3304
3305 /*
3306 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3307 * stuff.
3308 */
3309 if(chip->nr_ac97_codecs != 2) {
3310 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3311 return -EINVAL;
3312 }
3313
3314 modem_power = snd_cs46xx_codec_read (chip,
3315 AC97_EXTENDED_MSTATUS,
3316 CS46XX_SECONDARY_CODEC_INDEX);
3317 modem_power &=0xFEFF;
3318
3319 snd_cs46xx_codec_write(chip,
3320 AC97_EXTENDED_MSTATUS, modem_power,
3321 CS46XX_SECONDARY_CODEC_INDEX);
3322
3323 /*
3324 * Set GPIO pin's 7 and 8 so that they are configured for output.
3325 */
3326 pin_config = snd_cs46xx_codec_read (chip,
3327 AC97_GPIO_CFG,
3328 CS46XX_SECONDARY_CODEC_INDEX);
3329 pin_config &=0x27F;
3330
3331 snd_cs46xx_codec_write(chip,
3332 AC97_GPIO_CFG, pin_config,
3333 CS46XX_SECONDARY_CODEC_INDEX);
3334
3335 /*
3336 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3337 */
3338
3339 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3340 CS46XX_SECONDARY_CODEC_INDEX);
3341 logic_type &=0x27F;
3342
3343 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3344 CS46XX_SECONDARY_CODEC_INDEX);
3345
3346 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3347 valid_slots |= 0x200;
3348 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3349
3350 if ( cs46xx_wait_for_fifo(chip,1) ) {
3351 snd_printdd("FIFO is busy\n");
3352
3353 return -EINVAL;
3354 }
3355
3356 /*
3357 * Fill slots 12 with the correct value for the GPIO pins.
3358 */
3359 for(idx = 0x90; idx <= 0x9F; idx++) {
3360 /*
3361 * Initialize the fifo so that bits 7 and 8 are on.
3362 *
3363 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3364 * the left. 0x1800 corresponds to bits 7 and 8.
3365 */
3366 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3367
3368 /*
3369 * Wait for command to complete
3370 */
3371 if ( cs46xx_wait_for_fifo(chip,200) ) {
3372 snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx);
3373
3374 return -EINVAL;
3375 }
3376
3377 /*
3378 * Write the serial port FIFO index.
3379 */
3380 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3381
3382 /*
3383 * Tell the serial port to load the new value into the FIFO location.
3384 */
3385 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3386 }
3387
3388 /* wait for last command to complete */
3389 cs46xx_wait_for_fifo(chip,200);
3390
3391 /*
3392 * Now, if we powered up the devices, then power them back down again.
3393 * This is kinda ugly, but should never happen.
3394 */
3395 if (powerdown)
3396 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3397
3398 return 0;
3399 }
3400 #endif
3401
3402 /*
3403 * Crystal EAPD mode
3404 */
3405
3406 static void amp_voyetra(cs46xx_t *chip, int change)
3407 {
3408 /* Manage the EAPD bit on the Crystal 4297
3409 and the Analog AD1885 */
3410
3411 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3412 int old = chip->amplifier;
3413 #endif
3414 int oval, val;
3415
3416 chip->amplifier += change;
3417 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3418 CS46XX_PRIMARY_CODEC_INDEX);
3419 val = oval;
3420 if (chip->amplifier) {
3421 /* Turn the EAPD amp on */
3422 val |= 0x8000;
3423 } else {
3424 /* Turn the EAPD amp off */
3425 val &= ~0x8000;
3426 }
3427 if (val != oval) {
3428 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3429 CS46XX_PRIMARY_CODEC_INDEX);
3430 if (chip->eapd_switch)
3431 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3432 &chip->eapd_switch->id);
3433 }
3434
3435 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3436 if (chip->amplifier && !old) {
3437 voyetra_setup_eapd_slot(chip);
3438 }
3439 #endif
3440 }
3441
3442 static void hercules_init(cs46xx_t *chip)
3443 {
3444 /* default: AMP off, and SPDIF input optical */
3445 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3446 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3447 }
3448
3449
3450 /*
3451 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3452 */
3453 static void amp_hercules(cs46xx_t *chip, int change)
3454 {
3455 int old = chip->amplifier;
3456 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3457 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3458
3459 chip->amplifier += change;
3460 if (chip->amplifier && !old) {
3461 snd_printdd ("Hercules amplifier ON\n");
3462
3463 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3464 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3465 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3466 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3467 } else if (old && !chip->amplifier) {
3468 snd_printdd ("Hercules amplifier OFF\n");
3469 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3470 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3471 }
3472 }
3473
3474 static void voyetra_mixer_init (cs46xx_t *chip)
3475 {
3476 snd_printdd ("initializing Voyetra mixer\n");
3477
3478 /* Enable SPDIF out */
3479 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3480 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3481 }
3482
3483 static void hercules_mixer_init (cs46xx_t *chip)
3484 {
3485 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3486 unsigned int idx;
3487 int err;
3488 snd_card_t *card = chip->card;
3489 #endif
3490
3491 /* set EGPIO to default */
3492 hercules_init(chip);
3493
3494 snd_printdd ("initializing Hercules mixer\n");
3495
3496 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3497 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3498 snd_kcontrol_t *kctl;
3499
3500 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3501 if ((err = snd_ctl_add(card, kctl)) < 0) {
3502 printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err);
3503 break;
3504 }
3505 }
3506 #endif
3507 }
3508
3509
3510 #if 0
3511 /*
3512 * Untested
3513 */
3514
3515 static void amp_voyetra_4294(cs46xx_t *chip, int change)
3516 {
3517 chip->amplifier += change;
3518
3519 if (chip->amplifier) {
3520 /* Switch the GPIO pins 7 and 8 to open drain */
3521 snd_cs46xx_codec_write(chip, 0x4C,
3522 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3523 snd_cs46xx_codec_write(chip, 0x4E,
3524 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3525 /* Now wake the AMP (this might be backwards) */
3526 snd_cs46xx_codec_write(chip, 0x54,
3527 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3528 } else {
3529 snd_cs46xx_codec_write(chip, 0x54,
3530 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3531 }
3532 }
3533 #endif
3534
3535
3536 /*
3537 * piix4 pci ids
3538 */
3539 #ifndef PCI_VENDOR_ID_INTEL
3540 #define PCI_VENDOR_ID_INTEL 0x8086
3541 #endif /* PCI_VENDOR_ID_INTEL */
3542
3543 #ifndef PCI_DEVICE_ID_INTEL_82371AB_3
3544 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
3545 #endif /* PCI_DEVICE_ID_INTEL_82371AB_3 */
3546
3547 /*
3548 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3549 * whenever we need to beat on the chip.
3550 *
3551 * The original idea and code for this hack comes from David Kaiser at
3552 * Linuxcare. Perhaps one day Crystal will document their chips well
3553 * enough to make them useful.
3554 */
3555
3556 static void clkrun_hack(cs46xx_t *chip, int change)
3557 {
3558 u16 control, nval;
3559
3560 if (chip->acpi_dev == NULL)
3561 return;
3562
3563 chip->amplifier += change;
3564
3565 /* Read ACPI port */
3566 nval = control = inw(chip->acpi_port + 0x10);
3567
3568 /* Flip CLKRUN off while running */
3569 if (! chip->amplifier)
3570 nval |= 0x2000;
3571 else
3572 nval &= ~0x2000;
3573 if (nval != control)
3574 outw(nval, chip->acpi_port + 0x10);
3575 }
3576
3577
3578 /*
3579 * detect intel piix4
3580 */
3581 static void clkrun_init(cs46xx_t *chip)
3582 {
3583 u8 pp;
3584
3585 chip->acpi_dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3586 if (chip->acpi_dev == NULL)
3587 return; /* Not a thinkpad thats for sure */
3588
3589 /* Find the control port */
3590 pci_read_config_byte(chip->acpi_dev, 0x41, &pp);
3591 chip->acpi_port = pp << 8;
3592 }
3593
3594
3595 /*
3596 * Card subid table
3597 */
3598
3599 struct cs_card_type
3600 {
3601 u16 vendor;
3602 u16 id;
3603 char *name;
3604 void (*init)(cs46xx_t *);
3605 void (*amp)(cs46xx_t *, int);
3606 void (*active)(cs46xx_t *, int);
3607 void (*mixer_init)(cs46xx_t *);
3608 };
3609
3610 static struct cs_card_type __devinitdata cards[] = {
3611 {
3612 .vendor = 0x1489,
3613 .id = 0x7001,
3614 .name = "Genius Soundmaker 128 value",
3615 /* nothing special */
3616 },
3617 {
3618 .vendor = 0x5053,
3619 .id = 0x3357,
3620 .name = "Voyetra",
3621 .amp = amp_voyetra,
3622 .mixer_init = voyetra_mixer_init,
3623 },
3624 {
3625 .vendor = 0x1071,
3626 .id = 0x6003,
3627 .name = "Mitac MI6020/21",
3628 .amp = amp_voyetra,
3629 },
3630 {
3631 .vendor = 0x14AF,
3632 .id = 0x0050,
3633 .name = "Hercules Game Theatre XP",
3634 .amp = amp_hercules,
3635 .mixer_init = hercules_mixer_init,
3636 },
3637 {
3638 .vendor = 0x1681,
3639 .id = 0x0050,
3640 .name = "Hercules Game Theatre XP",
3641 .amp = amp_hercules,
3642 .mixer_init = hercules_mixer_init,
3643 },
3644 {
3645 .vendor = 0x1681,
3646 .id = 0x0051,
3647 .name = "Hercules Game Theatre XP",
3648 .amp = amp_hercules,
3649 .mixer_init = hercules_mixer_init,
3650
3651 },
3652 {
3653 .vendor = 0x1681,
3654 .id = 0x0052,
3655 .name = "Hercules Game Theatre XP",
3656 .amp = amp_hercules,
3657 .mixer_init = hercules_mixer_init,
3658 },
3659 {
3660 .vendor = 0x1681,
3661 .id = 0x0053,
3662 .name = "Hercules Game Theatre XP",
3663 .amp = amp_hercules,
3664 .mixer_init = hercules_mixer_init,
3665 },
3666 {
3667 .vendor = 0x1681,
3668 .id = 0x0054,
3669 .name = "Hercules Game Theatre XP",
3670 .amp = amp_hercules,
3671 .mixer_init = hercules_mixer_init,
3672 },
3673 /* Teratec */
3674 {
3675 .vendor = 0x153b,
3676 .id = 0x1136,
3677 .name = "Terratec SiXPack 5.1",
3678 },
3679 /* Not sure if the 570 needs the clkrun hack */
3680 {
3681 .vendor = PCI_VENDOR_ID_IBM,
3682 .id = 0x0132,
3683 .name = "Thinkpad 570",
3684 .init = clkrun_init,
3685 .active = clkrun_hack,
3686 },
3687 {
3688 .vendor = PCI_VENDOR_ID_IBM,
3689 .id = 0x0153,
3690 .name = "Thinkpad 600X/A20/T20",
3691 .init = clkrun_init,
3692 .active = clkrun_hack,
3693 },
3694 {
3695 .vendor = PCI_VENDOR_ID_IBM,
3696 .id = 0x1010,
3697 .name = "Thinkpad 600E (unsupported)",
3698 },
3699 {} /* terminator */
3700 };
3701
3702
3703 /*
3704 * APM support
3705 */
3706 #ifdef CONFIG_PM
3707 static int snd_cs46xx_suspend(snd_card_t *card, unsigned int state)
3708 {
3709 cs46xx_t *chip = card->pm_private_data;
3710 int amp_saved;
3711
3712 snd_pcm_suspend_all(chip->pcm);
3713 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3714 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3715
3716 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3717 if (chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])
3718 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3719
3720 amp_saved = chip->amplifier;
3721 /* turn off amp */
3722 chip->amplifier_ctrl(chip, -chip->amplifier);
3723 snd_cs46xx_hw_stop(chip);
3724 /* disable CLKRUN */
3725 chip->active_ctrl(chip, -chip->amplifier);
3726 chip->amplifier = amp_saved; /* restore the status */
3727 pci_disable_device(chip->pci);
3728 return 0;
3729 }
3730
3731 static int snd_cs46xx_resume(snd_card_t *card, unsigned int state)
3732 {
3733 cs46xx_t *chip = card->pm_private_data;
3734 int amp_saved;
3735
3736 pci_enable_device(chip->pci);
3737 pci_set_master(chip->pci);
3738 amp_saved = chip->amplifier;
3739 chip->amplifier = 0;
3740 chip->active_ctrl(chip, 1); /* force to on */
3741
3742 snd_cs46xx_chip_init(chip);
3743
3744 #if 0
3745 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3746 chip->ac97_general_purpose);
3747 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3748 chip->ac97_powerdown);
3749 mdelay(10);
3750 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3751 chip->ac97_powerdown);
3752 mdelay(5);
3753 #endif
3754
3755 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3756 if (chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])
3757 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3758
3759 if (amp_saved)
3760 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3761 else
3762 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3763 chip->amplifier = amp_saved;
3764 return 0;
3765 }
3766 #endif /* CONFIG_PM */
3767
3768
3769 /*
3770 */
3771
3772 int __devinit snd_cs46xx_create(snd_card_t * card,
3773 struct pci_dev * pci,
3774 int external_amp, int thinkpad,
3775 cs46xx_t ** rchip)
3776 {
3777 cs46xx_t *chip;
3778 int err, idx;
3779 snd_cs46xx_region_t *region;
3780 struct cs_card_type *cp;
3781 u16 ss_card, ss_vendor;
3782 static snd_device_ops_t ops = {
3783 .dev_free = snd_cs46xx_dev_free,
3784 };
3785
3786 *rchip = NULL;
3787
3788 /* enable PCI device */
3789 if ((err = pci_enable_device(pci)) < 0)
3790 return err;
3791
3792 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
3793 if (chip == NULL) {
3794 pci_disable_device(pci);
3795 return -ENOMEM;
3796 }
3797 spin_lock_init(&chip->reg_lock);
3798 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3799 init_MUTEX(&chip->spos_mutex);
3800 #endif
3801 chip->card = card;
3802 chip->pci = pci;
3803 chip->irq = -1;
3804 chip->ba0_addr = pci_resource_start(pci, 0);
3805 chip->ba1_addr = pci_resource_start(pci, 1);
3806 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3807 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3808 snd_printk("wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", chip->ba0_addr, chip->ba1_addr);
3809 snd_cs46xx_free(chip);
3810 return -ENOMEM;
3811 }
3812
3813 region = &chip->region.name.ba0;
3814 strcpy(region->name, "CS46xx_BA0");
3815 region->base = chip->ba0_addr;
3816 region->size = CS46XX_BA0_SIZE;
3817
3818 region = &chip->region.name.data0;
3819 strcpy(region->name, "CS46xx_BA1_data0");
3820 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3821 region->size = CS46XX_BA1_DATA0_SIZE;
3822
3823 region = &chip->region.name.data1;
3824 strcpy(region->name, "CS46xx_BA1_data1");
3825 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3826 region->size = CS46XX_BA1_DATA1_SIZE;
3827
3828 region = &chip->region.name.pmem;
3829 strcpy(region->name, "CS46xx_BA1_pmem");
3830 region->base = chip->ba1_addr + BA1_SP_PMEM;
3831 region->size = CS46XX_BA1_PRG_SIZE;
3832
3833 region = &chip->region.name.reg;
3834 strcpy(region->name, "CS46xx_BA1_reg");
3835 region->base = chip->ba1_addr + BA1_SP_REG;
3836 region->size = CS46XX_BA1_REG_SIZE;
3837
3838 /* set up amp and clkrun hack */
3839 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3840 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3841
3842 for (cp = &cards[0]; cp->name; cp++) {
3843 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3844 snd_printdd ("hack for %s enabled\n", cp->name);
3845
3846 chip->amplifier_ctrl = cp->amp;
3847 chip->active_ctrl = cp->active;
3848 chip->mixer_init = cp->mixer_init;
3849
3850 if (cp->init)
3851 cp->init(chip);
3852 break;
3853 }
3854 }
3855
3856 if (external_amp) {
3857 snd_printk("Crystal EAPD support forced on.\n");
3858 chip->amplifier_ctrl = amp_voyetra;
3859 }
3860
3861 if (thinkpad) {
3862 snd_printk("Activating CLKRUN hack for Thinkpad.\n");
3863 chip->active_ctrl = clkrun_hack;
3864 clkrun_init(chip);
3865 }
3866
3867 if (chip->amplifier_ctrl == NULL)
3868 chip->amplifier_ctrl = amp_none;
3869 if (chip->active_ctrl == NULL)
3870 chip->active_ctrl = amp_none;
3871
3872 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3873
3874 pci_set_master(pci);
3875
3876 for (idx = 0; idx < 5; idx++) {
3877 region = &chip->region.idx[idx];
3878 if ((region->resource = request_mem_region(region->base, region->size, region->name)) == NULL) {
3879 snd_printk("unable to request memory region 0x%lx-0x%lx\n", region->base, region->base + region->size - 1);
3880 snd_cs46xx_free(chip);
3881 return -EBUSY;
3882 }
3883 region->remap_addr = ioremap_nocache(region->base, region->size);
3884 if (region->remap_addr == NULL) {
3885 snd_printk("%s ioremap problem\n", region->name);
3886 snd_cs46xx_free(chip);
3887 return -ENOMEM;
3888 }
3889 }
3890
3891 if (request_irq(pci->irq, snd_cs46xx_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS46XX", (void *) chip)) {
3892 snd_printk("unable to grab IRQ %d\n", pci->irq);
3893 snd_cs46xx_free(chip);
3894 return -EBUSY;
3895 }
3896 chip->irq = pci->irq;
3897
3898 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3899 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3900 if (chip->dsp_spos_instance == NULL) {
3901 snd_cs46xx_free(chip);
3902 return -ENOMEM;
3903 }
3904 #endif
3905
3906 err = snd_cs46xx_chip_init(chip);
3907 if (err < 0) {
3908 snd_cs46xx_free(chip);
3909 return err;
3910 }
3911
3912 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3913 snd_cs46xx_free(chip);
3914 return err;
3915 }
3916
3917 snd_cs46xx_proc_init(card, chip);
3918
3919 snd_card_set_pm_callback(card, snd_cs46xx_suspend, snd_cs46xx_resume, chip);
3920
3921 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3922
3923 snd_card_set_dev(card, &pci->dev);
3924
3925 *rchip = chip;
3926 return 0;
3927 }
3928
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