1 /*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
22
23 #include <sound/driver.h>
24 #include <asm/io.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <sound/core.h>
33 #include <sound/info.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/rawmidi.h>
37 #include <sound/mpu401.h>
38 #include <sound/opl3.h>
39 #include <sound/sb.h>
40 #include <sound/asoundef.h>
41 #include <sound/initval.h>
42
43 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
44 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
45 MODULE_LICENSE("GPL");
46 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
47 "{C-Media,CMI8738B},"
48 "{C-Media,CMI8338A},"
49 "{C-Media,CMI8338B}}");
50
51 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
52 #define SUPPORT_JOYSTICK 1
53 #endif
54
55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
58 static long mpu_port[SNDRV_CARDS];
59 static long fm_port[SNDRV_CARDS];
60 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61 #ifdef SUPPORT_JOYSTICK
62 static int joystick_port[SNDRV_CARDS];
63 #endif
64
65 module_param_array(index, int, NULL, 0444);
66 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
67 module_param_array(id, charp, NULL, 0444);
68 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
69 module_param_array(enable, bool, NULL, 0444);
70 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
71 module_param_array(mpu_port, long, NULL, 0444);
72 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
73 module_param_array(fm_port, long, NULL, 0444);
74 MODULE_PARM_DESC(fm_port, "FM port.");
75 module_param_array(soft_ac3, bool, NULL, 0444);
76 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
77 #ifdef SUPPORT_JOYSTICK
78 module_param_array(joystick_port, int, NULL, 0444);
79 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
80 #endif
81
82 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738
83 #define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
84 #endif
85 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
86 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
87 #endif
88
89 /*
90 * CM8x38 registers definition
91 */
92
93 #define CM_REG_FUNCTRL0 0x00
94 #define CM_RST_CH1 0x00080000
95 #define CM_RST_CH0 0x00040000
96 #define CM_CHEN1 0x00020000 /* ch1: enable */
97 #define CM_CHEN0 0x00010000 /* ch0: enable */
98 #define CM_PAUSE1 0x00000008 /* ch1: pause */
99 #define CM_PAUSE0 0x00000004 /* ch0: pause */
100 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
101 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
102
103 #define CM_REG_FUNCTRL1 0x04
104 #define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */
105 #define CM_ASFC_SHIFT 13
106 #define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */
107 #define CM_DSFC_SHIFT 10
108 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
109 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
110 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */
111 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
112 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
113 #define CM_BREQ 0x00000010 /* bus master enabled */
114 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
115 #define CM_UART_EN 0x00000004 /* UART */
116 #define CM_JYSTK_EN 0x00000002 /* joy stick */
117
118 #define CM_REG_CHFORMAT 0x08
119
120 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
121 #define CM_CHB3D 0x20000000 /* 4 channels */
122
123 #define CM_CHIP_MASK1 0x1f000000
124 #define CM_CHIP_037 0x01000000
125
126 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
127 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
128 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
129 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
130
131 #define CM_ADCBITLEN_MASK 0x0000C000
132 #define CM_ADCBITLEN_16 0x00000000
133 #define CM_ADCBITLEN_15 0x00004000
134 #define CM_ADCBITLEN_14 0x00008000
135 #define CM_ADCBITLEN_13 0x0000C000
136
137 #define CM_ADCDACLEN_MASK 0x00003000
138 #define CM_ADCDACLEN_060 0x00000000
139 #define CM_ADCDACLEN_066 0x00001000
140 #define CM_ADCDACLEN_130 0x00002000
141 #define CM_ADCDACLEN_280 0x00003000
142
143 #define CM_CH1_SRATE_176K 0x00000800
144 #define CM_CH1_SRATE_88K 0x00000400
145 #define CM_CH0_SRATE_176K 0x00000200
146 #define CM_CH0_SRATE_88K 0x00000100
147
148 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
149
150 #define CM_CH1FMT_MASK 0x0000000C
151 #define CM_CH1FMT_SHIFT 2
152 #define CM_CH0FMT_MASK 0x00000003
153 #define CM_CH0FMT_SHIFT 0
154
155 #define CM_REG_INT_HLDCLR 0x0C
156 #define CM_CHIP_MASK2 0xff000000
157 #define CM_CHIP_039 0x04000000
158 #define CM_CHIP_039_6CH 0x01000000
159 #define CM_TDMA_INT_EN 0x00040000
160 #define CM_CH1_INT_EN 0x00020000
161 #define CM_CH0_INT_EN 0x00010000
162 #define CM_INT_HOLD 0x00000002
163 #define CM_INT_CLEAR 0x00000001
164
165 #define CM_REG_INT_STATUS 0x10
166 #define CM_INTR 0x80000000
167 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
168 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
169 #define CM_UARTINT 0x00010000
170 #define CM_LTDMAINT 0x00008000
171 #define CM_HTDMAINT 0x00004000
172 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
173 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
174 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
175 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
176 #define CM_CH1BUSY 0x00000008
177 #define CM_CH0BUSY 0x00000004
178 #define CM_CHINT1 0x00000002
179 #define CM_CHINT0 0x00000001
180
181 #define CM_REG_LEGACY_CTRL 0x14
182 #define CM_NXCHG 0x80000000 /* h/w multi channels? */
183 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
184 #define CM_VMPU_330 0x00000000
185 #define CM_VMPU_320 0x20000000
186 #define CM_VMPU_310 0x40000000
187 #define CM_VMPU_300 0x60000000
188 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
189 #define CM_VSBSEL_220 0x00000000
190 #define CM_VSBSEL_240 0x04000000
191 #define CM_VSBSEL_260 0x08000000
192 #define CM_VSBSEL_280 0x0C000000
193 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
194 #define CM_FMSEL_388 0x00000000
195 #define CM_FMSEL_3C8 0x01000000
196 #define CM_FMSEL_3E0 0x02000000
197 #define CM_FMSEL_3E8 0x03000000
198 #define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */
199 #define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */
200 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
201 #define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
202 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
203 #define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */
204
205 #define CM_REG_MISC_CTRL 0x18
206 #define CM_PWD 0x80000000
207 #define CM_RESET 0x40000000
208 #define CM_SFIL_MASK 0x30000000
209 #define CM_TXVX 0x08000000
210 #define CM_N4SPK3D 0x04000000 /* 4ch output */
211 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
212 #define CM_SPDIF48K 0x01000000 /* write */
213 #define CM_SPATUS48K 0x01000000 /* read */
214 #define CM_ENDBDAC 0x00800000 /* enable dual dac */
215 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
216 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
217 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */
218 #define CM_FM_EN 0x00080000 /* enalbe FM */
219 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
220 #define CM_VIDWPDSB 0x00010000
221 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
222 #define CM_MASK_EN 0x00004000
223 #define CM_VIDWPPRT 0x00002000
224 #define CM_SFILENB 0x00001000
225 #define CM_MMODE_MASK 0x00000E00
226 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
227 #define CM_ENCENTER 0x00000080
228 #define CM_FLINKON 0x00000040
229 #define CM_FLINKOFF 0x00000020
230 #define CM_MIDSMP 0x00000010
231 #define CM_UPDDMA_MASK 0x0000000C
232 #define CM_TWAIT_MASK 0x00000003
233
234 /* byte */
235 #define CM_REG_MIXER0 0x20
236
237 #define CM_REG_SB16_DATA 0x22
238 #define CM_REG_SB16_ADDR 0x23
239
240 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
241 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
242 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
243 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
244
245 #define CM_REG_MIXER1 0x24
246 #define CM_FMMUTE 0x80 /* mute FM */
247 #define CM_FMMUTE_SHIFT 7
248 #define CM_WSMUTE 0x40 /* mute PCM */
249 #define CM_WSMUTE_SHIFT 6
250 #define CM_SPK4 0x20 /* lin-in -> rear line out */
251 #define CM_SPK4_SHIFT 5
252 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
253 #define CM_REAR2FRONT_SHIFT 4
254 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
255 #define CM_WAVEINL_SHIFT 3
256 #define CM_WAVEINR 0x04 /* digical wave rec. right */
257 #define CM_WAVEINR_SHIFT 2
258 #define CM_X3DEN 0x02 /* 3D surround enable */
259 #define CM_X3DEN_SHIFT 1
260 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
261 #define CM_CDPLAY_SHIFT 0
262
263 #define CM_REG_MIXER2 0x25
264 #define CM_RAUXREN 0x80 /* AUX right capture */
265 #define CM_RAUXREN_SHIFT 7
266 #define CM_RAUXLEN 0x40 /* AUX left capture */
267 #define CM_RAUXLEN_SHIFT 6
268 #define CM_VAUXRM 0x20 /* AUX right mute */
269 #define CM_VAUXRM_SHIFT 5
270 #define CM_VAUXLM 0x10 /* AUX left mute */
271 #define CM_VAUXLM_SHIFT 4
272 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
273 #define CM_VADMIC_SHIFT 1
274 #define CM_MICGAINZ 0x01 /* mic boost */
275 #define CM_MICGAINZ_SHIFT 0
276
277 #define CM_REG_AUX_VOL 0x26
278 #define CM_VAUXL_MASK 0xf0
279 #define CM_VAUXR_MASK 0x0f
280
281 #define CM_REG_MISC 0x27
282 #define CM_XGPO1 0x20
283 // #define CM_XGPBIO 0x04
284 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
285 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
286 #define CM_SPDVALID 0x02 /* spdif input valid check */
287 #define CM_DMAUTO 0x01
288
289 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
290 /*
291 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
292 * or identical with AC97 codec?
293 */
294 #define CM_REG_EXTERN_CODEC CM_REG_AC97
295
296 /*
297 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
298 */
299 #define CM_REG_MPU_PCI 0x40
300
301 /*
302 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
303 */
304 #define CM_REG_FM_PCI 0x50
305
306 /*
307 * for CMI-8338 .. this is not valid for CMI-8738.
308 */
309 #define CM_REG_EXTENT_IND 0xf0
310 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
311 #define CM_VPHONE_SHIFT 5
312 #define CM_VPHOM 0x10 /* Phone mute control */
313 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
314 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
315 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
316
317 /*
318 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
319 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
320 * unit (readonly?).
321 */
322 #define CM_REG_PLL 0xf8
323
324 /*
325 * extended registers
326 */
327 #define CM_REG_CH0_FRAME1 0x80 /* base address */
328 #define CM_REG_CH0_FRAME2 0x84
329 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
330 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
331
332 /*
333 * size of i/o region
334 */
335 #define CM_EXTENT_CODEC 0x100
336 #define CM_EXTENT_MIDI 0x2
337 #define CM_EXTENT_SYNTH 0x4
338
339
340 /*
341 * pci ids
342 */
343 #ifndef PCI_VENDOR_ID_CMEDIA
344 #define PCI_VENDOR_ID_CMEDIA 0x13F6
345 #endif
346 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338A
347 #define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100
348 #endif
349 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338B
350 #define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101
351 #endif
352 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738
353 #define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
354 #endif
355 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
356 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
357 #endif
358
359 /*
360 * channels for playback / capture
361 */
362 #define CM_CH_PLAY 0
363 #define CM_CH_CAPT 1
364
365 /*
366 * flags to check device open/close
367 */
368 #define CM_OPEN_NONE 0
369 #define CM_OPEN_CH_MASK 0x01
370 #define CM_OPEN_DAC 0x10
371 #define CM_OPEN_ADC 0x20
372 #define CM_OPEN_SPDIF 0x40
373 #define CM_OPEN_MCHAN 0x80
374 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
375 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
376 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
377 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
378 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
379 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
380
381
382 #if CM_CH_PLAY == 1
383 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
384 #define CM_PLAYBACK_SPDF CM_SPDF_1
385 #define CM_CAPTURE_SPDF CM_SPDF_0
386 #else
387 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
388 #define CM_PLAYBACK_SPDF CM_SPDF_0
389 #define CM_CAPTURE_SPDF CM_SPDF_1
390 #endif
391
392
393 /*
394 * driver data
395 */
396
397 typedef struct snd_stru_cmipci cmipci_t;
398 typedef struct snd_stru_cmipci_pcm cmipci_pcm_t;
399
400 struct snd_stru_cmipci_pcm {
401 snd_pcm_substream_t *substream;
402 int running; /* dac/adc running? */
403 unsigned int dma_size; /* in frames */
404 unsigned int period_size; /* in frames */
405 unsigned int offset; /* physical address of the buffer */
406 unsigned int fmt; /* format bits */
407 int ch; /* channel (0/1) */
408 unsigned int is_dac; /* is dac? */
409 int bytes_per_frame;
410 int shift;
411 };
412
413 /* mixer elements toggled/resumed during ac3 playback */
414 struct cmipci_mixer_auto_switches {
415 const char *name; /* switch to toggle */
416 int toggle_on; /* value to change when ac3 mode */
417 };
418 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
419 {"PCM Playback Switch", 0},
420 {"IEC958 Output Switch", 1},
421 {"IEC958 Mix Analog", 0},
422 // {"IEC958 Out To DAC", 1}, // no longer used
423 {"IEC958 Loop", 0},
424 };
425 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
426
427 struct snd_stru_cmipci {
428 snd_card_t *card;
429
430 struct pci_dev *pci;
431 unsigned int device; /* device ID */
432 int irq;
433
434 unsigned long iobase;
435 unsigned int ctrl; /* FUNCTRL0 current value */
436
437 snd_pcm_t *pcm; /* DAC/ADC PCM */
438 snd_pcm_t *pcm2; /* 2nd DAC */
439 snd_pcm_t *pcm_spdif; /* SPDIF */
440
441 int chip_version;
442 int max_channels;
443 unsigned int has_dual_dac: 1;
444 unsigned int can_ac3_sw: 1;
445 unsigned int can_ac3_hw: 1;
446 unsigned int can_multi_ch: 1;
447 unsigned int do_soft_ac3: 1;
448
449 unsigned int spdif_playback_avail: 1; /* spdif ready? */
450 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
451 int spdif_counter; /* for software AC3 */
452
453 unsigned int dig_status;
454 unsigned int dig_pcm_status;
455
456 snd_pcm_hardware_t *hw_info[3]; /* for playbacks */
457
458 int opened[2]; /* open mode */
459 struct semaphore open_mutex;
460
461 int mixer_insensitive: 1;
462 snd_kcontrol_t *mixer_res_ctl[CM_SAVED_MIXERS];
463 int mixer_res_status[CM_SAVED_MIXERS];
464
465 opl3_t *opl3;
466 snd_hwdep_t *opl3hwdep;
467
468 cmipci_pcm_t channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
469
470 /* external MIDI */
471 snd_rawmidi_t *rmidi;
472
473 #ifdef SUPPORT_JOYSTICK
474 struct gameport gameport;
475 struct resource *res_joystick;
476 #endif
477
478 spinlock_t reg_lock;
479 };
480
481
482 /* read/write operations for dword register */
483 inline static void snd_cmipci_write(cmipci_t *cm, unsigned int cmd, unsigned int data)
484 {
485 outl(data, cm->iobase + cmd);
486 }
487 inline static unsigned int snd_cmipci_read(cmipci_t *cm, unsigned int cmd)
488 {
489 return inl(cm->iobase + cmd);
490 }
491
492 /* read/write operations for word register */
493 inline static void snd_cmipci_write_w(cmipci_t *cm, unsigned int cmd, unsigned short data)
494 {
495 outw(data, cm->iobase + cmd);
496 }
497 inline static unsigned short snd_cmipci_read_w(cmipci_t *cm, unsigned int cmd)
498 {
499 return inw(cm->iobase + cmd);
500 }
501
502 /* read/write operations for byte register */
503 inline static void snd_cmipci_write_b(cmipci_t *cm, unsigned int cmd, unsigned char data)
504 {
505 outb(data, cm->iobase + cmd);
506 }
507
508 inline static unsigned char snd_cmipci_read_b(cmipci_t *cm, unsigned int cmd)
509 {
510 return inb(cm->iobase + cmd);
511 }
512
513 /* bit operations for dword register */
514 static void snd_cmipci_set_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
515 {
516 unsigned int val;
517 val = inl(cm->iobase + cmd);
518 val |= flag;
519 outl(val, cm->iobase + cmd);
520 }
521
522 static void snd_cmipci_clear_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
523 {
524 unsigned int val;
525 val = inl(cm->iobase + cmd);
526 val &= ~flag;
527 outl(val, cm->iobase + cmd);
528 }
529
530 #if 0 // not used
531 /* bit operations for byte register */
532 static void snd_cmipci_set_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
533 {
534 unsigned char val;
535 val = inb(cm->iobase + cmd);
536 val |= flag;
537 outb(val, cm->iobase + cmd);
538 }
539
540 static void snd_cmipci_clear_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
541 {
542 unsigned char val;
543 val = inb(cm->iobase + cmd);
544 val &= ~flag;
545 outb(val, cm->iobase + cmd);
546 }
547 #endif
548
549
550 /*
551 * PCM interface
552 */
553
554 /*
555 * calculate frequency
556 */
557
558 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
559
560 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
561 {
562 unsigned int i;
563 for (i = 0; i < ARRAY_SIZE(rates); i++) {
564 if (rates[i] == rate)
565 return i;
566 }
567 snd_BUG();
568 return 0;
569 }
570
571 #ifdef USE_VAR48KRATE
572 /*
573 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
574 * does it this way .. maybe not. Never get any information from C-Media about
575 * that <werner@suse.de>.
576 */
577 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
578 {
579 unsigned int delta, tolerance;
580 int xm, xn, xr;
581
582 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
583 rate <<= 1;
584 *n = -1;
585 if (*r > 0xff)
586 goto out;
587 tolerance = rate*CM_TOLERANCE_RATE;
588
589 for (xn = (1+2); xn < (0x1f+2); xn++) {
590 for (xm = (1+2); xm < (0xff+2); xm++) {
591 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
592
593 if (xr < rate)
594 delta = rate - xr;
595 else
596 delta = xr - rate;
597
598 /*
599 * If we found one, remember this,
600 * and try to find a closer one
601 */
602 if (delta < tolerance) {
603 tolerance = delta;
604 *m = xm - 2;
605 *n = xn - 2;
606 }
607 }
608 }
609 out:
610 return (*n > -1);
611 }
612
613 /*
614 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
615 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
616 * at the register CM_REG_FUNCTRL1 (0x04).
617 * Problem: other ways are also possible (any information about that?)
618 */
619 static void snd_cmipci_set_pll(cmipci_t *cm, unsigned int rate, unsigned int slot)
620 {
621 unsigned int reg = CM_REG_PLL + slot;
622 /*
623 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
624 * for DSFC/ASFC (000 upto 111).
625 */
626
627 /* FIXME: Init (Do we've to set an other register first before programming?) */
628
629 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
630 snd_cmipci_write_b(cm, reg, rate>>8);
631 snd_cmipci_write_b(cm, reg, rate&0xff);
632
633 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
634 }
635 #endif /* USE_VAR48KRATE */
636
637 static int snd_cmipci_hw_params(snd_pcm_substream_t * substream,
638 snd_pcm_hw_params_t * hw_params)
639 {
640 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
641 }
642
643 static int snd_cmipci_playback2_hw_params(snd_pcm_substream_t * substream,
644 snd_pcm_hw_params_t * hw_params)
645 {
646 cmipci_t *cm = snd_pcm_substream_chip(substream);
647 if (params_channels(hw_params) > 2) {
648 down(&cm->open_mutex);
649 if (cm->opened[CM_CH_PLAY]) {
650 up(&cm->open_mutex);
651 return -EBUSY;
652 }
653 /* reserve the channel A */
654 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
655 up(&cm->open_mutex);
656 }
657 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
658 }
659
660 static void snd_cmipci_ch_reset(cmipci_t *cm, int ch)
661 {
662 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
663 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
664 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
665 udelay(10);
666 }
667
668 static int snd_cmipci_hw_free(snd_pcm_substream_t * substream)
669 {
670 return snd_pcm_lib_free_pages(substream);
671 }
672
673
674 /*
675 */
676
677 static unsigned int hw_channels[] = {1, 2, 4, 5, 6};
678 static snd_pcm_hw_constraint_list_t hw_constraints_channels_4 = {
679 .count = 3,
680 .list = hw_channels,
681 .mask = 0,
682 };
683 static snd_pcm_hw_constraint_list_t hw_constraints_channels_6 = {
684 .count = 5,
685 .list = hw_channels,
686 .mask = 0,
687 };
688
689 static int set_dac_channels(cmipci_t *cm, cmipci_pcm_t *rec, int channels)
690 {
691 if (channels > 2) {
692 if (! cm->can_multi_ch)
693 return -EINVAL;
694 if (rec->fmt != 0x03) /* stereo 16bit only */
695 return -EINVAL;
696
697 spin_lock_irq(&cm->reg_lock);
698 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
699 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
700 if (channels > 4) {
701 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
702 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
703 } else {
704 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
705 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
706 }
707 if (channels == 6) {
708 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
709 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
710 } else {
711 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
712 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
713 }
714 spin_unlock_irq(&cm->reg_lock);
715
716 } else {
717 if (cm->can_multi_ch) {
718 spin_lock_irq(&cm->reg_lock);
719 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
720 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
721 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
722 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
723 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
724 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
725 spin_unlock_irq(&cm->reg_lock);
726 }
727 }
728 return 0;
729 }
730
731
732 /*
733 * prepare playback/capture channel
734 * channel to be used must have been set in rec->ch.
735 */
736 static int snd_cmipci_pcm_prepare(cmipci_t *cm, cmipci_pcm_t *rec,
737 snd_pcm_substream_t *substream)
738 {
739 unsigned int reg, freq, val;
740 snd_pcm_runtime_t *runtime = substream->runtime;
741
742 rec->fmt = 0;
743 rec->shift = 0;
744 if (snd_pcm_format_width(runtime->format) >= 16) {
745 rec->fmt |= 0x02;
746 if (snd_pcm_format_width(runtime->format) > 16)
747 rec->shift++; /* 24/32bit */
748 }
749 if (runtime->channels > 1)
750 rec->fmt |= 0x01;
751 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
752 snd_printd("cannot set dac channels\n");
753 return -EINVAL;
754 }
755
756 rec->offset = runtime->dma_addr;
757 /* buffer and period sizes in frame */
758 rec->dma_size = runtime->buffer_size << rec->shift;
759 rec->period_size = runtime->period_size << rec->shift;
760 if (runtime->channels > 2) {
761 /* multi-channels */
762 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
763 rec->period_size = (rec->period_size * runtime->channels) / 2;
764 }
765
766 spin_lock_irq(&cm->reg_lock);
767
768 /* set buffer address */
769 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
770 snd_cmipci_write(cm, reg, rec->offset);
771 /* program sample counts */
772 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
773 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
774 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
775
776 /* set adc/dac flag */
777 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
778 if (rec->is_dac)
779 cm->ctrl &= ~val;
780 else
781 cm->ctrl |= val;
782 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
783 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
784
785 /* set sample rate */
786 freq = snd_cmipci_rate_freq(runtime->rate);
787 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
788 if (rec->ch) {
789 val &= ~CM_ASFC_MASK;
790 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
791 } else {
792 val &= ~CM_DSFC_MASK;
793 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
794 }
795 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
796 //snd_printd("cmipci: functrl1 = %08x\n", val);
797
798 /* set format */
799 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
800 if (rec->ch) {
801 val &= ~CM_CH1FMT_MASK;
802 val |= rec->fmt << CM_CH1FMT_SHIFT;
803 } else {
804 val &= ~CM_CH0FMT_MASK;
805 val |= rec->fmt << CM_CH0FMT_SHIFT;
806 }
807 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
808 //snd_printd("cmipci: chformat = %08x\n", val);
809
810 rec->running = 0;
811 spin_unlock_irq(&cm->reg_lock);
812
813 return 0;
814 }
815
816 /*
817 * PCM trigger/stop
818 */
819 static int snd_cmipci_pcm_trigger(cmipci_t *cm, cmipci_pcm_t *rec,
820 snd_pcm_substream_t *substream, int cmd)
821 {
822 unsigned int inthld, chen, reset, pause;
823 int result = 0;
824
825 inthld = CM_CH0_INT_EN << rec->ch;
826 chen = CM_CHEN0 << rec->ch;
827 reset = CM_RST_CH0 << rec->ch;
828 pause = CM_PAUSE0 << rec->ch;
829
830 spin_lock(&cm->reg_lock);
831 switch (cmd) {
832 case SNDRV_PCM_TRIGGER_START:
833 rec->running = 1;
834 /* set interrupt */
835 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
836 cm->ctrl |= chen;
837 /* enable channel */
838 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
839 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
840 break;
841 case SNDRV_PCM_TRIGGER_STOP:
842 rec->running = 0;
843 /* disable interrupt */
844 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
845 /* reset */
846 cm->ctrl &= ~chen;
847 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
848 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
849 break;
850 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
851 cm->ctrl |= pause;
852 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
853 break;
854 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
855 cm->ctrl &= ~pause;
856 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
857 break;
858 default:
859 result = -EINVAL;
860 break;
861 }
862 spin_unlock(&cm->reg_lock);
863 return result;
864 }
865
866 /*
867 * return the current pointer
868 */
869 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(cmipci_t *cm, cmipci_pcm_t *rec,
870 snd_pcm_substream_t *substream)
871 {
872 size_t ptr;
873 unsigned int reg;
874 if (!rec->running)
875 return 0;
876 #if 1 // this seems better..
877 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
878 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
879 ptr >>= rec->shift;
880 #else
881 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
882 ptr = snd_cmipci_read(cm, reg) - rec->offset;
883 ptr = bytes_to_frames(substream->runtime, ptr);
884 #endif
885 if (substream->runtime->channels > 2)
886 ptr = (ptr * 2) / substream->runtime->channels;
887 return ptr;
888 }
889
890 /*
891 * playback
892 */
893
894 static int snd_cmipci_playback_trigger(snd_pcm_substream_t *substream,
895 int cmd)
896 {
897 cmipci_t *cm = snd_pcm_substream_chip(substream);
898 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
899 }
900
901 static snd_pcm_uframes_t snd_cmipci_playback_pointer(snd_pcm_substream_t *substream)
902 {
903 cmipci_t *cm = snd_pcm_substream_chip(substream);
904 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
905 }
906
907
908
909 /*
910 * capture
911 */
912
913 static int snd_cmipci_capture_trigger(snd_pcm_substream_t *substream,
914 int cmd)
915 {
916 cmipci_t *cm = snd_pcm_substream_chip(substream);
917 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
918 }
919
920 static snd_pcm_uframes_t snd_cmipci_capture_pointer(snd_pcm_substream_t *substream)
921 {
922 cmipci_t *cm = snd_pcm_substream_chip(substream);
923 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
924 }
925
926
927 /*
928 * hw preparation for spdif
929 */
930
931 static int snd_cmipci_spdif_default_info(snd_kcontrol_t *kcontrol,
932 snd_ctl_elem_info_t *uinfo)
933 {
934 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
935 uinfo->count = 1;
936 return 0;
937 }
938
939 static int snd_cmipci_spdif_default_get(snd_kcontrol_t *kcontrol,
940 snd_ctl_elem_value_t *ucontrol)
941 {
942 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
943 int i;
944
945 spin_lock_irq(&chip->reg_lock);
946 for (i = 0; i < 4; i++)
947 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
948 spin_unlock_irq(&chip->reg_lock);
949 return 0;
950 }
951
952 static int snd_cmipci_spdif_default_put(snd_kcontrol_t * kcontrol,
953 snd_ctl_elem_value_t * ucontrol)
954 {
955 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
956 int i, change;
957 unsigned int val;
958
959 val = 0;
960 spin_lock_irq(&chip->reg_lock);
961 for (i = 0; i < 4; i++)
962 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
963 change = val != chip->dig_status;
964 chip->dig_status = val;
965 spin_unlock_irq(&chip->reg_lock);
966 return change;
967 }
968
969 static snd_kcontrol_new_t snd_cmipci_spdif_default __devinitdata =
970 {
971 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
972 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
973 .info = snd_cmipci_spdif_default_info,
974 .get = snd_cmipci_spdif_default_get,
975 .put = snd_cmipci_spdif_default_put
976 };
977
978 static int snd_cmipci_spdif_mask_info(snd_kcontrol_t *kcontrol,
979 snd_ctl_elem_info_t *uinfo)
980 {
981 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
982 uinfo->count = 1;
983 return 0;
984 }
985
986 static int snd_cmipci_spdif_mask_get(snd_kcontrol_t * kcontrol,
987 snd_ctl_elem_value_t *ucontrol)
988 {
989 ucontrol->value.iec958.status[0] = 0xff;
990 ucontrol->value.iec958.status[1] = 0xff;
991 ucontrol->value.iec958.status[2] = 0xff;
992 ucontrol->value.iec958.status[3] = 0xff;
993 return 0;
994 }
995
996 static snd_kcontrol_new_t snd_cmipci_spdif_mask __devinitdata =
997 {
998 .access = SNDRV_CTL_ELEM_ACCESS_READ,
999 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1000 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1001 .info = snd_cmipci_spdif_mask_info,
1002 .get = snd_cmipci_spdif_mask_get,
1003 };
1004
1005 static int snd_cmipci_spdif_stream_info(snd_kcontrol_t *kcontrol,
1006 snd_ctl_elem_info_t *uinfo)
1007 {
1008 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1009 uinfo->count = 1;
1010 return 0;
1011 }
1012
1013 static int snd_cmipci_spdif_stream_get(snd_kcontrol_t *kcontrol,
1014 snd_ctl_elem_value_t *ucontrol)
1015 {
1016 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1017 int i;
1018
1019 spin_lock_irq(&chip->reg_lock);
1020 for (i = 0; i < 4; i++)
1021 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1022 spin_unlock_irq(&chip->reg_lock);
1023 return 0;
1024 }
1025
1026 static int snd_cmipci_spdif_stream_put(snd_kcontrol_t *kcontrol,
1027 snd_ctl_elem_value_t *ucontrol)
1028 {
1029 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1030 int i, change;
1031 unsigned int val;
1032
1033 val = 0;
1034 spin_lock_irq(&chip->reg_lock);
1035 for (i = 0; i < 4; i++)
1036 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1037 change = val != chip->dig_pcm_status;
1038 chip->dig_pcm_status = val;
1039 spin_unlock_irq(&chip->reg_lock);
1040 return change;
1041 }
1042
1043 static snd_kcontrol_new_t snd_cmipci_spdif_stream __devinitdata =
1044 {
1045 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1046 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1047 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1048 .info = snd_cmipci_spdif_stream_info,
1049 .get = snd_cmipci_spdif_stream_get,
1050 .put = snd_cmipci_spdif_stream_put
1051 };
1052
1053 /*
1054 */
1055
1056 /* save mixer setting and mute for AC3 playback */
1057 static int save_mixer_state(cmipci_t *cm)
1058 {
1059 if (! cm->mixer_insensitive) {
1060 snd_ctl_elem_value_t *val;
1061 unsigned int i;
1062
1063 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1064 if (!val)
1065 return -ENOMEM;
1066 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1067 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1068 if (ctl) {
1069 int event;
1070 memset(val, 0, sizeof(*val));
1071 ctl->get(ctl, val);
1072 cm->mixer_res_status[i] = val->value.integer.value[0];
1073 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1074 event = SNDRV_CTL_EVENT_MASK_INFO;
1075 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1076 ctl->put(ctl, val); /* toggle */
1077 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1078 }
1079 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1080 snd_ctl_notify(cm->card, event, &ctl->id);
1081 }
1082 }
1083 kfree(val);
1084 cm->mixer_insensitive = 1;
1085 }
1086 return 0;
1087 }
1088
1089
1090 /* restore the previously saved mixer status */
1091 static void restore_mixer_state(cmipci_t *cm)
1092 {
1093 if (cm->mixer_insensitive) {
1094 snd_ctl_elem_value_t *val;
1095 unsigned int i;
1096
1097 val = kmalloc(sizeof(*val), GFP_KERNEL);
1098 if (!val)
1099 return;
1100 cm->mixer_insensitive = 0; /* at first clear this;
1101 otherwise the changes will be ignored */
1102 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1103 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1104 if (ctl) {
1105 int event;
1106
1107 memset(val, 0, sizeof(*val));
1108 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1109 ctl->get(ctl, val);
1110 event = SNDRV_CTL_EVENT_MASK_INFO;
1111 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1112 val->value.integer.value[0] = cm->mixer_res_status[i];
1113 ctl->put(ctl, val);
1114 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1115 }
1116 snd_ctl_notify(cm->card, event, &ctl->id);
1117 }
1118 }
1119 kfree(val);
1120 }
1121 }
1122
1123 /* spinlock held! */
1124 static void setup_ac3(cmipci_t *cm, snd_pcm_substream_t *subs, int do_ac3, int rate)
1125 {
1126 if (do_ac3) {
1127 /* AC3EN for 037 */
1128 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1129 /* AC3EN for 039 */
1130 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1131
1132 if (cm->can_ac3_hw) {
1133 /* SPD24SEL for 037, 0x02 */
1134 /* SPD24SEL for 039, 0x20, but cannot be set */
1135 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1136 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1137 } else { /* can_ac3_sw */
1138 /* SPD32SEL for 037 & 039, 0x20 */
1139 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1140 /* set 176K sample rate to fix 033 HW bug */
1141 if (cm->chip_version == 33) {
1142 if (rate >= 48000) {
1143 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1144 } else {
1145 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1146 }
1147 }
1148 }
1149
1150 } else {
1151 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1152 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1153
1154 if (cm->can_ac3_hw) {
1155 /* chip model >= 37 */
1156 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1157 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1158 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1159 } else {
1160 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1161 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1162 }
1163 } else {
1164 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1165 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1166 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1167 }
1168 }
1169 }
1170
1171 static int setup_spdif_playback(cmipci_t *cm, snd_pcm_substream_t *subs, int up, int do_ac3)
1172 {
1173 int rate, err;
1174
1175 rate = subs->runtime->rate;
1176
1177 if (up && do_ac3)
1178 if ((err = save_mixer_state(cm)) < 0)
1179 return err;
1180
1181 spin_lock_irq(&cm->reg_lock);
1182 cm->spdif_playback_avail = up;
1183 if (up) {
1184 /* they are controlled via "IEC958 Output Switch" */
1185 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1186 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1187 if (cm->spdif_playback_enabled)
1188 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1189 setup_ac3(cm, subs, do_ac3, rate);
1190
1191 if (rate == 48000)
1192 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1193 else
1194 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1195
1196 } else {
1197 /* they are controlled via "IEC958 Output Switch" */
1198 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1199 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1200 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1201 setup_ac3(cm, subs, 0, 0);
1202 }
1203 spin_unlock_irq(&cm->reg_lock);
1204 return 0;
1205 }
1206
1207
1208 /*
1209 * preparation
1210 */
1211
1212 /* playback - enable spdif only on the certain condition */
1213 static int snd_cmipci_playback_prepare(snd_pcm_substream_t *substream)
1214 {
1215 cmipci_t *cm = snd_pcm_substream_chip(substream);
1216 int rate = substream->runtime->rate;
1217 int err, do_spdif, do_ac3 = 0;
1218
1219 do_spdif = ((rate == 44100 || rate == 48000) &&
1220 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1221 substream->runtime->channels == 2);
1222 if (do_spdif && cm->can_ac3_hw)
1223 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1224 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1225 return err;
1226 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1227 }
1228
1229 /* playback (via device #2) - enable spdif always */
1230 static int snd_cmipci_playback_spdif_prepare(snd_pcm_substream_t *substream)
1231 {
1232 cmipci_t *cm = snd_pcm_substream_chip(substream);
1233 int err, do_ac3;
1234
1235 if (cm->can_ac3_hw)
1236 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1237 else
1238 do_ac3 = 1; /* doesn't matter */
1239 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1240 return err;
1241 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1242 }
1243
1244 static int snd_cmipci_playback_hw_free(snd_pcm_substream_t *substream)
1245 {
1246 cmipci_t *cm = snd_pcm_substream_chip(substream);
1247 setup_spdif_playback(cm, substream, 0, 0);
1248 restore_mixer_state(cm);
1249 return snd_cmipci_hw_free(substream);
1250 }
1251
1252 /* capture */
1253 static int snd_cmipci_capture_prepare(snd_pcm_substream_t *substream)
1254 {
1255 cmipci_t *cm = snd_pcm_substream_chip(substream);
1256 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1257 }
1258
1259 /* capture with spdif (via device #2) */
1260 static int snd_cmipci_capture_spdif_prepare(snd_pcm_substream_t *substream)
1261 {
1262 cmipci_t *cm = snd_pcm_substream_chip(substream);
1263
1264 spin_lock_irq(&cm->reg_lock);
1265 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1266 spin_unlock_irq(&cm->reg_lock);
1267
1268 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1269 }
1270
1271 static int snd_cmipci_capture_spdif_hw_free(snd_pcm_substream_t *subs)
1272 {
1273 cmipci_t *cm = snd_pcm_substream_chip(subs);
1274
1275 spin_lock_irq(&cm->reg_lock);
1276 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1277 spin_unlock_irq(&cm->reg_lock);
1278
1279 return snd_cmipci_hw_free(subs);
1280 }
1281
1282
1283 /*
1284 * interrupt handler
1285 */
1286 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1287 {
1288 cmipci_t *cm = dev_id;
1289 unsigned int status, mask = 0;
1290
1291 /* fastpath out, to ease interrupt sharing */
1292 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1293 if (!(status & CM_INTR))
1294 return IRQ_NONE;
1295
1296 /* acknowledge interrupt */
1297 spin_lock(&cm->reg_lock);
1298 if (status & CM_CHINT0)
1299 mask |= CM_CH0_INT_EN;
1300 if (status & CM_CHINT1)
1301 mask |= CM_CH1_INT_EN;
1302 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1303 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1304 spin_unlock(&cm->reg_lock);
1305
1306 if (cm->rmidi && (status & CM_UARTINT))
1307 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs);
1308
1309 if (cm->pcm) {
1310 if ((status & CM_CHINT0) && cm->channel[0].running)
1311 snd_pcm_period_elapsed(cm->channel[0].substream);
1312 if ((status & CM_CHINT1) && cm->channel[1].running)
1313 snd_pcm_period_elapsed(cm->channel[1].substream);
1314 }
1315 return IRQ_HANDLED;
1316 }
1317
1318 /*
1319 * h/w infos
1320 */
1321
1322 /* playback on channel A */
1323 static snd_pcm_hardware_t snd_cmipci_playback =
1324 {
1325 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1326 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1327 SNDRV_PCM_INFO_MMAP_VALID),
1328 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1329 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1330 .rate_min = 5512,
1331 .rate_max = 48000,
1332 .channels_min = 1,
1333 .channels_max = 2,
1334 .buffer_bytes_max = (128*1024),
1335 .period_bytes_min = 64,
1336 .period_bytes_max = (128*1024),
1337 .periods_min = 2,
1338 .periods_max = 1024,
1339 .fifo_size = 0,
1340 };
1341
1342 /* capture on channel B */
1343 static snd_pcm_hardware_t snd_cmipci_capture =
1344 {
1345 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1346 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1347 SNDRV_PCM_INFO_MMAP_VALID),
1348 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1349 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1350 .rate_min = 5512,
1351 .rate_max = 48000,
1352 .channels_min = 1,
1353 .channels_max = 2,
1354 .buffer_bytes_max = (128*1024),
1355 .period_bytes_min = 64,
1356 .period_bytes_max = (128*1024),
1357 .periods_min = 2,
1358 .periods_max = 1024,
1359 .fifo_size = 0,
1360 };
1361
1362 /* playback on channel B - stereo 16bit only? */
1363 static snd_pcm_hardware_t snd_cmipci_playback2 =
1364 {
1365 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1366 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1367 SNDRV_PCM_INFO_MMAP_VALID),
1368 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1369 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1370 .rate_min = 5512,
1371 .rate_max = 48000,
1372 .channels_min = 2,
1373 .channels_max = 2,
1374 .buffer_bytes_max = (128*1024),
1375 .period_bytes_min = 64,
1376 .period_bytes_max = (128*1024),
1377 .periods_min = 2,
1378 .periods_max = 1024,
1379 .fifo_size = 0,
1380 };
1381
1382 /* spdif playback on channel A */
1383 static snd_pcm_hardware_t snd_cmipci_playback_spdif =
1384 {
1385 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1386 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1387 SNDRV_PCM_INFO_MMAP_VALID),
1388 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1389 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1390 .rate_min = 44100,
1391 .rate_max = 48000,
1392 .channels_min = 2,
1393 .channels_max = 2,
1394 .buffer_bytes_max = (128*1024),
1395 .period_bytes_min = 64,
1396 .period_bytes_max = (128*1024),
1397 .periods_min = 2,
1398 .periods_max = 1024,
1399 .fifo_size = 0,
1400 };
1401
1402 /* spdif playback on channel A (32bit, IEC958 subframes) */
1403 static snd_pcm_hardware_t snd_cmipci_playback_iec958_subframe =
1404 {
1405 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1406 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1407 SNDRV_PCM_INFO_MMAP_VALID),
1408 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1409 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1410 .rate_min = 44100,
1411 .rate_max = 48000,
1412 .channels_min = 2,
1413 .channels_max = 2,
1414 .buffer_bytes_max = (128*1024),
1415 .period_bytes_min = 64,
1416 .period_bytes_max = (128*1024),
1417 .periods_min = 2,
1418 .periods_max = 1024,
1419 .fifo_size = 0,
1420 };
1421
1422 /* spdif capture on channel B */
1423 static snd_pcm_hardware_t snd_cmipci_capture_spdif =
1424 {
1425 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1426 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1427 SNDRV_PCM_INFO_MMAP_VALID),
1428 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1429 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1430 .rate_min = 44100,
1431 .rate_max = 48000,
1432 .channels_min = 2,
1433 .channels_max = 2,
1434 .buffer_bytes_max = (128*1024),
1435 .period_bytes_min = 64,
1436 .period_bytes_max = (128*1024),
1437 .periods_min = 2,
1438 .periods_max = 1024,
1439 .fifo_size = 0,
1440 };
1441
1442 /*
1443 * check device open/close
1444 */
1445 static int open_device_check(cmipci_t *cm, int mode, snd_pcm_substream_t *subs)
1446 {
1447 int ch = mode & CM_OPEN_CH_MASK;
1448
1449 /* FIXME: a file should wait until the device becomes free
1450 * when it's opened on blocking mode. however, since the current
1451 * pcm framework doesn't pass file pointer before actually opened,
1452 * we can't know whether blocking mode or not in open callback..
1453 */
1454 down(&cm->open_mutex);
1455 if (cm->opened[ch]) {
1456 up(&cm->open_mutex);
1457 return -EBUSY;
1458 }
1459 cm->opened[ch] = mode;
1460 cm->channel[ch].substream = subs;
1461 if (! (mode & CM_OPEN_DAC)) {
1462 /* disable dual DAC mode */
1463 cm->channel[ch].is_dac = 0;
1464 spin_lock_irq(&cm->reg_lock);
1465 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1466 spin_unlock_irq(&cm->reg_lock);
1467 }
1468 up(&cm->open_mutex);
1469 return 0;
1470 }
1471
1472 static void close_device_check(cmipci_t *cm, int mode)
1473 {
1474 int ch = mode & CM_OPEN_CH_MASK;
1475
1476 down(&cm->open_mutex);
1477 if (cm->opened[ch] == mode) {
1478 if (cm->channel[ch].substream) {
1479 snd_cmipci_ch_reset(cm, ch);
1480 cm->channel[ch].running = 0;
1481 cm->channel[ch].substream = NULL;
1482 }
1483 cm->opened[ch] = 0;
1484 if (! cm->channel[ch].is_dac) {
1485 /* enable dual DAC mode again */
1486 cm->channel[ch].is_dac = 1;
1487 spin_lock_irq(&cm->reg_lock);
1488 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1489 spin_unlock_irq(&cm->reg_lock);
1490 }
1491 }
1492 up(&cm->open_mutex);
1493 }
1494
1495 /*
1496 */
1497
1498 static int snd_cmipci_playback_open(snd_pcm_substream_t *substream)
1499 {
1500 cmipci_t *cm = snd_pcm_substream_chip(substream);
1501 snd_pcm_runtime_t *runtime = substream->runtime;
1502 int err;
1503
1504 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1505 return err;
1506 runtime->hw = snd_cmipci_playback;
1507 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1508 cm->dig_pcm_status = cm->dig_status;
1509 return 0;
1510 }
1511
1512 static int snd_cmipci_capture_open(snd_pcm_substream_t *substream)
1513 {
1514 cmipci_t *cm = snd_pcm_substream_chip(substream);
1515 snd_pcm_runtime_t *runtime = substream->runtime;
1516 int err;
1517
1518 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1519 return err;
1520 runtime->hw = snd_cmipci_capture;
1521 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1522 return 0;
1523 }
1524
1525 static int snd_cmipci_playback2_open(snd_pcm_substream_t *substream)
1526 {
1527 cmipci_t *cm = snd_pcm_substream_chip(substream);
1528 snd_pcm_runtime_t *runtime = substream->runtime;
1529 int err;
1530
1531 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1532 return err;
1533 runtime->hw = snd_cmipci_playback2;
1534 down(&cm->open_mutex);
1535 if (! cm->opened[CM_CH_PLAY]) {
1536 if (cm->can_multi_ch) {
1537 runtime->hw.channels_max = cm->max_channels;
1538 if (cm->max_channels == 4)
1539 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1540 else
1541 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1542 }
1543 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1544 }
1545 up(&cm->open_mutex);
1546 return 0;
1547 }
1548
1549 static int snd_cmipci_playback_spdif_open(snd_pcm_substream_t *substream)
1550 {
1551 cmipci_t *cm = snd_pcm_substream_chip(substream);
1552 snd_pcm_runtime_t *runtime = substream->runtime;
1553 int err;
1554
1555 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1556 return err;
1557 if (cm->can_ac3_hw) {
1558 runtime->hw = snd_cmipci_playback_spdif;
1559 if (cm->chip_version >= 37)
1560 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1561 } else {
1562 runtime->hw = snd_cmipci_playback_iec958_subframe;
1563 }
1564 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1565 cm->dig_pcm_status = cm->dig_status;
1566 return 0;
1567 }
1568
1569 static int snd_cmipci_capture_spdif_open(snd_pcm_substream_t * substream)
1570 {
1571 cmipci_t *cm = snd_pcm_substream_chip(substream);
1572 snd_pcm_runtime_t *runtime = substream->runtime;
1573 int err;
1574
1575 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1576 return err;
1577 runtime->hw = snd_cmipci_capture_spdif;
1578 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1579 return 0;
1580 }
1581
1582
1583 /*
1584 */
1585
1586 static int snd_cmipci_playback_close(snd_pcm_substream_t * substream)
1587 {
1588 cmipci_t *cm = snd_pcm_substream_chip(substream);
1589 close_device_check(cm, CM_OPEN_PLAYBACK);
1590 return 0;
1591 }
1592
1593 static int snd_cmipci_capture_close(snd_pcm_substream_t * substream)
1594 {
1595 cmipci_t *cm = snd_pcm_substream_chip(substream);
1596 close_device_check(cm, CM_OPEN_CAPTURE);
1597 return 0;
1598 }
1599
1600 static int snd_cmipci_playback2_close(snd_pcm_substream_t * substream)
1601 {
1602 cmipci_t *cm = snd_pcm_substream_chip(substream);
1603 close_device_check(cm, CM_OPEN_PLAYBACK2);
1604 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1605 return 0;
1606 }
1607
1608 static int snd_cmipci_playback_spdif_close(snd_pcm_substream_t * substream)
1609 {
1610 cmipci_t *cm = snd_pcm_substream_chip(substream);
1611 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1612 return 0;
1613 }
1614
1615 static int snd_cmipci_capture_spdif_close(snd_pcm_substream_t * substream)
1616 {
1617 cmipci_t *cm = snd_pcm_substream_chip(substream);
1618 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1619 return 0;
1620 }
1621
1622
1623 /*
1624 */
1625
1626 static snd_pcm_ops_t snd_cmipci_playback_ops = {
1627 .open = snd_cmipci_playback_open,
1628 .close = snd_cmipci_playback_close,
1629 .ioctl = snd_pcm_lib_ioctl,
1630 .hw_params = snd_cmipci_hw_params,
1631 .hw_free = snd_cmipci_playback_hw_free,
1632 .prepare = snd_cmipci_playback_prepare,
1633 .trigger = snd_cmipci_playback_trigger,
1634 .pointer = snd_cmipci_playback_pointer,
1635 };
1636
1637 static snd_pcm_ops_t snd_cmipci_capture_ops = {
1638 .open = snd_cmipci_capture_open,
1639 .close = snd_cmipci_capture_close,
1640 .ioctl = snd_pcm_lib_ioctl,
1641 .hw_params = snd_cmipci_hw_params,
1642 .hw_free = snd_cmipci_hw_free,
1643 .prepare = snd_cmipci_capture_prepare,
1644 .trigger = snd_cmipci_capture_trigger,
1645 .pointer = snd_cmipci_capture_pointer,
1646 };
1647
1648 static snd_pcm_ops_t snd_cmipci_playback2_ops = {
1649 .open = snd_cmipci_playback2_open,
1650 .close = snd_cmipci_playback2_close,
1651 .ioctl = snd_pcm_lib_ioctl,
1652 .hw_params = snd_cmipci_playback2_hw_params,
1653 .hw_free = snd_cmipci_hw_free,
1654 .prepare = snd_cmipci_capture_prepare, /* channel B */
1655 .trigger = snd_cmipci_capture_trigger, /* channel B */
1656 .pointer = snd_cmipci_capture_pointer, /* channel B */
1657 };
1658
1659 static snd_pcm_ops_t snd_cmipci_playback_spdif_ops = {
1660 .open = snd_cmipci_playback_spdif_open,
1661 .close = snd_cmipci_playback_spdif_close,
1662 .ioctl = snd_pcm_lib_ioctl,
1663 .hw_params = snd_cmipci_hw_params,
1664 .hw_free = snd_cmipci_playback_hw_free,
1665 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1666 .trigger = snd_cmipci_playback_trigger,
1667 .pointer = snd_cmipci_playback_pointer,
1668 };
1669
1670 static snd_pcm_ops_t snd_cmipci_capture_spdif_ops = {
1671 .open = snd_cmipci_capture_spdif_open,
1672 .close = snd_cmipci_capture_spdif_close,
1673 .ioctl = snd_pcm_lib_ioctl,
1674 .hw_params = snd_cmipci_hw_params,
1675 .hw_free = snd_cmipci_capture_spdif_hw_free,
1676 .prepare = snd_cmipci_capture_spdif_prepare,
1677 .trigger = snd_cmipci_capture_trigger,
1678 .pointer = snd_cmipci_capture_pointer,
1679 };
1680
1681
1682 /*
1683 */
1684
1685 static void snd_cmipci_pcm_free(snd_pcm_t *pcm)
1686 {
1687 snd_pcm_lib_preallocate_free_for_all(pcm);
1688 }
1689
1690 static int __devinit snd_cmipci_pcm_new(cmipci_t *cm, int device)
1691 {
1692 snd_pcm_t *pcm;
1693 int err;
1694
1695 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1696 if (err < 0)
1697 return err;
1698
1699 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1700 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1701
1702 pcm->private_data = cm;
1703 pcm->private_free = snd_cmipci_pcm_free;
1704 pcm->info_flags = 0;
1705 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1706 cm->pcm = pcm;
1707
1708 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1709 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1710
1711 return 0;
1712 }
1713
1714 static int __devinit snd_cmipci_pcm2_new(cmipci_t *cm, int device)
1715 {
1716 snd_pcm_t *pcm;
1717 int err;
1718
1719 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1720 if (err < 0)
1721 return err;
1722
1723 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1724
1725 pcm->private_data = cm;
1726 pcm->private_free = snd_cmipci_pcm_free;
1727 pcm->info_flags = 0;
1728 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1729 cm->pcm2 = pcm;
1730
1731 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1732 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1733
1734 return 0;
1735 }
1736
1737 static int __devinit snd_cmipci_pcm_spdif_new(cmipci_t *cm, int device)
1738 {
1739 snd_pcm_t *pcm;
1740 int err;
1741
1742 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1743 if (err < 0)
1744 return err;
1745
1746 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1747 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1748
1749 pcm->private_data = cm;
1750 pcm->private_free = snd_cmipci_pcm_free;
1751 pcm->info_flags = 0;
1752 strcpy(pcm->name, "C-Media PCI IEC958");
1753 cm->pcm_spdif = pcm;
1754
1755 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1756 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1757
1758 return 0;
1759 }
1760
1761 /*
1762 * mixer interface:
1763 * - CM8338/8738 has a compatible mixer interface with SB16, but
1764 * lack of some elements like tone control, i/o gain and AGC.
1765 * - Access to native registers:
1766 * - A 3D switch
1767 * - Output mute switches
1768 */
1769
1770 static void snd_cmipci_mixer_write(cmipci_t *s, unsigned char idx, unsigned char data)
1771 {
1772 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1773 outb(data, s->iobase + CM_REG_SB16_DATA);
1774 }
1775
1776 static unsigned char snd_cmipci_mixer_read(cmipci_t *s, unsigned char idx)
1777 {
1778 unsigned char v;
1779
1780 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1781 v = inb(s->iobase + CM_REG_SB16_DATA);
1782 return v;
1783 }
1784
1785 /*
1786 * general mixer element
1787 */
1788 typedef struct cmipci_sb_reg {
1789 unsigned int left_reg, right_reg;
1790 unsigned int left_shift, right_shift;
1791 unsigned int mask;
1792 unsigned int invert: 1;
1793 unsigned int stereo: 1;
1794 } cmipci_sb_reg_t;
1795
1796 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1797 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1798
1799 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1800 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1801 .info = snd_cmipci_info_volume, \
1802 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1803 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1804 }
1805
1806 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1807 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1808 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1809 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1810
1811 static void cmipci_sb_reg_decode(cmipci_sb_reg_t *r, unsigned long val)
1812 {
1813 r->left_reg = val & 0xff;
1814 r->right_reg = (val >> 8) & 0xff;
1815 r->left_shift = (val >> 16) & 0x07;
1816 r->right_shift = (val >> 19) & 0x07;
1817 r->invert = (val >> 22) & 1;
1818 r->stereo = (val >> 23) & 1;
1819 r->mask = (val >> 24) & 0xff;
1820 }
1821
1822 static int snd_cmipci_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1823 {
1824 cmipci_sb_reg_t reg;
1825
1826 cmipci_sb_reg_decode(®, kcontrol->private_value);
1827 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1828 uinfo->count = reg.stereo + 1;
1829 uinfo->value.integer.min = 0;
1830 uinfo->value.integer.max = reg.mask;
1831 return 0;
1832 }
1833
1834 static int snd_cmipci_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1835 {
1836 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1837 cmipci_sb_reg_t reg;
1838 int val;
1839
1840 cmipci_sb_reg_decode(®, kcontrol->private_value);
1841 spin_lock_irq(&cm->reg_lock);
1842 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1843 if (reg.invert)
1844 val = reg.mask - val;
1845 ucontrol->value.integer.value[0] = val;
1846 if (reg.stereo) {
1847 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1848 if (reg.invert)
1849 val = reg.mask - val;
1850 ucontrol->value.integer.value[1] = val;
1851 }
1852 spin_unlock_irq(&cm->reg_lock);
1853 return 0;
1854 }
1855
1856 static int snd_cmipci_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1857 {
1858 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1859 cmipci_sb_reg_t reg;
1860 int change;
1861 int left, right, oleft, oright;
1862
1863 cmipci_sb_reg_decode(®, kcontrol->private_value);
1864 left = ucontrol->value.integer.value[0] & reg.mask;
1865 if (reg.invert)
1866 left = reg.mask - left;
1867 left <<= reg.left_shift;
1868 if (reg.stereo) {
1869 right = ucontrol->value.integer.value[1] & reg.mask;
1870 if (reg.invert)
1871 right = reg.mask - right;
1872 right <<= reg.right_shift;
1873 } else
1874 right = 0;
1875 spin_lock_irq(&cm->reg_lock);
1876 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1877 left |= oleft & ~(reg.mask << reg.left_shift);
1878 change = left != oleft;
1879 if (reg.stereo) {
1880 if (reg.left_reg != reg.right_reg) {
1881 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1882 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1883 } else
1884 oright = left;
1885 right |= oright & ~(reg.mask << reg.right_shift);
1886 change |= right != oright;
1887 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1888 } else
1889 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1890 spin_unlock_irq(&cm->reg_lock);
1891 return change;
1892 }
1893
1894 /*
1895 * input route (left,right) -> (left,right)
1896 */
1897 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1898 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1899 .info = snd_cmipci_info_input_sw, \
1900 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1901 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1902 }
1903
1904 static int snd_cmipci_info_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1905 {
1906 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1907 uinfo->count = 4;
1908 uinfo->value.integer.min = 0;
1909 uinfo->value.integer.max = 1;
1910 return 0;
1911 }
1912
1913 static int snd_cmipci_get_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1914 {
1915 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1916 cmipci_sb_reg_t reg;
1917 int val1, val2;
1918
1919 cmipci_sb_reg_decode(®, kcontrol->private_value);
1920 spin_lock_irq(&cm->reg_lock);
1921 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1922 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1923 spin_unlock_irq(&cm->reg_lock);
1924 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
1925 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
1926 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
1927 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
1928 return 0;
1929 }
1930
1931 static int snd_cmipci_put_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1932 {
1933 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1934 cmipci_sb_reg_t reg;
1935 int change;
1936 int val1, val2, oval1, oval2;
1937
1938 cmipci_sb_reg_decode(®, kcontrol->private_value);
1939 spin_lock_irq(&cm->reg_lock);
1940 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1941 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1942 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1943 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1944 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
1945 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
1946 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
1947 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
1948 change = val1 != oval1 || val2 != oval2;
1949 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
1950 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
1951 spin_unlock_irq(&cm->reg_lock);
1952 return change;
1953 }
1954
1955 /*
1956 * native mixer switches/volumes
1957 */
1958
1959 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
1960 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1961 .info = snd_cmipci_info_native_mixer, \
1962 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1963 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
1964 }
1965
1966 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
1967 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1968 .info = snd_cmipci_info_native_mixer, \
1969 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1970 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
1971 }
1972
1973 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
1974 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1975 .info = snd_cmipci_info_native_mixer, \
1976 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1977 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
1978 }
1979
1980 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
1981 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1982 .info = snd_cmipci_info_native_mixer, \
1983 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1984 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
1985 }
1986
1987 static int snd_cmipci_info_native_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1988 {
1989 cmipci_sb_reg_t reg;
1990
1991 cmipci_sb_reg_decode(®, kcontrol->private_value);
1992 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1993 uinfo->count = reg.stereo + 1;
1994 uinfo->value.integer.min = 0;
1995 uinfo->value.integer.max = reg.mask;
1996 return 0;
1997
1998 }
1999
2000 static int snd_cmipci_get_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2001 {
2002 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2003 cmipci_sb_reg_t reg;
2004 unsigned char oreg, val;
2005
2006 cmipci_sb_reg_decode(®, kcontrol->private_value);
2007 spin_lock_irq(&cm->reg_lock);
2008 oreg = inb(cm->iobase + reg.left_reg);
2009 val = (oreg >> reg.left_shift) & reg.mask;
2010 if (reg.invert)
2011 val = reg.mask - val;
2012 ucontrol->value.integer.value[0] = val;
2013 if (reg.stereo) {
2014 val = (oreg >> reg.right_shift) & reg.mask;
2015 if (reg.invert)
2016 val = reg.mask - val;
2017 ucontrol->value.integer.value[1] = val;
2018 }
2019 spin_unlock_irq(&cm->reg_lock);
2020 return 0;
2021 }
2022
2023 static int snd_cmipci_put_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2024 {
2025 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2026 cmipci_sb_reg_t reg;
2027 unsigned char oreg, nreg, val;
2028
2029 cmipci_sb_reg_decode(®, kcontrol->private_value);
2030 spin_lock_irq(&cm->reg_lock);
2031 oreg = inb(cm->iobase + reg.left_reg);
2032 val = ucontrol->value.integer.value[0] & reg.mask;
2033 if (reg.invert)
2034 val = reg.mask - val;
2035 nreg = oreg & ~(reg.mask << reg.left_shift);
2036 nreg |= (val << reg.left_shift);
2037 if (reg.stereo) {
2038 val = ucontrol->value.integer.value[1] & reg.mask;
2039 if (reg.invert)
2040 val = reg.mask - val;
2041 nreg &= ~(reg.mask << reg.right_shift);
2042 nreg |= (val << reg.right_shift);
2043 }
2044 outb(nreg, cm->iobase + reg.left_reg);
2045 spin_unlock_irq(&cm->reg_lock);
2046 return (nreg != oreg);
2047 }
2048
2049 /*
2050 * special case - check mixer sensitivity
2051 */
2052 static int snd_cmipci_get_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2053 {
2054 //cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2055 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2056 }
2057
2058 static int snd_cmipci_put_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2059 {
2060 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2061 if (cm->mixer_insensitive) {
2062 /* ignored */
2063 return 0;
2064 }
2065 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2066 }
2067
2068
2069 static snd_kcontrol_new_t snd_cmipci_mixers[] __devinitdata = {
2070 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2071 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2072 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2073 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2074 { /* switch with sensitivity */
2075 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2076 .name = "PCM Playback Switch",
2077 .info = snd_cmipci_info_native_mixer,
2078 .get = snd_cmipci_get_native_mixer_sensitive,
2079 .put = snd_cmipci_put_native_mixer_sensitive,
2080 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2081 },
2082 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2083 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2084 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2085 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2086 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2087 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2088 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2089 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2090 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2091 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2092 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2093 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2094 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2095 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2096 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2097 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2098 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2099 CMIPCI_MIXER_SW_MONO("Mic Boost", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2100 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2101 };
2102
2103 /*
2104 * other switches
2105 */
2106
2107 typedef struct snd_cmipci_switch_args {
2108 int reg; /* register index */
2109 unsigned int mask; /* mask bits */
2110 unsigned int mask_on; /* mask bits to turn on */
2111 int is_byte: 1; /* byte access? */
2112 int ac3_sensitive: 1; /* access forbidden during non-audio operation? */
2113 } snd_cmipci_switch_args_t;
2114
2115 static int snd_cmipci_uswitch_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
2116 {
2117 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2118 uinfo->count = 1;
2119 uinfo->value.integer.min = 0;
2120 uinfo->value.integer.max = 1;
2121 return 0;
2122 }
2123
2124 static int _snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2125 {
2126 unsigned int val;
2127 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2128
2129 spin_lock_irq(&cm->reg_lock);
2130 if (args->ac3_sensitive && cm->mixer_insensitive) {
2131 ucontrol->value.integer.value[0] = 0;
2132 spin_unlock_irq(&cm->reg_lock);
2133 return 0;
2134 }
2135 if (args->is_byte)
2136 val = inb(cm->iobase + args->reg);
2137 else
2138 val = snd_cmipci_read(cm, args->reg);
2139 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2140 spin_unlock_irq(&cm->reg_lock);
2141 return 0;
2142 }
2143
2144 static int snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2145 {
2146 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2147 snd_assert(args != NULL, return -EINVAL);
2148 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2149 }
2150
2151 static int _snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2152 {
2153 unsigned int val;
2154 int change;
2155 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2156
2157 spin_lock_irq(&cm->reg_lock);
2158 if (args->ac3_sensitive && cm->mixer_insensitive) {
2159 /* ignored */
2160 spin_unlock_irq(&cm->reg_lock);
2161 return 0;
2162 }
2163 if (args->is_byte)
2164 val = inb(cm->iobase + args->reg);
2165 else
2166 val = snd_cmipci_read(cm, args->reg);
2167 change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0);
2168 if (change) {
2169 val &= ~args->mask;
2170 if (ucontrol->value.integer.value[0])
2171 val |= args->mask_on;
2172 else
2173 val |= (args->mask & ~args->mask_on);
2174 if (args->is_byte)
2175 outb((unsigned char)val, cm->iobase + args->reg);
2176 else
2177 snd_cmipci_write(cm, args->reg, val);
2178 }
2179 spin_unlock_irq(&cm->reg_lock);
2180 return change;
2181 }
2182
2183 static int snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2184 {
2185 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2186 snd_assert(args != NULL, return -EINVAL);
2187 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2188 }
2189
2190 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2191 static snd_cmipci_switch_args_t cmipci_switch_arg_##sname = { \
2192 .reg = xreg, \
2193 .mask = xmask, \
2194 .mask_on = xmask_on, \
2195 .is_byte = xis_byte, \
2196 .ac3_sensitive = xac3, \
2197 }
2198
2199 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2200 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2201
2202 #if 0 /* these will be controlled in pcm device */
2203 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2204 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2205 #endif
2206 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2207 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2208 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2209 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2210 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2211 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2212 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2213 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2214 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2215 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2216 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2217 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2218 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2219 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2220 #if CM_CH_PLAY == 1
2221 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2222 #else
2223 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2224 #endif
2225 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2226 DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2227 DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
2228 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2229 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2230
2231 #define DEFINE_SWITCH(sname, stype, sarg) \
2232 { .name = sname, \
2233 .iface = stype, \
2234 .info = snd_cmipci_uswitch_info, \
2235 .get = snd_cmipci_uswitch_get, \
2236 .put = snd_cmipci_uswitch_put, \
2237 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2238 }
2239
2240 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2241 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2242
2243
2244 /*
2245 * callbacks for spdif output switch
2246 * needs toggle two registers..
2247 */
2248 static int snd_cmipci_spdout_enable_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2249 {
2250 int changed;
2251 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2252 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2253 return changed;
2254 }
2255
2256 static int snd_cmipci_spdout_enable_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2257 {
2258 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
2259 int changed;
2260 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2261 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2262 if (changed) {
2263 if (ucontrol->value.integer.value[0]) {
2264 if (chip->spdif_playback_avail)
2265 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2266 } else {
2267 if (chip->spdif_playback_avail)
2268 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2269 }
2270 }
2271 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2272 return changed;
2273 }
2274
2275
2276 /* both for CM8338/8738 */
2277 static snd_kcontrol_new_t snd_cmipci_mixer_switches[] __devinitdata = {
2278 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2279 DEFINE_MIXER_SWITCH("Line-In As Rear", line_rear),
2280 };
2281
2282 /* for non-multichannel chips */
2283 static snd_kcontrol_new_t snd_cmipci_nomulti_switch __devinitdata =
2284 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2285
2286 /* only for CM8738 */
2287 static snd_kcontrol_new_t snd_cmipci_8738_mixer_switches[] __devinitdata = {
2288 #if 0 /* controlled in pcm device */
2289 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2290 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2291 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2292 #endif
2293 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2294 { .name = "IEC958 Output Switch",
2295 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2296 .info = snd_cmipci_uswitch_info,
2297 .get = snd_cmipci_spdout_enable_get,
2298 .put = snd_cmipci_spdout_enable_put,
2299 },
2300 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2301 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2302 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2303 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2304 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2305 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2306 };
2307
2308 /* only for model 033/037 */
2309 static snd_kcontrol_new_t snd_cmipci_old_mixer_switches[] __devinitdata = {
2310 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2311 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2312 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2313 };
2314
2315 /* only for model 039 or later */
2316 static snd_kcontrol_new_t snd_cmipci_extra_mixer_switches[] __devinitdata = {
2317 DEFINE_MIXER_SWITCH("Line-In As Bass", line_bass),
2318 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2319 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2320 DEFINE_MIXER_SWITCH("Mic As Center/LFE", spdi_phase), /* same bit as spdi_phase */
2321 };
2322
2323 /* card control switches */
2324 static snd_kcontrol_new_t snd_cmipci_control_switches[] __devinitdata = {
2325 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2326 DEFINE_CARD_SWITCH("Modem", modem),
2327 };
2328
2329
2330 static int __devinit snd_cmipci_mixer_new(cmipci_t *cm, int pcm_spdif_device)
2331 {
2332 snd_card_t *card;
2333 snd_kcontrol_new_t *sw;
2334 snd_kcontrol_t *kctl;
2335 unsigned int idx;
2336 int err;
2337
2338 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2339
2340 card = cm->card;
2341
2342 strcpy(card->mixername, "CMedia PCI");
2343
2344 spin_lock_irq(&cm->reg_lock);
2345 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2346 spin_unlock_irq(&cm->reg_lock);
2347
2348 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2349 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2350 return err;
2351 }
2352
2353 /* mixer switches */
2354 sw = snd_cmipci_mixer_switches;
2355 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2356 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2357 if (err < 0)
2358 return err;
2359 }
2360 if (! cm->can_multi_ch) {
2361 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2362 if (err < 0)
2363 return err;
2364 }
2365 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2366 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2367 sw = snd_cmipci_8738_mixer_switches;
2368 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2369 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2370 if (err < 0)
2371 return err;
2372 }
2373 if (cm->can_ac3_hw) {
2374 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2375 return err;
2376 kctl->id.device = pcm_spdif_device;
2377 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2378 return err;
2379 kctl->id.device = pcm_spdif_device;
2380 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2381 return err;
2382 kctl->id.device = pcm_spdif_device;
2383 }
2384 if (cm->chip_version <= 37) {
2385 sw = snd_cmipci_old_mixer_switches;
2386 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2387 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2388 if (err < 0)
2389 return err;
2390 }
2391 }
2392 }
2393 if (cm->chip_version >= 39) {
2394 sw = snd_cmipci_extra_mixer_switches;
2395 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2396 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2397 if (err < 0)
2398 return err;
2399 }
2400 }
2401
2402 /* card switches */
2403 sw = snd_cmipci_control_switches;
2404 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2405 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2406 if (err < 0)
2407 return err;
2408 }
2409
2410 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2411 snd_ctl_elem_id_t id;
2412 snd_kcontrol_t *ctl;
2413 memset(&id, 0, sizeof(id));
2414 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2415 strcpy(id.name, cm_saved_mixer[idx].name);
2416 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2417 cm->mixer_res_ctl[idx] = ctl;
2418 }
2419
2420 return 0;
2421 }
2422
2423
2424 /*
2425 * proc interface
2426 */
2427
2428 #ifdef CONFIG_PROC_FS
2429 static void snd_cmipci_proc_read(snd_info_entry_t *entry,
2430 snd_info_buffer_t *buffer)
2431 {
2432 cmipci_t *cm = entry->private_data;
2433 int i;
2434
2435 snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2436 for (i = 0; i < 0x40; i++) {
2437 int v = inb(cm->iobase + i);
2438 if (i % 4 == 0)
2439 snd_iprintf(buffer, "%02x: ", i);
2440 snd_iprintf(buffer, "%02x", v);
2441 if (i % 4 == 3)
2442 snd_iprintf(buffer, "\n");
2443 else
2444 snd_iprintf(buffer, " ");
2445 }
2446 }
2447
2448 static void __devinit snd_cmipci_proc_init(cmipci_t *cm)
2449 {
2450 snd_info_entry_t *entry;
2451
2452 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2453 snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read);
2454 }
2455 #else /* !CONFIG_PROC_FS */
2456 static inline void snd_cmipci_proc_init(cmipci_t *cm) {}
2457 #endif
2458
2459
2460 static struct pci_device_id snd_cmipci_ids[] = {
2461 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2462 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2463 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2464 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2465 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2466 {0,},
2467 };
2468
2469
2470 /*
2471 * check chip version and capabilities
2472 * driver name is modified according to the chip model
2473 */
2474 static void __devinit query_chip(cmipci_t *cm)
2475 {
2476 unsigned int detect;
2477
2478 /* check reg 0Ch, bit 24-31 */
2479 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2480 if (! detect) {
2481 /* check reg 08h, bit 24-28 */
2482 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2483 if (! detect) {
2484 cm->chip_version = 33;
2485 cm->max_channels = 2;
2486 if (cm->do_soft_ac3)
2487 cm->can_ac3_sw = 1;
2488 else
2489 cm->can_ac3_hw = 1;
2490 cm->has_dual_dac = 1;
2491 } else {
2492 cm->chip_version = 37;
2493 cm->max_channels = 2;
2494 cm->can_ac3_hw = 1;
2495 cm->has_dual_dac = 1;
2496 }
2497 } else {
2498 /* check reg 0Ch, bit 26 */
2499 if (detect & CM_CHIP_039) {
2500 cm->chip_version = 39;
2501 if (detect & CM_CHIP_039_6CH)
2502 cm->max_channels = 6;
2503 else
2504 cm->max_channels = 4;
2505 cm->can_ac3_hw = 1;
2506 cm->has_dual_dac = 1;
2507 cm->can_multi_ch = 1;
2508 } else {
2509 cm->chip_version = 55; /* 4 or 6 channels */
2510 cm->max_channels = 6;
2511 cm->can_ac3_hw = 1;
2512 cm->has_dual_dac = 1;
2513 cm->can_multi_ch = 1;
2514 }
2515 }
2516
2517 /* added -MCx suffix for chip supporting multi-channels */
2518 if (cm->can_multi_ch)
2519 sprintf(cm->card->driver + strlen(cm->card->driver),
2520 "-MC%d", cm->max_channels);
2521 else if (cm->can_ac3_sw)
2522 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2523 }
2524
2525
2526 static int snd_cmipci_free(cmipci_t *cm)
2527 {
2528 if (cm->irq >= 0) {
2529 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2530 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2531 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2532 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2533 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2534 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2535 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2536
2537 /* reset mixer */
2538 snd_cmipci_mixer_write(cm, 0, 0);
2539
2540 synchronize_irq(cm->irq);
2541
2542 free_irq(cm->irq, (void *)cm);
2543 }
2544 #ifdef SUPPORT_JOYSTICK
2545 if (cm->res_joystick) {
2546 gameport_unregister_port(&cm->gameport);
2547 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2548 release_resource(cm->res_joystick);
2549 kfree_nocheck(cm->res_joystick);
2550 }
2551 #endif
2552 pci_release_regions(cm->pci);
2553 pci_disable_device(cm->pci);
2554 kfree(cm);
2555 return 0;
2556 }
2557
2558 static int snd_cmipci_dev_free(snd_device_t *device)
2559 {
2560 cmipci_t *cm = device->device_data;
2561 return snd_cmipci_free(cm);
2562 }
2563
2564 static int __devinit snd_cmipci_create(snd_card_t *card, struct pci_dev *pci,
2565 int dev, cmipci_t **rcmipci)
2566 {
2567 cmipci_t *cm;
2568 int err;
2569 static snd_device_ops_t ops = {
2570 .dev_free = snd_cmipci_dev_free,
2571 };
2572 unsigned int val = 0;
2573 long iomidi = mpu_port[dev];
2574 long iosynth = fm_port[dev];
2575 int pcm_index, pcm_spdif_index;
2576 static struct pci_device_id intel_82437vx[] = {
2577 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2578 { },
2579 };
2580
2581 *rcmipci = NULL;
2582
2583 if ((err = pci_enable_device(pci)) < 0)
2584 return err;
2585
2586 cm = kcalloc(1, sizeof(*cm), GFP_KERNEL);
2587 if (cm == NULL) {
2588 pci_disable_device(pci);
2589 return -ENOMEM;
2590 }
2591
2592 spin_lock_init(&cm->reg_lock);
2593 init_MUTEX(&cm->open_mutex);
2594 cm->device = pci->device;
2595 cm->card = card;
2596 cm->pci = pci;
2597 cm->irq = -1;
2598 cm->channel[0].ch = 0;
2599 cm->channel[1].ch = 1;
2600 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2601
2602 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2603 kfree(cm);
2604 pci_disable_device(pci);
2605 return err;
2606 }
2607 cm->iobase = pci_resource_start(pci, 0);
2608
2609 if (request_irq(pci->irq, snd_cmipci_interrupt, SA_INTERRUPT|SA_SHIRQ, card->driver, (void *)cm)) {
2610 snd_printk("unable to grab IRQ %d\n", pci->irq);
2611 snd_cmipci_free(cm);
2612 return -EBUSY;
2613 }
2614 cm->irq = pci->irq;
2615
2616 pci_set_master(cm->pci);
2617
2618 /*
2619 * check chip version, max channels and capabilities
2620 */
2621
2622 cm->chip_version = 0;
2623 cm->max_channels = 2;
2624 cm->do_soft_ac3 = soft_ac3[dev];
2625
2626 query_chip(cm);
2627
2628 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2629 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2630
2631 #if CM_CH_PLAY == 1
2632 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
2633 #else
2634 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
2635 #endif
2636
2637 /* initialize codec registers */
2638 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2639 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2640 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2641 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2642 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2643
2644 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2645 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2646 #if CM_CH_PLAY == 1
2647 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2648 #else
2649 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2650 #endif
2651 /* Set Bus Master Request */
2652 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2653
2654 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2655 switch (pci->device) {
2656 case PCI_DEVICE_ID_CMEDIA_CM8738:
2657 case PCI_DEVICE_ID_CMEDIA_CM8738B:
2658 if (!pci_dev_present(intel_82437vx))
2659 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2660 break;
2661 default:
2662 break;
2663 }
2664
2665 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2666 snd_cmipci_free(cm);
2667 return err;
2668 }
2669
2670 /* set MPU address */
2671 switch (iomidi) {
2672 case 0x320: val = CM_VMPU_320; break;
2673 case 0x310: val = CM_VMPU_310; break;
2674 case 0x300: val = CM_VMPU_300; break;
2675 case 0x330: val = CM_VMPU_330; break;
2676 default:
2677 iomidi = 0; break;
2678 }
2679 if (iomidi > 0) {
2680 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2681 /* enable UART */
2682 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
2683 }
2684
2685 /* set FM address */
2686 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2687 switch (iosynth) {
2688 case 0x3E8: val |= CM_FMSEL_3E8; break;
2689 case 0x3E0: val |= CM_FMSEL_3E0; break;
2690 case 0x3C8: val |= CM_FMSEL_3C8; break;
2691 case 0x388: val |= CM_FMSEL_388; break;
2692 default:
2693 iosynth = 0; break;
2694 }
2695 if (iosynth > 0) {
2696 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2697 /* enable FM */
2698 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2699
2700 if (snd_opl3_create(card, iosynth, iosynth + 2,
2701 OPL3_HW_OPL3, 0, &cm->opl3) < 0) {
2702 printk(KERN_ERR "cmipci: no OPL device at 0x%lx, skipping...\n", iosynth);
2703 iosynth = 0;
2704 } else {
2705 if ((err = snd_opl3_hwdep_new(cm->opl3, 0, 1, &cm->opl3hwdep)) < 0) {
2706 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2707 return err;
2708 }
2709 }
2710 }
2711 if (! iosynth) {
2712 /* disable FM */
2713 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val & ~CM_FMSEL_MASK);
2714 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2715 }
2716
2717 /* reset mixer */
2718 snd_cmipci_mixer_write(cm, 0, 0);
2719
2720 snd_cmipci_proc_init(cm);
2721
2722 /* create pcm devices */
2723 pcm_index = pcm_spdif_index = 0;
2724 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
2725 return err;
2726 pcm_index++;
2727 if (cm->has_dual_dac) {
2728 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
2729 return err;
2730 pcm_index++;
2731 }
2732 if (cm->can_ac3_hw || cm->can_ac3_sw) {
2733 pcm_spdif_index = pcm_index;
2734 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
2735 return err;
2736 }
2737
2738 /* create mixer interface & switches */
2739 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
2740 return err;
2741
2742 if (iomidi > 0) {
2743 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
2744 iomidi, 0,
2745 cm->irq, 0, &cm->rmidi)) < 0) {
2746 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
2747 }
2748 }
2749
2750 #ifdef USE_VAR48KRATE
2751 for (val = 0; val < ARRAY_SIZE(rates); val++)
2752 snd_cmipci_set_pll(cm, rates[val], val);
2753
2754 /*
2755 * (Re-)Enable external switch spdo_48k
2756 */
2757 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
2758 #endif /* USE_VAR48KRATE */
2759
2760 #ifdef SUPPORT_JOYSTICK
2761 if (joystick_port[dev] > 0) {
2762 if (joystick_port[dev] == 1) { /* auto-detect */
2763 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2764 int i;
2765 for (i = 0; ports[i]; i++) {
2766 joystick_port[dev] = ports[i];
2767 cm->res_joystick = request_region(ports[i], 1, "CMIPCI gameport");
2768 if (cm->res_joystick)
2769 break;
2770 }
2771 } else {
2772 cm->res_joystick = request_region(joystick_port[dev], 1, "CMIPCI gameport");
2773 }
2774 }
2775 if (cm->res_joystick) {
2776 cm->gameport.io = joystick_port[dev];
2777 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2778 gameport_register_port(&cm->gameport);
2779 } else {
2780 if (joystick_port[dev] > 0)
2781 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2782 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2783 }
2784 #endif
2785 snd_card_set_dev(card, &pci->dev);
2786
2787 *rcmipci = cm;
2788 return 0;
2789 }
2790
2791 /*
2792 */
2793
2794 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
2795
2796 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
2797 const struct pci_device_id *pci_id)
2798 {
2799 static int dev;
2800 snd_card_t *card;
2801 cmipci_t *cm;
2802 int err;
2803
2804 if (dev >= SNDRV_CARDS)
2805 return -ENODEV;
2806 if (! enable[dev]) {
2807 dev++;
2808 return -ENOENT;
2809 }
2810
2811 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2812 if (card == NULL)
2813 return -ENOMEM;
2814
2815 switch (pci->device) {
2816 case PCI_DEVICE_ID_CMEDIA_CM8738:
2817 case PCI_DEVICE_ID_CMEDIA_CM8738B:
2818 strcpy(card->driver, "CMI8738");
2819 break;
2820 case PCI_DEVICE_ID_CMEDIA_CM8338A:
2821 case PCI_DEVICE_ID_CMEDIA_CM8338B:
2822 strcpy(card->driver, "CMI8338");
2823 break;
2824 default:
2825 strcpy(card->driver, "CMIPCI");
2826 break;
2827 }
2828
2829 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
2830 snd_card_free(card);
2831 return err;
2832 }
2833
2834 sprintf(card->shortname, "C-Media PCI %s", card->driver);
2835 sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i",
2836 card->shortname,
2837 cm->chip_version,
2838 cm->iobase,
2839 cm->irq);
2840
2841 //snd_printd("%s is detected\n", card->longname);
2842
2843 if ((err = snd_card_register(card)) < 0) {
2844 snd_card_free(card);
2845 return err;
2846 }
2847 pci_set_drvdata(pci, card);
2848 dev++;
2849 return 0;
2850
2851 }
2852
2853 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
2854 {
2855 snd_card_free(pci_get_drvdata(pci));
2856 pci_set_drvdata(pci, NULL);
2857 }
2858
2859
2860 static struct pci_driver driver = {
2861 .name = "C-Media PCI",
2862 .id_table = snd_cmipci_ids,
2863 .probe = snd_cmipci_probe,
2864 .remove = __devexit_p(snd_cmipci_remove),
2865 };
2866
2867 static int __init alsa_card_cmipci_init(void)
2868 {
2869 return pci_module_init(&driver);
2870 }
2871
2872 static void __exit alsa_card_cmipci_exit(void)
2873 {
2874 pci_unregister_driver(&driver);
2875 }
2876
2877 module_init(alsa_card_cmipci_init)
2878 module_exit(alsa_card_cmipci_exit)
2879
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