1 #ifndef __HAL2_H
2 #define __HAL2_H
3
4 /*
5 * Driver for HAL2 sound processors
6 * Copyright (c) 1999 Ulf Carlsson <ulfc@bun.falkenberg.se>
7 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24 #include <asm/addrspace.h>
25 #include <asm/sgi/hpc3.h>
26 #include <linux/spinlock.h>
27 #include <linux/types.h>
28
29 /* Indirect status register */
30
31 #define H2_ISR_TSTATUS 0x01 /* RO: transaction status 1=busy */
32 #define H2_ISR_USTATUS 0x02 /* RO: utime status bit 1=armed */
33 #define H2_ISR_QUAD_MODE 0x04 /* codec mode 0=indigo 1=quad */
34 #define H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */
35 #define H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */
36
37 /* Revision register */
38
39 #define H2_REV_AUDIO_PRESENT 0x8000 /* RO: audio present 0=present */
40 #define H2_REV_BOARD_M 0x7000 /* RO: bits 14:12, board revision */
41 #define H2_REV_MAJOR_CHIP_M 0x00F0 /* RO: bits 7:4, major chip revision */
42 #define H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */
43
44 /* Indirect address register */
45
46 /*
47 * Address of indirect internal register to be accessed. A write to this
48 * register initiates read or write access to the indirect registers in the
49 * HAL2. Note that there af four indirect data registers for write access to
50 * registers larger than 16 byte.
51 */
52
53 #define H2_IAR_TYPE_M 0xF000 /* bits 15:12, type of functional */
54 /* block the register resides in */
55 /* 1=DMA Port */
56 /* 9=Global DMA Control */
57 /* 2=Bresenham */
58 /* 3=Unix Timer */
59 #define H2_IAR_NUM_M 0x0F00 /* bits 11:8 instance of the */
60 /* blockin which the indirect */
61 /* register resides */
62 /* If IAR_TYPE_M=DMA Port: */
63 /* 1=Synth In */
64 /* 2=AES In */
65 /* 3=AES Out */
66 /* 4=DAC Out */
67 /* 5=ADC Out */
68 /* 6=Synth Control */
69 /* If IAR_TYPE_M=Global DMA Control: */
70 /* 1=Control */
71 /* If IAR_TYPE_M=Bresenham: */
72 /* 1=Bresenham Clock Gen 1 */
73 /* 2=Bresenham Clock Gen 2 */
74 /* 3=Bresenham Clock Gen 3 */
75 /* If IAR_TYPE_M=Unix Timer: */
76 /* 1=Unix Timer */
77 #define H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */
78 #define H2_IAR_PARAM 0x000C /* Parameter Select */
79 #define H2_IAR_RB_INDEX_M 0x0003 /* Read Back Index */
80 /* 00:word0 */
81 /* 01:word1 */
82 /* 10:word2 */
83 /* 11:word3 */
84 /*
85 * HAL2 internal addressing
86 *
87 * The HAL2 has "indirect registers" (idr) which are accessed by writing to the
88 * Indirect Data registers. Write the address to the Indirect Address register
89 * to transfer the data.
90 *
91 * We define the H2IR_* to the read address and H2IW_* to the write address and
92 * H2I_* to be fields in whatever register is referred to.
93 *
94 * When we write to indirect registers which are larger than one word (16 bit)
95 * we have to fill more than one indirect register before writing. When we read
96 * back however we have to read several times, each time with different Read
97 * Back Indexes (there are defs for doing this easily).
98 */
99
100 /*
101 * Relay Control
102 */
103 #define H2I_RELAY_C 0x9100
104 #define H2I_RELAY_C_STATE 0x01 /* state of RELAY pin signal */
105
106 /* DMA port enable */
107
108 #define H2I_DMA_PORT_EN 0x9104
109 #define H2I_DMA_PORT_EN_SY_IN 0x01 /* Synth_in DMA port */
110 #define H2I_DMA_PORT_EN_AESRX 0x02 /* AES receiver DMA port */
111 #define H2I_DMA_PORT_EN_AESTX 0x04 /* AES transmitter DMA port */
112 #define H2I_DMA_PORT_EN_CODECTX 0x08 /* CODEC transmit DMA port */
113 #define H2I_DMA_PORT_EN_CODECR 0x10 /* CODEC receive DMA port */
114
115 #define H2I_DMA_END 0x9108 /* global dma endian select */
116 #define H2I_DMA_END_SY_IN 0x01 /* Synth_in DMA port */
117 #define H2I_DMA_END_AESRX 0x02 /* AES receiver DMA port */
118 #define H2I_DMA_END_AESTX 0x04 /* AES transmitter DMA port */
119 #define H2I_DMA_END_CODECTX 0x08 /* CODEC transmit DMA port */
120 #define H2I_DMA_END_CODECR 0x10 /* CODEC receive DMA port */
121 /* 0=b_end 1=l_end */
122
123 #define H2I_DMA_DRV 0x910C /* global PBUS DMA enable */
124
125 #define H2I_SYNTH_C 0x1104 /* Synth DMA control */
126
127 #define H2I_AESRX_C 0x1204 /* AES RX dma control */
128
129 #define H2I_C_TS_EN 0x20 /* Timestamp enable */
130 #define H2I_C_TS_FRMT 0x40 /* Timestamp format */
131 #define H2I_C_NAUDIO 0x80 /* Sign extend */
132
133 /* AESRX CTL, 16 bit */
134
135 #define H2I_AESTX_C 0x1304 /* AES TX DMA control */
136 #define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
137 #define H2I_AESTX_C_CLKID_M 0x18
138 #define H2I_AESTX_C_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
139 #define H2I_AESTX_C_DATAT_M 0x300
140
141 /* CODEC registers */
142
143 #define H2I_DAC_C1 0x1404 /* DAC DMA control, 16 bit */
144 #define H2I_DAC_C2 0x1408 /* DAC DMA control, 32 bit */
145 #define H2I_ADC_C1 0x1504 /* ADC DMA control, 16 bit */
146 #define H2I_ADC_C2 0x1508 /* ADC DMA control, 32 bit */
147
148 /* Bits in CTL1 register */
149
150 #define H2I_C1_DMA_SHIFT 0 /* DMA channel */
151 #define H2I_C1_DMA_M 0x7
152 #define H2I_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
153 #define H2I_C1_CLKID_M 0x18
154 #define H2I_C1_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
155 #define H2I_C1_DATAT_M 0x300
156
157 /* Bits in CTL2 register */
158
159 #define H2I_C2_R_GAIN_SHIFT 0 /* right a/d input gain */
160 #define H2I_C2_R_GAIN_M 0xf
161 #define H2I_C2_L_GAIN_SHIFT 4 /* left a/d input gain */
162 #define H2I_C2_L_GAIN_M 0xf0
163 #define H2I_C2_R_SEL 0x100 /* right input select */
164 #define H2I_C2_L_SEL 0x200 /* left input select */
165 #define H2I_C2_MUTE 0x400 /* mute */
166 #define H2I_C2_DO1 0x00010000 /* digital output port bit 0 */
167 #define H2I_C2_DO2 0x00020000 /* digital output port bit 1 */
168 #define H2I_C2_R_ATT_SHIFT 18 /* right d/a output - */
169 #define H2I_C2_R_ATT_M 0x007c0000 /* attenuation */
170 #define H2I_C2_L_ATT_SHIFT 23 /* left d/a output - */
171 #define H2I_C2_L_ATT_M 0x0f800000 /* attenuation */
172
173 #define H2I_SYNTH_MAP_C 0x1104 /* synth dma handshake ctrl */
174
175 /* Clock generator CTL 1, 16 bit */
176
177 #define H2I_BRES1_C1 0x2104
178 #define H2I_BRES2_C1 0x2204
179 #define H2I_BRES3_C1 0x2304
180
181 #define H2I_BRES_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */
182 #define H2I_BRES_C1_M 0x03
183
184 /* Clock generator CTL 2, 32 bit */
185
186 #define H2I_BRES1_C2 0x2108
187 #define H2I_BRES2_C2 0x2208
188 #define H2I_BRES3_C2 0x2308
189
190 #define H2I_BRES_C2_INC_SHIFT 0 /* increment value */
191 #define H2I_BRES_C2_INC_M 0xffff
192 #define H2I_BRES_C2_MOD_SHIFT 16 /* modcontrol value */
193 #define H2I_BRES_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
194
195 /* Unix timer, 64 bit */
196
197 #define H2I_UTIME 0x3104
198 #define H2I_UTIME_0_LD 0xffff /* microseconds, LSB's */
199 #define H2I_UTIME_1_LD0 0x0f /* microseconds, MSB's */
200 #define H2I_UTIME_1_LD1 0xf0 /* tenths of microseconds */
201 #define H2I_UTIME_2_LD 0xffff /* seconds, LSB's */
202 #define H2I_UTIME_3_LD 0xffff /* seconds, MSB's */
203
204 struct hal2_ctl_regs {
205 u32 _unused0[4];
206 volatile u32 isr; /* 0x10 Status Register */
207 u32 _unused1[3];
208 volatile u32 rev; /* 0x20 Revision Register */
209 u32 _unused2[3];
210 volatile u32 iar; /* 0x30 Indirect Address Register */
211 u32 _unused3[3];
212 volatile u32 idr0; /* 0x40 Indirect Data Register 0 */
213 u32 _unused4[3];
214 volatile u32 idr1; /* 0x50 Indirect Data Register 1 */
215 u32 _unused5[3];
216 volatile u32 idr2; /* 0x60 Indirect Data Register 2 */
217 u32 _unused6[3];
218 volatile u32 idr3; /* 0x70 Indirect Data Register 3 */
219 };
220
221 struct hal2_aes_regs {
222 volatile u32 rx_stat[2]; /* Status registers */
223 volatile u32 rx_cr[2]; /* Control registers */
224 volatile u32 rx_ud[4]; /* User data window */
225 volatile u32 rx_st[24]; /* Channel status data */
226
227 volatile u32 tx_stat[1]; /* Status register */
228 volatile u32 tx_cr[3]; /* Control registers */
229 volatile u32 tx_ud[4]; /* User data window */
230 volatile u32 tx_st[24]; /* Channel status data */
231 };
232
233 struct hal2_vol_regs {
234 volatile u32 right; /* Right volume */
235 volatile u32 left; /* Left volume */
236 };
237
238 struct hal2_syn_regs {
239 u32 _unused0[2];
240 volatile u32 page; /* DOC Page register */
241 volatile u32 regsel; /* DOC Register selection */
242 volatile u32 dlow; /* DOC Data low */
243 volatile u32 dhigh; /* DOC Data high */
244 volatile u32 irq; /* IRQ Status */
245 volatile u32 dram; /* DRAM Access */
246 };
247
248 #endif /* __HAL2_H */
249
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