1 /*
2 * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 *
21 * NOTE: comments are copy/paste from cwcemb80.lst
22 * provided by Tom Woller at Cirrus (my only
23 * documentation about the SP OS running inside
24 * the DSP)
25 */
26
27 #ifndef __CS46XX_DSP_SCB_TYPES_H__
28 #define __CS46XX_DSP_SCB_TYPES_H__
29
30 #include <asm/byteorder.h>
31
32 #ifndef ___DSP_DUAL_16BIT_ALLOC
33 #if defined(__LITTLE_ENDIAN)
34 #define ___DSP_DUAL_16BIT_ALLOC(a,b) u16 a; u16 b;
35 #elif defined(__BIG_ENDIAN)
36 #define ___DSP_DUAL_16BIT_ALLOC(a,b) u16 b; u16 a;
37 #else
38 #error Not __LITTLE_ENDIAN and not __BIG_ENDIAN, then what ???
39 #endif
40 #endif
41
42 /* This structs are used internally by the SP */
43
44 typedef struct _basic_dma_req_t {
45 /* DMA Requestor Word 0 (DCW) fields:
46
47 31 [30-28]27 [26:24] 23 22 21 20 [19:18] [17:16] 15 14 13 12 11 10 9 8 7 6 [5:0]
48 _______________________________________________________________________________________
49 |S| SBT |D| DBT |wb|wb| | | LS | SS |Opt|Do|SSG|DSG| | | | | | | Dword |
50 |H|_____ |H|_________|S_|D |__|__|______|_______|___|ne|__ |__ |__|__|_|_|_|_|_Count -1|
51 */
52 u32 dcw; /* DMA Control Word */
53 u32 dmw; /* DMA Mode Word */
54 u32 saw; /* Source Address Word */
55 u32 daw; /* Destination Address Word */
56 } basic_dma_req_t;
57
58 typedef struct _scatter_gather_ext_t {
59 u32 npaw; /* Next-Page Address Word */
60
61 /* DMA Requestor Word 5 (NPCW) fields:
62
63 31-30 29 28 [27:16] [15:12] [11:3] [2:0]
64 _________________________________________________________________________________________
65 |SV |LE|SE| Sample-end byte offset | | Page-map entry offset for next | |
66 |page|__|__| ___________________________|_________|__page, if !sample-end___________|____|
67 */
68 u32 npcw; /* Next-Page Control Word */
69 u32 lbaw; /* Loop-Begin Address Word */
70 u32 nplbaw; /* Next-Page after Loop-Begin Address Word */
71 u32 sgaw; /* Scatter/Gather Address Word */
72 } scatter_gather_ext_t;
73
74 typedef struct _volume_control_t {
75 ___DSP_DUAL_16BIT_ALLOC(
76 rightTarg, /* Target volume for left & right channels */
77 leftTarg
78 )
79 ___DSP_DUAL_16BIT_ALLOC(
80 rightVol, /* Current left & right channel volumes */
81 leftVol
82 )
83 } volume_control_t;
84
85 /* Generic stream control block (SCB) structure definition */
86 typedef struct _generic_scb_t {
87 /* For streaming I/O, the DSP should never alter any words in the DMA
88 requestor or the scatter/gather extension. Only ad hoc DMA request
89 streams are free to alter the requestor (currently only occur in the
90 DOS-based MIDI controller and in debugger-inserted code).
91
92 If an SCB does not have any associated DMA requestor, these 9 ints
93 may be freed for use by other tasks, but the pointer to the SCB must
94 still be such that the insOrd:nextSCB appear at offset 9 from the
95 SCB pointer.
96
97 Basic (non scatter/gather) DMA requestor (4 ints)
98 */
99
100 /* Initialized by the host, only modified by DMA
101 R/O for the DSP task */
102 basic_dma_req_t basic_req; /* Optional */
103
104 /* Scatter/gather DMA requestor extension (5 ints)
105 Initialized by the host, only modified by DMA
106 DSP task never needs to even read these.
107 */
108 scatter_gather_ext_t sg_ext; /* Optional */
109
110 /* Sublist pointer & next stream control block (SCB) link.
111 Initialized & modified by the host R/O for the DSP task
112 */
113 ___DSP_DUAL_16BIT_ALLOC(
114 next_scb, /* REQUIRED */
115 sub_list_ptr /* REQUIRED */
116 )
117
118 /* Pointer to this tasks parameter block & stream function pointer
119 Initialized by the host R/O for the DSP task */
120 ___DSP_DUAL_16BIT_ALLOC(
121 entry_point, /* REQUIRED */
122 this_spb /* REQUIRED */
123 )
124
125 /* rsConfig register for stream buffer (rsDMA reg.
126 is loaded from basicReq.daw for incoming streams, or
127 basicReq.saw, for outgoing streams)
128
129 31 30 29 [28:24] [23:16] 15 14 13 12 11 10 9 8 7 6 5 4 [3:0]
130 ______________________________________________________________________________
131 |DMA |D|maxDMAsize| streamNum|dir|p| | | | | | |ds |shr 1|rev Cy | mod |
132 |prio |_|__________|__________|___|_|__|__|__|__|_|_|___|_____|_______|_______|
133 31 30 29 [28:24] [23:16] 15 14 13 12 11 10 9 8 7 6 5 4 [3:0]
134
135
136 Initialized by the host R/O for the DSP task
137 */
138 u32 strm_rs_config; /* REQUIRED */
139 //
140 /* On mixer input streams: indicates mixer input stream configuration
141 On Tees, this is copied from the stream being snooped
142
143 Stream sample pointer & MAC-unit mode for this stream
144
145 Initialized by the host Updated by the DSP task
146 */
147 u32 strm_buf_ptr; /* REQUIRED */
148
149 /* On mixer input streams: points to next mixer input and is updated by the
150 mixer subroutine in the "parent" DSP task
151 (least-significant 16 bits are preserved, unused)
152
153 On Tees, the pointer is copied from the stream being snooped on
154 initialization, and, subsequently, it is copied into the
155 stream being snooped.
156
157 On wavetable/3D voices: the strmBufPtr will use all 32 bits to allow for
158 fractional phase accumulation
159
160 Fractional increment per output sample in the input sample buffer
161
162 (Not used on mixer input streams & redefined on Tees)
163 On wavetable/3D voices: this 32-bit word specifies the integer.fractional
164 increment per output sample.
165 */
166 u32 strmPhiIncr;
167
168
169 /* Standard stereo volume control
170 Initialized by the host (host updates target volumes)
171
172 Current volumes update by the DSP task
173 On mixer input streams: required & updated by the mixer subroutine in the
174 "parent" DSP task
175
176 On Tees, both current & target volumes are copied up on initialization,
177 and, subsequently, the target volume is copied up while the current
178 volume is copied down.
179
180 These two 32-bit words are redefined for wavetable & 3-D voices.
181 */
182 volume_control_t vol_ctrl_t; /* Optional */
183 } generic_scb_t;
184
185
186 typedef struct _spos_control_block_t {
187 /* WARNING: Certain items in this structure are modified by the host
188 Any dword that can be modified by the host, must not be
189 modified by the SP as the host can only do atomic dword
190 writes, and to do otherwise, even a read modify write,
191 may lead to corrupted data on the SP.
192
193 This rule does not apply to one off boot time initialisation prior to starting the SP
194 */
195
196
197 ___DSP_DUAL_16BIT_ALLOC(
198 /* First element on the Hyper forground task tree */
199 hfg_tree_root_ptr, /* HOST */
200 /* First 3 dwords are written by the host and read-only on the DSP */
201 hfg_stack_base /* HOST */
202 )
203
204 ___DSP_DUAL_16BIT_ALLOC(
205 /* Point to this data structure to enable easy access */
206 spos_cb_ptr, /* SP */
207 prev_task_tree_ptr /* SP && HOST */
208 )
209
210 ___DSP_DUAL_16BIT_ALLOC(
211 /* Currently Unused */
212 xxinterval_timer_period,
213 /* Enable extension of SPOS data structure */
214 HFGSPB_ptr
215 )
216
217
218 ___DSP_DUAL_16BIT_ALLOC(
219 xxnum_HFG_ticks_thisInterval,
220 /* Modified by the DSP */
221 xxnum_tntervals
222 )
223
224
225 /* Set by DSP upon encountering a trap (breakpoint) or a spurious
226 interrupt. The host must clear this dword after reading it
227 upon receiving spInt1. */
228 ___DSP_DUAL_16BIT_ALLOC(
229 spurious_int_flag, /* (Host & SP) Nature of the spurious interrupt */
230 trap_flag /* (Host & SP) Nature of detected Trap */
231 )
232
233 ___DSP_DUAL_16BIT_ALLOC(
234 unused2,
235 invalid_IP_flag /* (Host & SP ) Indicate detection of invalid instruction pointer */
236 )
237
238 ___DSP_DUAL_16BIT_ALLOC(
239 /* pointer to forground task tree header for use in next task search */
240 fg_task_tree_hdr_ptr, /* HOST */
241 /* Data structure for controlling synchronous link update */
242 hfg_sync_update_ptr /* HOST */
243 )
244
245 ___DSP_DUAL_16BIT_ALLOC(
246 begin_foreground_FCNT, /* SP */
247 /* Place holder for holding sleep timing */
248 last_FCNT_before_sleep /* SP */
249 )
250
251 ___DSP_DUAL_16BIT_ALLOC(
252 unused7, /* SP */
253 next_task_treePtr /* SP */
254 )
255
256 u32 unused5;
257
258 ___DSP_DUAL_16BIT_ALLOC(
259 active_flags, /* SP */
260 /* State flags, used to assist control of execution of Hyper Forground */
261 HFG_flags /* SP */
262 )
263
264 ___DSP_DUAL_16BIT_ALLOC(
265 unused9,
266 unused8
267 )
268
269 /* Space for saving enough context so that we can set up enough
270 to save some more context.
271 */
272 u32 rFE_save_for_invalid_IP;
273 u32 r32_save_for_spurious_int;
274 u32 r32_save_for_trap;
275 u32 r32_save_for_HFG;
276 } spos_control_block_t;
277
278 /* SPB for MIX_TO_OSTREAM algorithm family */
279 typedef struct _mix2_ostream_spb_t
280 {
281 /* 16b.16b integer.frac approximation to the
282 number of 3 sample triplets to output each
283 frame. (approximation must be floor, to
284 insure that the fractional error is always
285 positive)
286 */
287 u32 outTripletsPerFrame;
288
289 /* 16b.16b integer.frac accumulated number of
290 output triplets since the start of group
291 */
292 u32 accumOutTriplets;
293 } mix2_ostream_spb_t;
294
295 /* SCB for Timing master algorithm */
296 typedef struct _timing_master_scb_t {
297 /* First 12 dwords from generic_scb_t */
298 basic_dma_req_t basic_req; /* Optional */
299 scatter_gather_ext_t sg_ext; /* Optional */
300 ___DSP_DUAL_16BIT_ALLOC(
301 next_scb, /* REQUIRED */
302 sub_list_ptr /* REQUIRED */
303 )
304
305 ___DSP_DUAL_16BIT_ALLOC(
306 entry_point, /* REQUIRED */
307 this_spb /* REQUIRED */
308 )
309
310 ___DSP_DUAL_16BIT_ALLOC(
311 /* Initial values are 0000:xxxx */
312 reserved,
313 extra_sample_accum
314 )
315
316
317 /* Initial values are xxxx:0000
318 hi: Current CODEC output FIFO pointer
319 (0 to 0x0f)
320 lo: Flag indicating that the CODEC
321 FIFO is sync'd (host clears to
322 resynchronize the FIFO pointer
323 upon start/restart)
324 */
325 ___DSP_DUAL_16BIT_ALLOC(
326 codec_FIFO_syncd,
327 codec_FIFO_ptr
328 )
329
330 /* Init. 8000:0005 for 44.1k
331 8000:0001 for 48k
332 hi: Fractional sample accumulator 0.16b
333 lo: Number of frames remaining to be
334 processed in the current group of
335 frames
336 */
337 ___DSP_DUAL_16BIT_ALLOC(
338 frac_samp_accum_qm1,
339 TM_frms_left_in_group
340 )
341
342 /* Init. 0001:0005 for 44.1k
343 0000:0001 for 48k
344 hi: Fractional sample correction factor 0.16b
345 to be added every frameGroupLength frames
346 to correct for truncation error in
347 nsamp_per_frm_q15
348 lo: Number of frames in the group
349 */
350 ___DSP_DUAL_16BIT_ALLOC(
351 frac_samp_correction_qm1,
352 TM_frm_group_length
353 )
354
355 /* Init. 44.1k*65536/8k = 0x00058333 for 44.1k
356 48k*65536/8k = 0x00060000 for 48k
357 16b.16b integer.frac approximation to the
358 number of samples to output each frame.
359 (approximation must be floor, to insure */
360 u32 nsamp_per_frm_q15;
361 } timing_master_scb_t;
362
363 /* SCB for CODEC output algorithm */
364 typedef struct _codec_output_scb_t {
365 /* First 13 dwords from generic_scb_t */
366 basic_dma_req_t basic_req; /* Optional */
367 scatter_gather_ext_t sg_ext; /* Optional */
368 ___DSP_DUAL_16BIT_ALLOC(
369 next_scb, /* REQUIRED */
370 sub_list_ptr /* REQUIRED */
371 )
372
373 ___DSP_DUAL_16BIT_ALLOC(
374 entry_point, /* REQUIRED */
375 this_spb /* REQUIRED */
376 )
377
378 u32 strm_rs_config; /* REQUIRED */
379
380 u32 strm_buf_ptr; /* REQUIRED */
381
382 /* NOTE: The CODEC output task reads samples from the first task on its
383 sublist at the stream buffer pointer (init. to lag DMA destination
384 address word). After the required number of samples is transferred,
385 the CODEC output task advances sub_list_ptr->strm_buf_ptr past the samples
386 consumed.
387 */
388
389 /* Init. 0000:0010 for SDout
390 0060:0010 for SDout2
391 0080:0010 for SDout3
392 hi: Base IO address of FIFO to which
393 the left-channel samples are to
394 be written.
395 lo: Displacement for the base IO
396 address for left-channel to obtain
397 the base IO address for the FIFO
398 to which the right-channel samples
399 are to be written.
400 */
401 ___DSP_DUAL_16BIT_ALLOC(
402 left_chan_base_IO_addr,
403 right_chan_IO_disp
404 )
405
406
407 /* Init: 0x0080:0004 for non-AC-97
408 Init: 0x0080:0000 for AC-97
409 hi: Exponential volume change rate
410 for input stream
411 lo: Positive shift count to shift the
412 16-bit input sample to obtain the
413 32-bit output word
414 */
415 ___DSP_DUAL_16BIT_ALLOC(
416 CO_scale_shift_count,
417 CO_exp_vol_change_rate
418 )
419
420 /* Pointer to SCB at end of input chain */
421 ___DSP_DUAL_16BIT_ALLOC(
422 reserved,
423 last_sub_ptr
424 )
425 } codec_output_scb_t;
426
427 /* SCB for CODEC input algorithm */
428 typedef struct _codec_input_scb_t {
429 /* First 13 dwords from generic_scb_t */
430 basic_dma_req_t basic_req; /* Optional */
431 scatter_gather_ext_t sg_ext; /* Optional */
432 ___DSP_DUAL_16BIT_ALLOC(
433 next_scb, /* REQUIRED */
434 sub_list_ptr /* REQUIRED */
435 )
436
437 ___DSP_DUAL_16BIT_ALLOC(
438 entry_point, /* REQUIRED */
439 this_spb /* REQUIRED */
440 )
441
442 u32 strm_rs_config; /* REQUIRED */
443 u32 strm_buf_ptr; /* REQUIRED */
444
445 /* NOTE: The CODEC input task reads samples from the hardware FIFO
446 sublist at the DMA source address word (sub_list_ptr->basic_req.saw).
447 After the required number of samples is transferred, the CODEC
448 output task advances sub_list_ptr->basic_req.saw past the samples
449 consumed. SPuD must initialize the sub_list_ptr->basic_req.saw
450 to point half-way around from the initial sub_list_ptr->strm_nuf_ptr
451 to allow for lag/lead.
452 */
453
454 /* Init. 0000:0010 for SDout
455 0060:0010 for SDout2
456 0080:0010 for SDout3
457 hi: Base IO address of FIFO to which
458 the left-channel samples are to
459 be written.
460 lo: Displacement for the base IO
461 address for left-channel to obtain
462 the base IO address for the FIFO
463 to which the right-channel samples
464 are to be written.
465 */
466 ___DSP_DUAL_16BIT_ALLOC(
467 rightChanINdisp,
468 left_chan_base_IN_addr
469 )
470 /* Init. ?:fffc
471 lo: Negative shift count to shift the
472 32-bit input dword to obtain the
473 16-bit sample msb-aligned (count
474 is negative to shift left)
475 */
476 ___DSP_DUAL_16BIT_ALLOC(
477 scaleShiftCount,
478 reserver1
479 )
480
481 u32 reserved2;
482 } codec_input_scb_t;
483
484
485 typedef struct _pcm_serial_input_scb_t {
486 /* First 13 dwords from generic_scb_t */
487 basic_dma_req_t basic_req; /* Optional */
488 scatter_gather_ext_t sg_ext; /* Optional */
489 ___DSP_DUAL_16BIT_ALLOC(
490 next_scb, /* REQUIRED */
491 sub_list_ptr /* REQUIRED */
492 )
493
494 ___DSP_DUAL_16BIT_ALLOC(
495 entry_point, /* REQUIRED */
496 this_spb /* REQUIRED */
497 )
498
499 u32 strm_buf_ptr; /* REQUIRED */
500 u32 strm_rs_config; /* REQUIRED */
501
502 /* Init. Ptr to CODEC input SCB
503 hi: Pointer to the SCB containing the
504 input buffer to which CODEC input
505 samples are written
506 lo: Flag indicating the link to the CODEC
507 input task is to be initialized
508 */
509 ___DSP_DUAL_16BIT_ALLOC(
510 init_codec_input_link,
511 codec_input_buf_scb
512 )
513
514 /* Initialized by the host (host updates target volumes) */
515 volume_control_t psi_vol_ctrl;
516
517 } pcm_serial_input_scb_t;
518
519 typedef struct _src_task_scb_t {
520 ___DSP_DUAL_16BIT_ALLOC(
521 frames_left_in_gof,
522 gofs_left_in_sec
523 )
524
525 ___DSP_DUAL_16BIT_ALLOC(
526 const2_thirds,
527 num_extra_tnput_samples
528 )
529
530 ___DSP_DUAL_16BIT_ALLOC(
531 cor_per_gof,
532 correction_per_sec
533 )
534
535 ___DSP_DUAL_16BIT_ALLOC(
536 output_buf_producer_ptr,
537 junk_DMA_MID
538 )
539
540 ___DSP_DUAL_16BIT_ALLOC(
541 gof_length,
542 gofs_per_sec
543 )
544
545 u32 input_buf_strm_config;
546
547 ___DSP_DUAL_16BIT_ALLOC(
548 reserved_for_SRC_use,
549 input_buf_consumer_ptr
550 )
551
552 u32 accum_phi;
553
554 ___DSP_DUAL_16BIT_ALLOC(
555 exp_src_vol_change_rate,
556 input_buf_producer_ptr
557 )
558
559 ___DSP_DUAL_16BIT_ALLOC(
560 src_next_scb,
561 src_sub_list_ptr
562 )
563
564 ___DSP_DUAL_16BIT_ALLOC(
565 src_entry_point,
566 src_this_sbp
567 )
568
569 u32 src_strm_rs_config;
570 u32 src_strm_buf_ptr;
571
572 u32 phiIncr6int_26frac;
573
574 volume_control_t src_vol_ctrl;
575 } src_task_scb_t;
576
577 typedef struct _decimate_by_pow2_scb_t {
578 /* decimationFactor = 2, 4, or 8 (larger factors waste too much memory
579 when compared to cascading decimators)
580 */
581 ___DSP_DUAL_16BIT_ALLOC(
582 dec2_coef_base_ptr,
583 dec2_coef_increment
584 )
585
586 /* coefIncrement = 128 / decimationFactor (for our ROM filter)
587 coefBasePtr = 0x8000 (for our ROM filter)
588 */
589 ___DSP_DUAL_16BIT_ALLOC(
590 dec2_in_samples_per_out_triplet,
591 dec2_extra_in_samples
592 )
593 /* extraInSamples: # of accumulated, unused input samples (init. to 0)
594 inSamplesPerOutTriplet = 3 * decimationFactor
595 */
596
597 ___DSP_DUAL_16BIT_ALLOC(
598 dec2_const2_thirds,
599 dec2_half_num_taps_mp5
600 )
601 /* halfNumTapsM5: (1/2 number of taps in decimation filter) minus 5
602 const2thirds: constant 2/3 in 16Q0 format (sign.15)
603 */
604
605 ___DSP_DUAL_16BIT_ALLOC(
606 dec2_output_buf_producer_ptr,
607 dec2_junkdma_mid
608 )
609
610 u32 dec2_reserved2;
611
612 u32 dec2_input_nuf_strm_config;
613 /* inputBufStrmConfig: rsConfig for the input buffer to the decimator
614 (buffer size = decimationFactor * 32 dwords)
615 */
616
617 ___DSP_DUAL_16BIT_ALLOC(
618 dec2_phi_incr,
619 dec2_input_buf_consumer_ptr
620 )
621 /* inputBufConsumerPtr: Input buffer read pointer (into SRC filter)
622 phiIncr = decimationFactor * 4
623 */
624
625 u32 dec2_reserved3;
626
627 ___DSP_DUAL_16BIT_ALLOC(
628 dec2_exp_vol_change_rate,
629 dec2_input_buf_producer_ptr
630 )
631 /* inputBufProducerPtr: Input buffer write pointer
632 expVolChangeRate: Exponential volume change rate for possible
633 future mixer on input streams
634 */
635
636 ___DSP_DUAL_16BIT_ALLOC(
637 dec2_next_scb,
638 dec2_sub_list_ptr
639 )
640
641 ___DSP_DUAL_16BIT_ALLOC(
642 dec2_entry_point,
643 dec2_this_spb
644 )
645
646 u32 dec2_strm_rs_config;
647 u32 dec2_strm_buf_ptr;
648
649 u32 dec2_reserved4;
650
651 volume_control_t dec2_vol_ctrl; /* Not used! */
652 } decimate_by_pow2_scb_t;
653
654 typedef struct _vari_decimate_scb_t {
655 ___DSP_DUAL_16BIT_ALLOC(
656 vdec_frames_left_in_gof,
657 vdec_gofs_left_in_sec
658 )
659
660 ___DSP_DUAL_16BIT_ALLOC(
661 vdec_const2_thirds,
662 vdec_extra_in_samples
663 )
664 /* extraInSamples: # of accumulated, unused input samples (init. to 0)
665 const2thirds: constant 2/3 in 16Q0 format (sign.15) */
666
667 ___DSP_DUAL_16BIT_ALLOC(
668 vdec_cor_per_gof,
669 vdec_correction_per_sec
670 )
671
672 ___DSP_DUAL_16BIT_ALLOC(
673 vdec_output_buf_producer_ptr,
674 vdec_input_buf_consumer_ptr
675 )
676 /* inputBufConsumerPtr: Input buffer read pointer (into SRC filter) */
677 ___DSP_DUAL_16BIT_ALLOC(
678 vdec_gof_length,
679 vdec_gofs_per_sec
680 )
681
682 u32 vdec_input_buf_strm_config;
683 /* inputBufStrmConfig: rsConfig for the input buffer to the decimator
684 (buffer size = 64 dwords) */
685 u32 vdec_coef_increment;
686 /* coefIncrement = - 128.0 / decimationFactor (as a 32Q15 number) */
687
688 u32 vdec_accumphi;
689 /* accumPhi: accumulated fractional phase increment (6.26) */
690
691 ___DSP_DUAL_16BIT_ALLOC(
692 vdec_exp_vol_change_rate,
693 vdec_input_buf_producer_ptr
694 )
695 /* inputBufProducerPtr: Input buffer write pointer
696 expVolChangeRate: Exponential volume change rate for possible
697 future mixer on input streams */
698
699 ___DSP_DUAL_16BIT_ALLOC(
700 vdec_next_scb,
701 vdec_sub_list_ptr
702 )
703
704 ___DSP_DUAL_16BIT_ALLOC(
705 vdec_entry_point,
706 vdec_this_spb
707 )
708
709 u32 vdec_strm_rs_config;
710 u32 vdec_strm_buf_ptr;
711
712 u32 vdec_phi_incr_6int_26frac;
713
714 volume_control_t vdec_vol_ctrl;
715 } vari_decimate_scb_t;
716
717
718 /* SCB for MIX_TO_OSTREAM algorithm family */
719 typedef struct _mix2_ostream_scb_t {
720 /* First 13 dwords from generic_scb_t */
721 basic_dma_req_t basic_req; /* Optional */
722 scatter_gather_ext_t sg_ext; /* Optional */
723 ___DSP_DUAL_16BIT_ALLOC(
724 next_scb, /* REQUIRED */
725 sub_list_ptr /* REQUIRED */
726 )
727
728 ___DSP_DUAL_16BIT_ALLOC(
729 entry_point, /* REQUIRED */
730 this_spb /* REQUIRED */
731 )
732
733 u32 strm_rs_config; /* REQUIRED */
734 u32 strm_buf_ptr; /* REQUIRED */
735
736
737 /* hi: Number of mixed-down input triplets
738 computed since start of group
739 lo: Number of frames remaining to be
740 processed in the current group of
741 frames
742 */
743 ___DSP_DUAL_16BIT_ALLOC(
744 frames_left_in_group,
745 accum_input_triplets
746 )
747
748 /* hi: Exponential volume change rate
749 for mixer on input streams
750 lo: Number of frames in the group
751 */
752 ___DSP_DUAL_16BIT_ALLOC(
753 frame_group_length,
754 exp_vol_change_rate
755 )
756
757 ___DSP_DUAL_16BIT_ALLOC(
758 const_FFFF,
759 const_zero
760 )
761 } mix2_ostream_scb_t;
762
763
764 /* SCB for S16_MIX algorithm */
765 typedef struct _mix_only_scb_t {
766 /* First 13 dwords from generic_scb_t */
767 basic_dma_req_t basic_req; /* Optional */
768 scatter_gather_ext_t sg_ext; /* Optional */
769 ___DSP_DUAL_16BIT_ALLOC(
770 next_scb, /* REQUIRED */
771 sub_list_ptr /* REQUIRED */
772 )
773
774 ___DSP_DUAL_16BIT_ALLOC(
775 entry_point, /* REQUIRED */
776 this_spb /* REQUIRED */
777 )
778
779 u32 strm_rs_config; /* REQUIRED */
780 u32 strm_buf_ptr; /* REQUIRED */
781
782 u32 reserved;
783 volume_control_t vol_ctrl;
784 } mix_only_scb_t;
785
786 /* SCB for the async. CODEC input algorithm */
787 typedef struct _async_codec_input_scb_t {
788 u32 io_free2;
789
790 u32 io_current_total;
791 u32 io_previous_total;
792
793 u16 io_count;
794 u16 io_count_limit;
795
796 u16 o_fifo_base_addr;
797 u16 ost_mo_format;
798 /* 1 = stereo; 0 = mono
799 xxx for ASER 1 (not allowed); 118 for ASER2 */
800
801 u32 ostrm_rs_config;
802 u32 ostrm_buf_ptr;
803
804 ___DSP_DUAL_16BIT_ALLOC(
805 io_sclks_per_lr_clk,
806 io_io_enable
807 )
808
809 u32 io_free4;
810
811 ___DSP_DUAL_16BIT_ALLOC(
812 io_next_scb,
813 io_sub_list_ptr
814 )
815
816 ___DSP_DUAL_16BIT_ALLOC(
817 io_entry_point,
818 io_this_spb
819 )
820
821 u32 istrm_rs_config;
822 u32 istrm_buf_ptr;
823
824 /* Init. 0000:8042: for ASER1
825 0000:8044: for ASER2 */
826 ___DSP_DUAL_16BIT_ALLOC(
827 io_stat_reg_addr,
828 iofifo_pointer
829 )
830
831 /* Init 1 stero:100 ASER1
832 Init 0 mono:110 ASER2
833 */
834 ___DSP_DUAL_16BIT_ALLOC(
835 ififo_base_addr,
836 ist_mo_format
837 )
838
839 u32 i_free;
840 } async_codec_input_scb_t;
841
842
843 /* SCB for the SP/DIF CODEC input and output */
844 typedef struct _spdifiscb_t {
845 ___DSP_DUAL_16BIT_ALLOC(
846 status_ptr,
847 status_start_ptr
848 )
849
850 u32 current_total;
851 u32 previous_total;
852
853 ___DSP_DUAL_16BIT_ALLOC(
854 count,
855 count_limit
856 )
857
858 u32 status_data;
859
860 ___DSP_DUAL_16BIT_ALLOC(
861 status,
862 free4
863 )
864
865 u32 free3;
866
867 ___DSP_DUAL_16BIT_ALLOC(
868 free2,
869 bit_count
870 )
871
872 u32 temp_status;
873
874 ___DSP_DUAL_16BIT_ALLOC(
875 next_SCB,
876 sub_list_ptr
877 )
878
879 ___DSP_DUAL_16BIT_ALLOC(
880 entry_point,
881 this_spb
882 )
883
884 u32 strm_rs_config;
885 u32 strm_buf_ptr;
886
887 ___DSP_DUAL_16BIT_ALLOC(
888 stat_reg_addr,
889 fifo_pointer
890 )
891
892 ___DSP_DUAL_16BIT_ALLOC(
893 fifo_base_addr,
894 st_mo_format
895 )
896
897 u32 free1;
898 } spdifiscb_t;
899
900
901 /* SCB for the SP/DIF CODEC input and output */
902 typedef struct _spdifoscb_t {
903
904
905 u32 free2;
906
907 u32 free3[4];
908
909 /* Need to be here for compatibility with AsynchFGTxCode */
910 u32 strm_rs_config;
911
912 u32 strm_buf_ptr;
913
914 ___DSP_DUAL_16BIT_ALLOC(
915 status,
916 free5
917 )
918
919 u32 free4;
920
921 ___DSP_DUAL_16BIT_ALLOC(
922 next_scb,
923 sub_list_ptr
924 )
925
926 ___DSP_DUAL_16BIT_ALLOC(
927 entry_point,
928 this_spb
929 )
930
931 u32 free6[2];
932
933 ___DSP_DUAL_16BIT_ALLOC(
934 stat_reg_addr,
935 fifo_pointer
936 )
937
938 ___DSP_DUAL_16BIT_ALLOC(
939 fifo_base_addr,
940 st_mo_format
941 )
942
943 u32 free1;
944 } spdifoscb_t;
945
946
947
948 typedef struct _asynch_fg_rx_scb_t {
949 ___DSP_DUAL_16BIT_ALLOC(
950 bot_buf_mask,
951 buf_Mask
952 )
953
954 ___DSP_DUAL_16BIT_ALLOC(
955 max,
956 min
957 )
958
959 ___DSP_DUAL_16BIT_ALLOC(
960 old_producer_pointer,
961 hfg_scb_ptr
962 )
963
964 ___DSP_DUAL_16BIT_ALLOC(
965 delta,
966 adjust_count
967 )
968
969 u32 unused2[5];
970
971 ___DSP_DUAL_16BIT_ALLOC(
972 sibling_ptr,
973 child_ptr
974 )
975
976 ___DSP_DUAL_16BIT_ALLOC(
977 code_ptr,
978 this_ptr
979 )
980
981 u32 strm_rs_config;
982
983 u32 strm_buf_ptr;
984
985 u32 unused_phi_incr;
986
987 ___DSP_DUAL_16BIT_ALLOC(
988 right_targ,
989 left_targ
990 )
991
992 ___DSP_DUAL_16BIT_ALLOC(
993 right_vol,
994 left_vol
995 )
996 } asynch_fg_rx_scb_t;
997
998
999
1000 typedef struct _asynch_fg_tx_scb_t {
1001 ___DSP_DUAL_16BIT_ALLOC(
1002 not_buf_mask,
1003 buf_mask
1004 )
1005
1006 ___DSP_DUAL_16BIT_ALLOC(
1007 max,
1008 min
1009 )
1010
1011 ___DSP_DUAL_16BIT_ALLOC(
1012 unused1,
1013 hfg_scb_ptr
1014 )
1015
1016 ___DSP_DUAL_16BIT_ALLOC(
1017 delta,
1018 adjust_count
1019 )
1020
1021 u32 accum_phi;
1022
1023 ___DSP_DUAL_16BIT_ALLOC(
1024 unused2,
1025 const_one_third
1026 )
1027
1028 u32 unused3[3];
1029
1030 ___DSP_DUAL_16BIT_ALLOC(
1031 sibling_ptr,
1032 child_ptr
1033 )
1034
1035 ___DSP_DUAL_16BIT_ALLOC(
1036 codePtr,
1037 this_ptr
1038 )
1039
1040 u32 strm_rs_config;
1041
1042 u32 strm_buf_ptr;
1043
1044 u32 phi_incr;
1045
1046 ___DSP_DUAL_16BIT_ALLOC(
1047 unused_right_targ,
1048 unused_left_targ
1049 )
1050
1051 ___DSP_DUAL_16BIT_ALLOC(
1052 unused_right_vol,
1053 unused_left_vol
1054 )
1055 } asynch_fg_tx_scb_t;
1056
1057
1058 typedef struct _output_snoop_scb_t {
1059 /* First 13 dwords from generic_scb_t */
1060 basic_dma_req_t basic_req; /* Optional */
1061 scatter_gather_ext_t sg_ext; /* Optional */
1062 ___DSP_DUAL_16BIT_ALLOC(
1063 next_scb, /* REQUIRED */
1064 sub_list_ptr /* REQUIRED */
1065 )
1066
1067 ___DSP_DUAL_16BIT_ALLOC(
1068 entry_point, /* REQUIRED */
1069 this_spb /* REQUIRED */
1070 )
1071
1072 u32 strm_rs_config; /* REQUIRED */
1073 u32 strm_buf_ptr; /* REQUIRED */
1074
1075 ___DSP_DUAL_16BIT_ALLOC(
1076 init_snoop_input_link,
1077 snoop_child_input_scb
1078 )
1079
1080 u32 snoop_input_buf_ptr;
1081
1082 ___DSP_DUAL_16BIT_ALLOC(
1083 reserved,
1084 input_scb
1085 )
1086 } output_snoop_scb_t;
1087
1088 typedef struct _spio_write_scb_t {
1089 ___DSP_DUAL_16BIT_ALLOC(
1090 address1,
1091 address2
1092 )
1093
1094 u32 data1;
1095
1096 u32 data2;
1097
1098 ___DSP_DUAL_16BIT_ALLOC(
1099 address3,
1100 address4
1101 )
1102
1103 u32 data3;
1104
1105 u32 data4;
1106
1107 ___DSP_DUAL_16BIT_ALLOC(
1108 unused1,
1109 data_ptr
1110 )
1111
1112 u32 unused2[2];
1113
1114 ___DSP_DUAL_16BIT_ALLOC(
1115 sibling_ptr,
1116 child_ptr
1117 )
1118
1119 ___DSP_DUAL_16BIT_ALLOC(
1120 entry_point,
1121 this_ptr
1122 )
1123
1124 u32 unused3[5];
1125 } spio_write_scb_t;
1126
1127 typedef struct _magic_snoop_task_t {
1128 u32 i0;
1129 u32 i1;
1130
1131 u32 strm_buf_ptr1;
1132
1133 u16 i2;
1134 u16 snoop_scb;
1135
1136 u32 i3;
1137 u32 i4;
1138 u32 i5;
1139 u32 i6;
1140
1141 u32 i7;
1142
1143 ___DSP_DUAL_16BIT_ALLOC(
1144 next_scb,
1145 sub_list_ptr
1146 )
1147
1148 ___DSP_DUAL_16BIT_ALLOC(
1149 entry_point,
1150 this_ptr
1151 )
1152
1153 u32 strm_buf_config;
1154 u32 strm_buf_ptr2;
1155
1156 u32 i8;
1157
1158 volume_control_t vdec_vol_ctrl;
1159 } magic_snoop_task_t;
1160
1161
1162 typedef struct _filter_scb_t {
1163 ___DSP_DUAL_16BIT_ALLOC(
1164 a0_right, /* 0x00 */
1165 a0_left
1166 )
1167 ___DSP_DUAL_16BIT_ALLOC(
1168 a1_right, /* 0x01 */
1169 a1_left
1170 )
1171 ___DSP_DUAL_16BIT_ALLOC(
1172 a2_right, /* 0x02 */
1173 a2_left
1174 )
1175 ___DSP_DUAL_16BIT_ALLOC(
1176 output_buf_ptr, /* 0x03 */
1177 init
1178 )
1179
1180 ___DSP_DUAL_16BIT_ALLOC(
1181 filter_unused3, /* 0x04 */
1182 filter_unused2
1183 )
1184
1185 u32 prev_sample_output1; /* 0x05 */
1186 u32 prev_sample_output2; /* 0x06 */
1187 u32 prev_sample_input1; /* 0x07 */
1188 u32 prev_sample_input2; /* 0x08 */
1189
1190 ___DSP_DUAL_16BIT_ALLOC(
1191 next_scb_ptr, /* 0x09 */
1192 sub_list_ptr
1193 )
1194
1195 ___DSP_DUAL_16BIT_ALLOC(
1196 entry_point, /* 0x0A */
1197 spb_ptr
1198 )
1199
1200 u32 strm_rs_config; /* 0x0B */
1201 u32 strm_buf_ptr; /* 0x0C */
1202
1203 ___DSP_DUAL_16BIT_ALLOC(
1204 b0_right, /* 0x0D */
1205 b0_left
1206 )
1207 ___DSP_DUAL_16BIT_ALLOC(
1208 b1_right, /* 0x0E */
1209 b1_left
1210 )
1211 ___DSP_DUAL_16BIT_ALLOC(
1212 b2_right, /* 0x0F */
1213 b2_left
1214 )
1215 } filter_scb_t;
1216 #endif /* __DSP_SCB_TYPES_H__ */
1217
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