1 /*
2 * SuperH FLCTL nand controller
3 *
4 * Copyright © 2008 Renesas Solutions Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20 #ifndef __SH_FLCTL_H__
21 #define __SH_FLCTL_H__
22
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/nand.h>
25 #include <linux/mtd/partitions.h>
26
27 /* FLCTL registers */
28 #define FLCMNCR(f) (f->reg + 0x0)
29 #define FLCMDCR(f) (f->reg + 0x4)
30 #define FLCMCDR(f) (f->reg + 0x8)
31 #define FLADR(f) (f->reg + 0xC)
32 #define FLADR2(f) (f->reg + 0x3C)
33 #define FLDATAR(f) (f->reg + 0x10)
34 #define FLDTCNTR(f) (f->reg + 0x14)
35 #define FLINTDMACR(f) (f->reg + 0x18)
36 #define FLBSYTMR(f) (f->reg + 0x1C)
37 #define FLBSYCNT(f) (f->reg + 0x20)
38 #define FLDTFIFO(f) (f->reg + 0x24)
39 #define FLECFIFO(f) (f->reg + 0x28)
40 #define FLTRCR(f) (f->reg + 0x2C)
41 #define FL4ECCRESULT0(f) (f->reg + 0x80)
42 #define FL4ECCRESULT1(f) (f->reg + 0x84)
43 #define FL4ECCRESULT2(f) (f->reg + 0x88)
44 #define FL4ECCRESULT3(f) (f->reg + 0x8C)
45 #define FL4ECCCR(f) (f->reg + 0x90)
46 #define FL4ECCCNT(f) (f->reg + 0x94)
47 #define FLERRADR(f) (f->reg + 0x98)
48
49 /* FLCMNCR control bits */
50 #define ECCPOS2 (0x1 << 25)
51 #define _4ECCCNTEN (0x1 << 24)
52 #define _4ECCEN (0x1 << 23)
53 #define _4ECCCORRECT (0x1 << 22)
54 #define SNAND_E (0x1 << 18) /* SNAND (0=512 1=2048)*/
55 #define QTSEL_E (0x1 << 17)
56 #define ENDIAN (0x1 << 16) /* 1 = little endian */
57 #define FCKSEL_E (0x1 << 15)
58 #define ECCPOS_00 (0x00 << 12)
59 #define ECCPOS_01 (0x01 << 12)
60 #define ECCPOS_02 (0x02 << 12)
61 #define ACM_SACCES_MODE (0x01 << 10)
62 #define NANWF_E (0x1 << 9)
63 #define SE_D (0x1 << 8) /* Spare area disable */
64 #define CE1_ENABLE (0x1 << 4) /* Chip Enable 1 */
65 #define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */
66 #define TYPESEL_SET (0x1 << 0)
67
68 /* FLCMDCR control bits */
69 #define ADRCNT2_E (0x1 << 31) /* 5byte address enable */
70 #define ADRMD_E (0x1 << 26) /* Sector address access */
71 #define CDSRC_E (0x1 << 25) /* Data buffer selection */
72 #define DOSR_E (0x1 << 24) /* Status read check */
73 #define SELRW (0x1 << 21) /* 0:read 1:write */
74 #define DOADR_E (0x1 << 20) /* Address stage execute */
75 #define ADRCNT_1 (0x00 << 18) /* Address data bytes: 1byte */
76 #define ADRCNT_2 (0x01 << 18) /* Address data bytes: 2byte */
77 #define ADRCNT_3 (0x02 << 18) /* Address data bytes: 3byte */
78 #define ADRCNT_4 (0x03 << 18) /* Address data bytes: 4byte */
79 #define DOCMD2_E (0x1 << 17) /* 2nd cmd stage execute */
80 #define DOCMD1_E (0x1 << 16) /* 1st cmd stage execute */
81
82 /* FLTRCR control bits */
83 #define TRSTRT (0x1 << 0) /* translation start */
84 #define TREND (0x1 << 1) /* translation end */
85
86 /* FL4ECCCR control bits */
87 #define _4ECCFA (0x1 << 2) /* 4 symbols correct fault */
88 #define _4ECCEND (0x1 << 1) /* 4 symbols end */
89 #define _4ECCEXST (0x1 << 0) /* 4 symbols exist */
90
91 #define INIT_FL4ECCRESULT_VAL 0x03FF03FF
92 #define LOOP_TIMEOUT_MAX 0x00010000
93
94 #define mtd_to_flctl(mtd) container_of(mtd, struct sh_flctl, mtd)
95
96 struct sh_flctl {
97 struct mtd_info mtd;
98 struct nand_chip chip;
99 void __iomem *reg;
100
101 uint8_t done_buff[2048 + 64]; /* max size 2048 + 64 */
102 int read_bytes;
103 int index;
104 int seqin_column; /* column in SEQIN cmd */
105 int seqin_page_addr; /* page_addr in SEQIN cmd */
106 uint32_t seqin_read_cmd; /* read cmd in SEQIN cmd */
107 int erase1_page_addr; /* page_addr in ERASE1 cmd */
108 uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */
109 uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */
110
111 int hwecc_cant_correct[4];
112
113 unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */
114 unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */
115 };
116
117 struct sh_flctl_platform_data {
118 struct mtd_partition *parts;
119 int nr_parts;
120 unsigned long flcmncr_val;
121
122 unsigned has_hwecc:1;
123 };
124
125 #endif /* __SH_FLCTL_H__ */
126
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