1 #ifndef _AM_X86_MPSPEC_H
2 #define _AM_X86_MPSPEC_H
3
4 #include <asm/mpspec_def.h>
5
6 #ifdef CONFIG_X86_32
7 #include <mach_mpspec.h>
8
9 extern int mp_bus_id_to_type[MAX_MP_BUSSES];
10 extern int mp_bus_id_to_node[MAX_MP_BUSSES];
11 extern int mp_bus_id_to_local[MAX_MP_BUSSES];
12 extern int quad_local_to_mp_bus_id[NR_CPUS/4][4];
13
14 extern unsigned int def_to_bigsmp;
15 extern int apic_version[MAX_APICS];
16 extern u8 apicid_2_node[];
17 extern int pic_mode;
18
19 #define MAX_APICID 256
20
21 #else
22
23 #define MAX_MP_BUSSES 256
24 /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
25 #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
26
27 extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
28
29 #endif
30
31 extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES];
32
33 extern unsigned int boot_cpu_physical_apicid;
34 extern int smp_found_config;
35 extern int nr_ioapics;
36 extern int mp_irq_entries;
37 extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
38 extern int mpc_default_type;
39 extern unsigned long mp_lapic_addr;
40
41 extern void find_smp_config(void);
42 extern void get_smp_config(void);
43
44 #ifdef CONFIG_ACPI
45 extern void mp_register_lapic(u8 id, u8 enabled);
46 extern void mp_register_lapic_address(u64 address);
47 extern void mp_register_ioapic(u8 id, u32 address, u32 gsi_base);
48 extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
49 u32 gsi);
50 extern void mp_config_acpi_legacy_irqs(void);
51 extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low);
52 #endif /* CONFIG_ACPI */
53
54 #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
55
56 struct physid_mask
57 {
58 unsigned long mask[PHYSID_ARRAY_SIZE];
59 };
60
61 typedef struct physid_mask physid_mask_t;
62
63 #define physid_set(physid, map) set_bit(physid, (map).mask)
64 #define physid_clear(physid, map) clear_bit(physid, (map).mask)
65 #define physid_isset(physid, map) test_bit(physid, (map).mask)
66 #define physid_test_and_set(physid, map) \
67 test_and_set_bit(physid, (map).mask)
68
69 #define physids_and(dst, src1, src2) \
70 bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
71
72 #define physids_or(dst, src1, src2) \
73 bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
74
75 #define physids_clear(map) \
76 bitmap_zero((map).mask, MAX_APICS)
77
78 #define physids_complement(dst, src) \
79 bitmap_complement((dst).mask, (src).mask, MAX_APICS)
80
81 #define physids_empty(map) \
82 bitmap_empty((map).mask, MAX_APICS)
83
84 #define physids_equal(map1, map2) \
85 bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
86
87 #define physids_weight(map) \
88 bitmap_weight((map).mask, MAX_APICS)
89
90 #define physids_shift_right(d, s, n) \
91 bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
92
93 #define physids_shift_left(d, s, n) \
94 bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
95
96 #define physids_coerce(map) ((map).mask[0])
97
98 #define physids_promote(physids) \
99 ({ \
100 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
101 __physid_mask.mask[0] = physids; \
102 __physid_mask; \
103 })
104
105 #define physid_mask_of_physid(physid) \
106 ({ \
107 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
108 physid_set(physid, __physid_mask); \
109 __physid_mask; \
110 })
111
112 #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
113 #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
114
115 extern physid_mask_t phys_cpu_present_map;
116
117 #endif
118
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