1 /* linux/include/asm-arm/plat-s3c/uncompress.h
2 *
3 * Copyright 2003, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C - uncompress code
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #ifndef __ASM_PLAT_UNCOMPRESS_H
15 #define __ASM_PLAT_UNCOMPRESS_H
16
17 typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
18
19 /* uart setup */
20
21 static unsigned int fifo_mask;
22 static unsigned int fifo_max;
23
24 /* forward declerations */
25
26 static void arch_detect_cpu(void);
27
28 /* defines for UART registers */
29
30 #include <asm/plat-s3c/regs-serial.h>
31 #include <asm/plat-s3c/regs-watchdog.h>
32
33 /* working in physical space... */
34 #undef S3C2410_WDOGREG
35 #define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
36
37 /* how many bytes we allow into the FIFO at a time in FIFO mode */
38 #define FIFO_MAX (14)
39
40 #define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
41
42 static __inline__ void
43 uart_wr(unsigned int reg, unsigned int val)
44 {
45 volatile unsigned int *ptr;
46
47 ptr = (volatile unsigned int *)(reg + uart_base);
48 *ptr = val;
49 }
50
51 static __inline__ unsigned int
52 uart_rd(unsigned int reg)
53 {
54 volatile unsigned int *ptr;
55
56 ptr = (volatile unsigned int *)(reg + uart_base);
57 return *ptr;
58 }
59
60 /* we can deal with the case the UARTs are being run
61 * in FIFO mode, so that we don't hold up our execution
62 * waiting for tx to happen...
63 */
64
65 static void putc(int ch)
66 {
67 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
68 int level;
69
70 while (1) {
71 level = uart_rd(S3C2410_UFSTAT);
72 level &= fifo_mask;
73
74 if (level < fifo_max)
75 break;
76 }
77
78 } else {
79 /* not using fifos */
80
81 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
82 barrier();
83 }
84
85 /* write byte to transmission register */
86 uart_wr(S3C2410_UTXH, ch);
87 }
88
89 static inline void flush(void)
90 {
91 }
92
93 #define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
94
95 /* CONFIG_S3C_BOOT_WATCHDOG
96 *
97 * Simple boot-time watchdog setup, to reboot the system if there is
98 * any problem with the boot process
99 */
100
101 #ifdef CONFIG_S3C_BOOT_WATCHDOG
102
103 #define WDOG_COUNT (0xff00)
104
105 static inline void arch_decomp_wdog(void)
106 {
107 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
108 }
109
110 static void arch_decomp_wdog_start(void)
111 {
112 __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
113 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
114 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
115 }
116
117 #else
118 #define arch_decomp_wdog_start()
119 #define arch_decomp_wdog()
120 #endif
121
122 #ifdef CONFIG_S3C_BOOT_ERROR_RESET
123
124 static void arch_decomp_error(const char *x)
125 {
126 putstr("\n\n");
127 putstr(x);
128 putstr("\n\n -- System resetting\n");
129
130 __raw_writel(0x4000, S3C2410_WTDAT);
131 __raw_writel(0x4000, S3C2410_WTCNT);
132 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
133
134 while(1);
135 }
136
137 #define arch_error arch_decomp_error
138 #endif
139
140 static void error(char *err);
141
142 static void
143 arch_decomp_setup(void)
144 {
145 /* we may need to setup the uart(s) here if we are not running
146 * on an BAST... the BAST will have left the uarts configured
147 * after calling linux.
148 */
149
150 arch_detect_cpu();
151 arch_decomp_wdog_start();
152 }
153
154
155 #endif /* __ASM_PLAT_UNCOMPRESS_H */
156
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