1 /*
2 * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h
3 *
4 * PXA3xx specific register definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #ifndef __ASM_ARCH_PXA3XX_REGS_H
14 #define __ASM_ARCH_PXA3XX_REGS_H
15 /*
16 * Service Power Management Unit (MPMU)
17 */
18 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */
19 #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
20 #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
21 #define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
22 #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
23 #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
24 #define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
25 #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
26 #define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
27 #define PCMD(x) __REG(0x40F50110 + ((x) << 2))
28
29 /*
30 * Slave Power Managment Unit
31 */
32 #define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */
33 #define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */
34 #define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */
35 #define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */
36 #define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */
37 #define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */
38 #define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */
39 #define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */
40 #define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */
41 #define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */
42 #define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */
43 #define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */
44 #define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */
45 #define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */
46
47 /*
48 * Application Subsystem Configuration bits.
49 */
50 #define ASCR_RDH (1 << 31)
51 #define ASCR_D1S (1 << 2)
52 #define ASCR_D2S (1 << 1)
53 #define ASCR_D3S (1 << 0)
54
55 /*
56 * Application Reset Status bits.
57 */
58 #define ARSR_GPR (1 << 3)
59 #define ARSR_LPMR (1 << 2)
60 #define ARSR_WDT (1 << 1)
61 #define ARSR_HWR (1 << 0)
62
63 /*
64 * Application Subsystem Wake-Up bits.
65 */
66 #define ADXER_WRTC (1 << 31) /* RTC */
67 #define ADXER_WOST (1 << 30) /* OS Timer */
68 #define ADXER_WTSI (1 << 29) /* Touchscreen */
69 #define ADXER_WUSBH (1 << 28) /* USB host */
70 #define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */
71 #define ADXER_WMSL0 (1 << 24) /* MSL port 0*/
72 #define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */
73 #define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */
74 #define ADXER_WKP (1 << 21) /* Keypad */
75 #define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */
76 #define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */
77 #define ADXER_WOTG (1 << 16) /* USBOTG input */
78 #define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */
79 #define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */
80 #define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */
81 #define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */
82 #define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */
83 #define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */
84 #define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */
85 #define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */
86 #define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */
87 #define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */
88 #define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */
89 #define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */
90 #define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */
91 #define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */
92 #define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */
93 #define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */
94
95 /*
96 * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320.
97 */
98 #define ADXR_L2 (1 << 8)
99 #define ADXR_R5 (1 << 5)
100 #define ADXR_R4 (1 << 4)
101 #define ADXR_R3 (1 << 3)
102 #define ADXR_R2 (1 << 2)
103 #define ADXR_R1 (1 << 1)
104 #define ADXR_R0 (1 << 0)
105
106 /*
107 * Values for PWRMODE CP15 register
108 */
109 #define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */
110 #define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */
111 #define PXA3xx_PM_S0D2C2 0x03 /* aka standby */
112 #define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */
113 #define PXA3xx_PM_S0D0C1 0x01
114
115 /*
116 * Application Subsystem Clock
117 */
118 #define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
119 #define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
120 #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
121 #define CKENA __REG(0x4134000C) /* A Clock Enable Register */
122 #define CKENB __REG(0x41340010) /* B Clock Enable Register */
123 #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
124
125 /*
126 * Clock Enable Bit
127 */
128 #define CKEN_LCD 1 /* < LCD Clock Enable */
129 #define CKEN_USBH 2 /* < USB host clock enable */
130 #define CKEN_CAMERA 3 /* < Camera interface clock enable */
131 #define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */
132 #define CKEN_USB2 6 /* < USB 2.0 client clock enable. */
133 #define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */
134 #define CKEN_SMC 9 /* < Static Memory Controller clock enable */
135 #define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */
136 #define CKEN_BOOT 11 /* < Boot rom clock enable */
137 #define CKEN_MMC1 12 /* < MMC1 Clock enable */
138 #define CKEN_MMC2 13 /* < MMC2 clock enable */
139 #define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */
140 #define CKEN_CIR 15 /* < Consumer IR Clock Enable */
141 #define CKEN_USIM0 17 /* < USIM[0] Clock Enable */
142 #define CKEN_USIM1 18 /* < USIM[1] Clock Enable */
143 #define CKEN_TPM 19 /* < TPM clock enable */
144 #define CKEN_UDC 20 /* < UDC clock enable */
145 #define CKEN_BTUART 21 /* < BTUART clock enable */
146 #define CKEN_FFUART 22 /* < FFUART clock enable */
147 #define CKEN_STUART 23 /* < STUART clock enable */
148 #define CKEN_AC97 24 /* < AC97 clock enable */
149 #define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */
150 #define CKEN_SSP1 26 /* < SSP1 clock enable */
151 #define CKEN_SSP2 27 /* < SSP2 clock enable */
152 #define CKEN_SSP3 28 /* < SSP3 clock enable */
153 #define CKEN_SSP4 29 /* < SSP4 clock enable */
154 #define CKEN_MSL0 30 /* < MSL0 clock enable */
155 #define CKEN_PWM0 32 /* < PWM[0] clock enable */
156 #define CKEN_PWM1 33 /* < PWM[1] clock enable */
157 #define CKEN_I2C 36 /* < I2C clock enable */
158 #define CKEN_INTC 38 /* < Interrupt controller clock enable */
159 #define CKEN_GPIO 39 /* < GPIO clock enable */
160 #define CKEN_1WIRE 40 /* < 1-wire clock enable */
161 #define CKEN_HSIO2 41 /* < HSIO2 clock enable */
162 #define CKEN_MINI_IM 48 /* < Mini-IM */
163 #define CKEN_MINI_LCD 49 /* < Mini LCD */
164
165 #if defined(CONFIG_CPU_PXA310)
166 #define CKEN_MMC3 5 /* < MMC3 Clock Enable */
167 #define CKEN_MVED 43 /* < MVED clock enable */
168 #endif
169
170 /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
171 #define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */
172 #define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */
173
174 #endif /* __ASM_ARCH_PXA3XX_REGS_H */
175
|
This page was automatically generated by the
LXR engine.
|