1 /* linux/include/asm-arm/arch-msm/irqs.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17 #ifndef __ASM_ARCH_MSM_IRQS_H
18
19 /* MSM ARM11 Interrupt Numbers */
20 /* See 80-VE113-1 A, pp219-221 */
21
22 #define INT_A9_M2A_0 0
23 #define INT_A9_M2A_1 1
24 #define INT_A9_M2A_2 2
25 #define INT_A9_M2A_3 3
26 #define INT_A9_M2A_4 4
27 #define INT_A9_M2A_5 5
28 #define INT_A9_M2A_6 6
29 #define INT_GP_TIMER_EXP 7
30 #define INT_DEBUG_TIMER_EXP 8
31 #define INT_UART1 9
32 #define INT_UART2 10
33 #define INT_UART3 11
34 #define INT_UART1_RX 12
35 #define INT_UART2_RX 13
36 #define INT_UART3_RX 14
37 #define INT_USB_OTG 15
38 #define INT_MDDI_PRI 16
39 #define INT_MDDI_EXT 17
40 #define INT_MDDI_CLIENT 18
41 #define INT_MDP 19
42 #define INT_GRAPHICS 20
43 #define INT_ADM_AARM 21
44 #define INT_ADSP_A11 22
45 #define INT_ADSP_A9_A11 23
46 #define INT_SDC1_0 24
47 #define INT_SDC1_1 25
48 #define INT_SDC2_0 26
49 #define INT_SDC2_1 27
50 #define INT_KEYSENSE 28
51 #define INT_TCHSCRN_SSBI 29
52 #define INT_TCHSCRN1 30
53 #define INT_TCHSCRN2 31
54
55 #define INT_GPIO_GROUP1 (32 + 0)
56 #define INT_GPIO_GROUP2 (32 + 1)
57 #define INT_PWB_I2C (32 + 2)
58 #define INT_SOFTRESET (32 + 3)
59 #define INT_NAND_WR_ER_DONE (32 + 4)
60 #define INT_NAND_OP_DONE (32 + 5)
61 #define INT_PBUS_ARM11 (32 + 6)
62 #define INT_AXI_MPU_SMI (32 + 7)
63 #define INT_AXI_MPU_EBI1 (32 + 8)
64 #define INT_AD_HSSD (32 + 9)
65 #define INT_ARM11_PMU (32 + 10)
66 #define INT_ARM11_DMA (32 + 11)
67 #define INT_TSIF_IRQ (32 + 12)
68 #define INT_UART1DM_IRQ (32 + 13)
69 #define INT_UART1DM_RX (32 + 14)
70 #define INT_USB_HS (32 + 15)
71 #define INT_SDC3_0 (32 + 16)
72 #define INT_SDC3_1 (32 + 17)
73 #define INT_SDC4_0 (32 + 18)
74 #define INT_SDC4_1 (32 + 19)
75 #define INT_UART2DM_RX (32 + 20)
76 #define INT_UART2DM_IRQ (32 + 21)
77
78 /* 22-31 are reserved */
79
80 #define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
81
82 #define NR_MSM_IRQS 64
83 #define NR_GPIO_IRQS 122
84 #define NR_BOARD_IRQS 64
85 #define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
86
87 #define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
88
89 #endif
90
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