1 /*
2 * w1_io.c
3 *
4 * Copyright (c) 2004 Evgeniy Polyakov <johnpol@2ka.mipt.ru>
5 *
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #include <asm/io.h>
23
24 #include <linux/delay.h>
25 #include <linux/moduleparam.h>
26 #include <linux/module.h>
27
28 #include "w1.h"
29 #include "w1_log.h"
30
31 static int w1_delay_parm = 1;
32 module_param_named(delay_coef, w1_delay_parm, int, 0);
33
34 static u8 w1_crc8_table[] = {
35 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65,
36 157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220,
37 35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98,
38 190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255,
39 70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7,
40 219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154,
41 101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36,
42 248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185,
43 140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205,
44 17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80,
45 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238,
46 50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45, 115,
47 202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139,
48 87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22,
49 233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168,
50 116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53
51 };
52
53 static void w1_delay(unsigned long tm)
54 {
55 udelay(tm * w1_delay_parm);
56 }
57
58 static void w1_write_bit(struct w1_master *dev, int bit);
59 static u8 w1_read_bit(struct w1_master *dev);
60
61 /**
62 * Generates a write-0 or write-1 cycle and samples the level.
63 */
64 static u8 w1_touch_bit(struct w1_master *dev, int bit)
65 {
66 if (dev->bus_master->touch_bit)
67 return dev->bus_master->touch_bit(dev->bus_master->data, bit);
68 else if (bit)
69 return w1_read_bit(dev);
70 else {
71 w1_write_bit(dev, 0);
72 return 0;
73 }
74 }
75
76 /**
77 * Generates a write-0 or write-1 cycle.
78 * Only call if dev->bus_master->touch_bit is NULL
79 */
80 static void w1_write_bit(struct w1_master *dev, int bit)
81 {
82 if (bit) {
83 dev->bus_master->write_bit(dev->bus_master->data, 0);
84 w1_delay(6);
85 dev->bus_master->write_bit(dev->bus_master->data, 1);
86 w1_delay(64);
87 } else {
88 dev->bus_master->write_bit(dev->bus_master->data, 0);
89 w1_delay(60);
90 dev->bus_master->write_bit(dev->bus_master->data, 1);
91 w1_delay(10);
92 }
93 }
94
95 /**
96 * Pre-write operation, currently only supporting strong pullups.
97 * Program the hardware for a strong pullup, if one has been requested and
98 * the hardware supports it.
99 *
100 * @param dev the master device
101 */
102 static void w1_pre_write(struct w1_master *dev)
103 {
104 if (dev->pullup_duration &&
105 dev->enable_pullup && dev->bus_master->set_pullup) {
106 dev->bus_master->set_pullup(dev->bus_master->data,
107 dev->pullup_duration);
108 }
109 }
110
111 /**
112 * Post-write operation, currently only supporting strong pullups.
113 * If a strong pullup was requested, clear it if the hardware supports
114 * them, or execute the delay otherwise, in either case clear the request.
115 *
116 * @param dev the master device
117 */
118 static void w1_post_write(struct w1_master *dev)
119 {
120 if (dev->pullup_duration) {
121 if (dev->enable_pullup && dev->bus_master->set_pullup)
122 dev->bus_master->set_pullup(dev->bus_master->data, 0);
123 else
124 msleep(dev->pullup_duration);
125 dev->pullup_duration = 0;
126 }
127 }
128
129 /**
130 * Writes 8 bits.
131 *
132 * @param dev the master device
133 * @param byte the byte to write
134 */
135 void w1_write_8(struct w1_master *dev, u8 byte)
136 {
137 int i;
138
139 if (dev->bus_master->write_byte) {
140 w1_pre_write(dev);
141 dev->bus_master->write_byte(dev->bus_master->data, byte);
142 }
143 else
144 for (i = 0; i < 8; ++i) {
145 if (i == 7)
146 w1_pre_write(dev);
147 w1_touch_bit(dev, (byte >> i) & 0x1);
148 }
149 w1_post_write(dev);
150 }
151 EXPORT_SYMBOL_GPL(w1_write_8);
152
153
154 /**
155 * Generates a write-1 cycle and samples the level.
156 * Only call if dev->bus_master->touch_bit is NULL
157 */
158 static u8 w1_read_bit(struct w1_master *dev)
159 {
160 int result;
161
162 dev->bus_master->write_bit(dev->bus_master->data, 0);
163 w1_delay(6);
164 dev->bus_master->write_bit(dev->bus_master->data, 1);
165 w1_delay(9);
166
167 result = dev->bus_master->read_bit(dev->bus_master->data);
168 w1_delay(55);
169
170 return result & 0x1;
171 }
172
173 /**
174 * Does a triplet - used for searching ROM addresses.
175 * Return bits:
176 * bit 0 = id_bit
177 * bit 1 = comp_bit
178 * bit 2 = dir_taken
179 * If both bits 0 & 1 are set, the search should be restarted.
180 *
181 * @param dev the master device
182 * @param bdir the bit to write if both id_bit and comp_bit are 0
183 * @return bit fields - see above
184 */
185 u8 w1_triplet(struct w1_master *dev, int bdir)
186 {
187 if (dev->bus_master->triplet)
188 return dev->bus_master->triplet(dev->bus_master->data, bdir);
189 else {
190 u8 id_bit = w1_touch_bit(dev, 1);
191 u8 comp_bit = w1_touch_bit(dev, 1);
192 u8 retval;
193
194 if (id_bit && comp_bit)
195 return 0x03; /* error */
196
197 if (!id_bit && !comp_bit) {
198 /* Both bits are valid, take the direction given */
199 retval = bdir ? 0x04 : 0;
200 } else {
201 /* Only one bit is valid, take that direction */
202 bdir = id_bit;
203 retval = id_bit ? 0x05 : 0x02;
204 }
205
206 if (dev->bus_master->touch_bit)
207 w1_touch_bit(dev, bdir);
208 else
209 w1_write_bit(dev, bdir);
210 return retval;
211 }
212 }
213
214 /**
215 * Reads 8 bits.
216 *
217 * @param dev the master device
218 * @return the byte read
219 */
220 u8 w1_read_8(struct w1_master *dev)
221 {
222 int i;
223 u8 res = 0;
224
225 if (dev->bus_master->read_byte)
226 res = dev->bus_master->read_byte(dev->bus_master->data);
227 else
228 for (i = 0; i < 8; ++i)
229 res |= (w1_touch_bit(dev,1) << i);
230
231 return res;
232 }
233 EXPORT_SYMBOL_GPL(w1_read_8);
234
235 /**
236 * Writes a series of bytes.
237 *
238 * @param dev the master device
239 * @param buf pointer to the data to write
240 * @param len the number of bytes to write
241 */
242 void w1_write_block(struct w1_master *dev, const u8 *buf, int len)
243 {
244 int i;
245
246 if (dev->bus_master->write_block) {
247 w1_pre_write(dev);
248 dev->bus_master->write_block(dev->bus_master->data, buf, len);
249 }
250 else
251 for (i = 0; i < len; ++i)
252 w1_write_8(dev, buf[i]); /* calls w1_pre_write */
253 w1_post_write(dev);
254 }
255 EXPORT_SYMBOL_GPL(w1_write_block);
256
257 /**
258 * Touches a series of bytes.
259 *
260 * @param dev the master device
261 * @param buf pointer to the data to write
262 * @param len the number of bytes to write
263 */
264 void w1_touch_block(struct w1_master *dev, u8 *buf, int len)
265 {
266 int i, j;
267 u8 tmp;
268
269 for (i = 0; i < len; ++i) {
270 tmp = 0;
271 for (j = 0; j < 8; ++j) {
272 if (j == 7)
273 w1_pre_write(dev);
274 tmp |= w1_touch_bit(dev, (buf[i] >> j) & 0x1) << j;
275 }
276
277 buf[i] = tmp;
278 }
279 }
280 EXPORT_SYMBOL_GPL(w1_touch_block);
281
282 /**
283 * Reads a series of bytes.
284 *
285 * @param dev the master device
286 * @param buf pointer to the buffer to fill
287 * @param len the number of bytes to read
288 * @return the number of bytes read
289 */
290 u8 w1_read_block(struct w1_master *dev, u8 *buf, int len)
291 {
292 int i;
293 u8 ret;
294
295 if (dev->bus_master->read_block)
296 ret = dev->bus_master->read_block(dev->bus_master->data, buf, len);
297 else {
298 for (i = 0; i < len; ++i)
299 buf[i] = w1_read_8(dev);
300 ret = len;
301 }
302
303 return ret;
304 }
305 EXPORT_SYMBOL_GPL(w1_read_block);
306
307 /**
308 * Issues a reset bus sequence.
309 *
310 * @param dev The bus master pointer
311 * @return 0=Device present, 1=No device present or error
312 */
313 int w1_reset_bus(struct w1_master *dev)
314 {
315 int result;
316
317 if (dev->bus_master->reset_bus)
318 result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
319 else {
320 dev->bus_master->write_bit(dev->bus_master->data, 0);
321 /* minimum 480, max ? us
322 * be nice and sleep, except 18b20 spec lists 960us maximum,
323 * so until we can sleep with microsecond accuracy, spin.
324 * Feel free to come up with some other way to give up the
325 * cpu for such a short amount of time AND get it back in
326 * the maximum amount of time.
327 */
328 w1_delay(480);
329 dev->bus_master->write_bit(dev->bus_master->data, 1);
330 w1_delay(70);
331
332 result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
333 /* minmum 70 (above) + 410 = 480 us
334 * There aren't any timing requirements between a reset and
335 * the following transactions. Sleeping is safe here.
336 */
337 /* w1_delay(410); min required time */
338 msleep(1);
339 }
340
341 return result;
342 }
343 EXPORT_SYMBOL_GPL(w1_reset_bus);
344
345 u8 w1_calc_crc8(u8 * data, int len)
346 {
347 u8 crc = 0;
348
349 while (len--)
350 crc = w1_crc8_table[crc ^ *data++];
351
352 return crc;
353 }
354 EXPORT_SYMBOL_GPL(w1_calc_crc8);
355
356 void w1_search_devices(struct w1_master *dev, u8 search_type, w1_slave_found_callback cb)
357 {
358 dev->attempts++;
359 if (dev->bus_master->search)
360 dev->bus_master->search(dev->bus_master->data, dev,
361 search_type, cb);
362 else
363 w1_search(dev, search_type, cb);
364 }
365
366 /**
367 * Resets the bus and then selects the slave by sending either a skip rom
368 * or a rom match.
369 * The w1 master lock must be held.
370 *
371 * @param sl the slave to select
372 * @return 0=success, anything else=error
373 */
374 int w1_reset_select_slave(struct w1_slave *sl)
375 {
376 if (w1_reset_bus(sl->master))
377 return -1;
378
379 if (sl->master->slave_count == 1)
380 w1_write_8(sl->master, W1_SKIP_ROM);
381 else {
382 u8 match[9] = {W1_MATCH_ROM, };
383 u64 rn = le64_to_cpu(*((u64*)&sl->reg_num));
384
385 memcpy(&match[1], &rn, 8);
386 w1_write_block(sl->master, match, 9);
387 }
388 return 0;
389 }
390 EXPORT_SYMBOL_GPL(w1_reset_select_slave);
391
392 /**
393 * Put out a strong pull-up of the specified duration after the next write
394 * operation. Not all hardware supports strong pullups. Hardware that
395 * doesn't support strong pullups will sleep for the given time after the
396 * write operation without a strong pullup. This is a one shot request for
397 * the next write, specifying zero will clear a previous request.
398 * The w1 master lock must be held.
399 *
400 * @param delay time in milliseconds
401 * @return 0=success, anything else=error
402 */
403 void w1_next_pullup(struct w1_master *dev, int delay)
404 {
405 dev->pullup_duration = delay;
406 }
407 EXPORT_SYMBOL_GPL(w1_next_pullup);
408
|
This page was automatically generated by the
LXR engine.
|