1 /*
2 * linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver
3 *
4 * Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de>
5 *
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file COPYING in the main directory of this
8 * archive for more details.
9 */
10
11
12 #ifndef __SAVAGEFB_H__
13 #define __SAVAGEFB_H__
14
15 #include <linux/i2c.h>
16 #include <linux/i2c-id.h>
17 #include <linux/i2c-algo-bit.h>
18 #include "../edid.h"
19
20 #ifdef SAVAGEFB_DEBUG
21 # define DBG(x) printk (KERN_DEBUG "savagefb: %s\n", (x));
22 #else
23 # define DBG(x)
24 # define SavagePrintRegs(...)
25 #endif
26
27
28 #define PCI_CHIP_SAVAGE4 0x8a22
29 #define PCI_CHIP_SAVAGE3D 0x8a20
30 #define PCI_CHIP_SAVAGE3D_MV 0x8a21
31 #define PCI_CHIP_SAVAGE2000 0x9102
32 #define PCI_CHIP_SAVAGE_MX_MV 0x8c10
33 #define PCI_CHIP_SAVAGE_MX 0x8c11
34 #define PCI_CHIP_SAVAGE_IX_MV 0x8c12
35 #define PCI_CHIP_SAVAGE_IX 0x8c13
36 #define PCI_CHIP_PROSAVAGE_PM 0x8a25
37 #define PCI_CHIP_PROSAVAGE_KM 0x8a26
38 /* Twister is a code name; hope I get the real name soon. */
39 #define PCI_CHIP_S3TWISTER_P 0x8d01
40 #define PCI_CHIP_S3TWISTER_K 0x8d02
41 #define PCI_CHIP_PROSAVAGE_DDR 0x8d03
42 #define PCI_CHIP_PROSAVAGE_DDRK 0x8d04
43 #define PCI_CHIP_SUPSAV_MX128 0x8c22
44 #define PCI_CHIP_SUPSAV_MX64 0x8c24
45 #define PCI_CHIP_SUPSAV_MX64C 0x8c26
46 #define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a
47 #define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b
48 #define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c
49 #define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d
50 #define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e
51 #define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f
52
53
54
55 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
56
57 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE))
58
59 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
60
61 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
62
63
64 /* Chip tags. These are used to group the adapters into
65 * related families.
66 */
67
68 typedef enum {
69 S3_UNKNOWN = 0,
70 S3_SAVAGE3D,
71 S3_SAVAGE_MX,
72 S3_SAVAGE4,
73 S3_PROSAVAGE,
74 S3_SUPERSAVAGE,
75 S3_SAVAGE2000,
76 S3_LAST
77 } savage_chipset;
78
79 #define BIOS_BSIZE 1024
80 #define BIOS_BASE 0xc0000
81
82 #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */
83 #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000
84 #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */
85 #define SAVAGE_NEWMMIO_VGABASE 0x8000
86
87 #define BASE_FREQ 14318
88 #define HALF_BASE_FREQ 7159
89
90 #define FIFO_CONTROL_REG 0x8200
91 #define MIU_CONTROL_REG 0x8204
92 #define STREAMS_TIMEOUT_REG 0x8208
93 #define MISC_TIMEOUT_REG 0x820c
94
95 #define MONO_PAT_0 0xa4e8
96 #define MONO_PAT_1 0xa4ec
97
98 #define MAXFIFO 0x7f00
99
100 #define BCI_CMD_NOP 0x40000000
101 #define BCI_CMD_SETREG 0x96000000
102 #define BCI_CMD_RECT 0x48000000
103 #define BCI_CMD_RECT_XP 0x01000000
104 #define BCI_CMD_RECT_YP 0x02000000
105 #define BCI_CMD_SEND_COLOR 0x00008000
106 #define BCI_CMD_DEST_GBD 0x00000000
107 #define BCI_CMD_SRC_GBD 0x00000020
108 #define BCI_CMD_SRC_SOLID 0x00000000
109 #define BCI_CMD_SRC_MONO 0x00000060
110 #define BCI_CMD_CLIP_NEW 0x00006000
111 #define BCI_CMD_CLIP_LR 0x00004000
112
113 #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
114 #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
115 #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
116 #define BCI_W_H(w, h) (((h) << 16) | ((w) & 0xFFF))
117 #define BCI_X_Y(x, y) (((y) << 16) | ((x) & 0xFFF))
118
119 #define BCI_GBD1 0xE0
120 #define BCI_GBD2 0xE1
121
122 #define BCI_BUFFER_OFFSET 0x10000
123 #define BCI_SIZE 0x4000
124
125 #define BCI_SEND(dw) writel(dw, par->bci_base + par->bci_ptr++)
126
127 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
128 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
129 #define BCI_CMD_SEND_COLOR 0x00008000
130
131 struct xtimings {
132 unsigned int Clock;
133 unsigned int HDisplay;
134 unsigned int HSyncStart;
135 unsigned int HSyncEnd;
136 unsigned int HTotal;
137 unsigned int HAdjusted;
138 unsigned int VDisplay;
139 unsigned int VSyncStart;
140 unsigned int VSyncEnd;
141 unsigned int VTotal;
142 unsigned int sync;
143 int dblscan;
144 int interlaced;
145 };
146
147
148 /* --------------------------------------------------------------------- */
149
150 #define NR_PALETTE 256
151
152
153 struct savagefb_par;
154
155 struct savagefb_i2c_chan {
156 struct savagefb_par *par;
157 struct i2c_adapter adapter;
158 struct i2c_algo_bit_data algo;
159 volatile u8 __iomem *ioaddr;
160 u32 reg;
161 };
162
163 struct savagefb_par {
164 struct pci_dev *pcidev;
165 savage_chipset chip;
166 struct savagefb_i2c_chan chan;
167 unsigned char *edid;
168 u32 pseudo_palette[16];
169 int dacSpeedBpp;
170 int maxClock;
171 int minClock;
172 int numClocks;
173 int clock[4];
174 struct {
175 u8 __iomem *vbase;
176 u32 pbase;
177 u32 len;
178 #ifdef CONFIG_MTRR
179 int mtrr;
180 #endif
181 } video;
182
183 struct {
184 volatile u8 __iomem *vbase;
185 u32 pbase;
186 u32 len;
187 } mmio;
188
189 volatile u32 __iomem *bci_base;
190 unsigned int bci_ptr;
191
192 u32 cob_offset;
193 u32 cob_size;
194 int cob_index;
195
196 void (*SavageWaitIdle) (struct savagefb_par *par);
197 void (*SavageWaitFifo) (struct savagefb_par *par, int space);
198
199 int MCLK, REFCLK, LCDclk;
200 int HorizScaleFactor;
201
202 /* Panels size */
203 int SavagePanelWidth;
204 int SavagePanelHeight;
205
206 struct {
207 u16 red, green, blue, transp;
208 } palette[NR_PALETTE];
209
210 int depth;
211 int vwidth;
212
213 unsigned char MiscOutReg; /* Misc */
214 unsigned char CRTC[25]; /* Crtc Controller */
215 unsigned char Sequencer[5]; /* Video Sequencer */
216 unsigned char Graphics[9]; /* Video Graphics */
217 unsigned char Attribute[21]; /* Video Atribute */
218
219 unsigned int mode, refresh;
220 unsigned char SR08, SR0E, SR0F;
221 unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29, SR30;
222 unsigned char SR54[8];
223 unsigned char Clock;
224 unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C;
225 unsigned char CR40, CR41, CR42, CR43, CR45;
226 unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E;
227 unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F;
228 unsigned char CR86, CR88;
229 unsigned char CR90, CR91, CRB0;
230 unsigned int STREAMS[22]; /* yuck, streams regs */
231 unsigned int MMPR0, MMPR1, MMPR2, MMPR3;
232 };
233
234 #define BCI_BD_BW_DISABLE 0x10000000
235 #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
236 #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
237
238
239 /* IO functions */
240
241 #define vga_in8(addr) (inb (addr))
242 #define vga_in16(addr) (inw (addr))
243 #define vga_in32(addr) (inl (addr))
244
245 #define vga_out8(addr,val) (outb ((val), (addr)))
246 #define vga_out16(addr,val) (outw ((val), (addr)))
247 #define vga_out32(addr,val) (outl ((val), (addr)))
248
249 #define savage_in16(addr) readw(par->mmio.vbase + (addr))
250 #define savage_in32(addr) readl(par->mmio.vbase + (addr))
251
252 #define savage_out16(addr,val) writew((val), par->mmio.vbase + (addr))
253 #define savage_out32(addr,val) writel((val), par->mmio.vbase + (addr))
254
255 static inline u8 VGArCR (u8 index)
256 {
257 outb (index, 0x3d4);
258 return inb (0x3d5);
259 }
260
261 static inline u8 VGArGR (u8 index)
262 {
263 outb (index, 0x3ce);
264 return inb (0x3cf);
265 }
266
267 static inline u8 VGArSEQ (u8 index)
268 {
269 outb (index, 0x3c4);
270 return inb (0x3c5);
271 }
272
273 #define VGAwCR(index, val) \
274 do { \
275 vga_out8 (0x3d4, index); \
276 vga_out8 (0x3d5, val); \
277 } while (0)
278
279 #define VGAwGR(index, val) \
280 do { \
281 vga_out8 (0x3ce, index); \
282 vga_out8 (0x3cf, val); \
283 } while (0)
284
285 #define VGAwSEQ(index, val) \
286 do { \
287 vga_out8 (0x3c4, index); \
288 vga_out8 (0x3c5, val); \
289 } while (0)
290
291 #define VGAenablePalette() \
292 do { \
293 u8 tmp; \
294 \
295 tmp = vga_in8 (0x3da); \
296 vga_out8 (0x3c0, 0x00); \
297 paletteEnabled = 1; \
298 } while (0)
299
300 #define VGAdisablePalette() \
301 do { \
302 u8 tmp; \
303 \
304 tmp = vga_in8 (0x3da); \
305 vga_out8 (0x3c0, 0x20); \
306 paletteEnabled = 0; \
307 } while (0)
308
309 #define VGAwATTR(index, value) \
310 do { \
311 u8 tmp; \
312 \
313 if (paletteEnabled) \
314 index &= ~0x20; \
315 else \
316 index |= 0x20; \
317 \
318 tmp = vga_in8 (0x3da); \
319 vga_out8 (0x3c0, index); \
320 vga_out8 (0x3c0, value); \
321 } while (0)
322
323 #define VGAwMISC(value) \
324 do { \
325 vga_out8 (0x3c2, value); \
326 } while (0)
327
328 #ifndef CONFIG_FB_SAVAGE_ACCEL
329 #define savagefb_set_clip(x)
330 #endif
331
332 #define VerticalRetraceWait() \
333 { \
334 vga_out8 (0x3d4, 0x17); \
335 if (vga_in8 (0x3d5) & 0x80) { \
336 while ((vga_in8(0x3da) & 0x08) == 0x08) ; \
337 while ((vga_in8(0x3da) & 0x08) == 0x00) ; \
338 } \
339 }
340
341 extern int savagefb_probe_i2c_connector(struct savagefb_par *par,
342 u8 **out_edid);
343 extern void savagefb_create_i2c_busses(struct fb_info *info);
344 extern void savagefb_delete_i2c_busses(struct fb_info *info);
345 extern int savagefb_sync(struct fb_info *info);
346 extern void savagefb_copyarea(struct fb_info *info,
347 const struct fb_copyarea *region);
348 extern void savagefb_fillrect(struct fb_info *info,
349 const struct fb_fillrect *rect);
350 extern void savagefb_imageblit(struct fb_info *info,
351 const struct fb_image *image);
352
353
354 #endif /* __SAVAGEFB_H__ */
355
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