1 #ifndef _INTELFBHW_H
2 #define _INTELFBHW_H
3
4 /* $DHD: intelfb/intelfbhw.h,v 1.5 2003/06/27 15:06:25 dawes Exp $ */
5
6
7 /*** HW-specific data ***/
8
9 /* Information about the 852GM/855GM variants */
10 #define INTEL_85X_CAPID 0x44
11 #define INTEL_85X_VARIANT_MASK 0x7
12 #define INTEL_85X_VARIANT_SHIFT 5
13 #define INTEL_VAR_855GME 0x0
14 #define INTEL_VAR_855GM 0x4
15 #define INTEL_VAR_852GME 0x2
16 #define INTEL_VAR_852GM 0x5
17
18 /* Information about DVO/LVDS Ports */
19 #define DVOA_PORT 0x1
20 #define DVOB_PORT 0x2
21 #define DVOC_PORT 0x4
22 #define LVDS_PORT 0x8
23
24 /*
25 * The Bridge device's PCI config space has information about the
26 * fb aperture size and the amount of pre-reserved memory.
27 */
28 #define INTEL_GMCH_CTRL 0x52
29 #define INTEL_GMCH_ENABLED 0x4
30 #define INTEL_GMCH_MEM_MASK 0x1
31 #define INTEL_GMCH_MEM_64M 0x1
32 #define INTEL_GMCH_MEM_128M 0
33
34 #define INTEL_830_GMCH_GMS_MASK (0x7 << 4)
35 #define INTEL_830_GMCH_GMS_DISABLED (0x0 << 4)
36 #define INTEL_830_GMCH_GMS_LOCAL (0x1 << 4)
37 #define INTEL_830_GMCH_GMS_STOLEN_512 (0x2 << 4)
38 #define INTEL_830_GMCH_GMS_STOLEN_1024 (0x3 << 4)
39 #define INTEL_830_GMCH_GMS_STOLEN_8192 (0x4 << 4)
40
41 #define INTEL_855_GMCH_GMS_MASK (0x7 << 4)
42 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
43 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
44 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
45 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
46 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
47 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
48
49 /* HW registers */
50
51 /* Fence registers */
52 #define FENCE 0x2000
53 #define FENCE_NUM 8
54
55 /* Primary ring buffer */
56 #define PRI_RING_TAIL 0x2030
57 #define RING_TAIL_MASK 0x001ffff8
58 #define RING_INUSE 0x1
59
60 #define PRI_RING_HEAD 0x2034
61 #define RING_HEAD_WRAP_MASK 0x7ff
62 #define RING_HEAD_WRAP_SHIFT 21
63 #define RING_HEAD_MASK 0x001ffffc
64
65 #define PRI_RING_START 0x2038
66 #define RING_START_MASK 0xfffff000
67
68 #define PRI_RING_LENGTH 0x203c
69 #define RING_LENGTH_MASK 0x001ff000
70 #define RING_REPORT_MASK (0x3 << 1)
71 #define RING_NO_REPORT (0x0 << 1)
72 #define RING_REPORT_64K (0x1 << 1)
73 #define RING_REPORT_4K (0x2 << 1)
74 #define RING_REPORT_128K (0x3 << 1)
75 #define RING_ENABLE 0x1
76
77 /*
78 * Tail can't wrap to any closer than RING_MIN_FREE bytes of the head,
79 * and the last RING_MIN_FREE bytes need to be padded with MI_NOOP
80 */
81 #define RING_MIN_FREE 64
82
83 #define IPEHR 0x2088
84
85 #define INSTDONE 0x2090
86 #define PRI_RING_EMPTY 1
87
88 #define INSTPM 0x20c0
89 #define SYNC_FLUSH_ENABLE (1 << 5)
90
91 #define INSTPS 0x20c4
92
93 #define MEM_MODE 0x20cc
94
95 #define MASK_SHIFT 16
96
97 #define FW_BLC_0 0x20d8
98 #define FW_DISPA_WM_SHIFT 0
99 #define FW_DISPA_WM_MASK 0x3f
100 #define FW_DISPA_BL_SHIFT 8
101 #define FW_DISPA_BL_MASK 0xf
102 #define FW_DISPB_WM_SHIFT 16
103 #define FW_DISPB_WM_MASK 0x1f
104 #define FW_DISPB_BL_SHIFT 24
105 #define FW_DISPB_BL_MASK 0x7
106
107 #define FW_BLC_1 0x20dc
108 #define FW_DISPC_WM_SHIFT 0
109 #define FW_DISPC_WM_MASK 0x1f
110 #define FW_DISPC_BL_SHIFT 8
111 #define FW_DISPC_BL_MASK 0x7
112
113
114 /* PLL registers */
115 #define VGA0_DIVISOR 0x06000
116 #define VGA1_DIVISOR 0x06004
117 #define VGAPD 0x06010
118 #define VGAPD_0_P1_SHIFT 0
119 #define VGAPD_0_P1_FORCE_DIV2 (1 << 5)
120 #define VGAPD_0_P2_SHIFT 7
121 #define VGAPD_1_P1_SHIFT 8
122 #define VGAPD_1_P1_FORCE_DIV2 (1 << 13)
123 #define VGAPD_1_P2_SHIFT 15
124
125 #define DPLL_A 0x06014
126 #define DPLL_B 0x06018
127 #define DPLL_VCO_ENABLE (1 << 31)
128 #define DPLL_2X_CLOCK_ENABLE (1 << 30)
129 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
130 #define DPLL_VGA_MODE_DISABLE (1 << 28)
131 #define DPLL_P2_MASK 1
132 #define DPLL_P2_SHIFT 23
133 #define DPLL_P1_FORCE_DIV2 (1 << 21)
134 #define DPLL_P1_MASK 0x1f
135 #define DPLL_P1_SHIFT 16
136 #define DPLL_REFERENCE_SELECT_MASK (0x3 << 13)
137 #define DPLL_REFERENCE_DEFAULT (0x0 << 13)
138 #define DPLL_REFERENCE_TVCLK (0x2 << 13)
139 #define DPLL_RATE_SELECT_MASK (1 << 8)
140 #define DPLL_RATE_SELECT_FP0 (0 << 8)
141 #define DPLL_RATE_SELECT_FP1 (1 << 8)
142
143 #define FPA0 0x06040
144 #define FPA1 0x06044
145 #define FPB0 0x06048
146 #define FPB1 0x0604c
147 #define FP_DIVISOR_MASK 0x3f
148 #define FP_N_DIVISOR_SHIFT 16
149 #define FP_M1_DIVISOR_SHIFT 8
150 #define FP_M2_DIVISOR_SHIFT 0
151
152 /* PLL parameters (these are for 852GM/855GM/865G, check earlier chips). */
153 /* Clock values are in units of kHz */
154 #define PLL_REFCLK 48000
155 #define MIN_VCO_FREQ 930000
156 #define MAX_VCO_FREQ 1400000
157 #define MIN_CLOCK 25000
158 #define MAX_CLOCK 350000
159 #define P_TRANSITION_CLOCK 165000
160 #define MIN_M 108
161 #define MAX_M 140
162 #define MIN_M1 18
163 #define MAX_M1 26
164 #define MIN_M2 6
165 #define MAX_M2 16
166 #define MIN_P 4
167 #define MAX_P 128
168 #define MIN_P1 0
169 #define MAX_P1 31
170 #define MIN_N 3
171 #define MAX_N 16
172
173 #define CALC_VCLOCK(m1, m2, n, p1, p2) \
174 ((PLL_REFCLK * (5 * ((m1) + 2) + ((m2) + 2)) / ((n) + 2)) / \
175 (((p1) + 2) * (1 << (p2 + 1))))
176
177 #define CALC_VCLOCK3(m, n, p) ((PLL_REFCLK * (m) / (n)) / (p))
178
179 /* Two pipes */
180 #define PIPE_A 0
181 #define PIPE_B 1
182 #define PIPE_MASK 1
183
184 /* palette registers */
185 #define PALETTE_A 0x0a000
186 #define PALETTE_B 0x0a800
187 #ifndef PALETTE_8_ENTRIES
188 #define PALETTE_8_ENTRIES 256
189 #endif
190 #define PALETTE_8_SIZE (PALETTE_8_ENTRIES * 4)
191 #define PALETTE_10_ENTRIES 128
192 #define PALETTE_10_SIZE (PALETTE_10_ENTRIES * 8)
193 #define PALETTE_8_MASK 0xff
194 #define PALETTE_8_RED_SHIFT 16
195 #define PALETTE_8_GREEN_SHIFT 8
196 #define PALETTE_8_BLUE_SHIFT 0
197
198 /* CRTC registers */
199 #define HTOTAL_A 0x60000
200 #define HBLANK_A 0x60004
201 #define HSYNC_A 0x60008
202 #define VTOTAL_A 0x6000c
203 #define VBLANK_A 0x60010
204 #define VSYNC_A 0x60014
205 #define SRC_SIZE_A 0x6001c
206 #define BCLRPAT_A 0x60020
207
208 #define HTOTAL_B 0x61000
209 #define HBLANK_B 0x61004
210 #define HSYNC_B 0x61008
211 #define VTOTAL_B 0x6100c
212 #define VBLANK_B 0x61010
213 #define VSYNC_B 0x61014
214 #define SRC_SIZE_B 0x6101c
215 #define BCLRPAT_B 0x61020
216
217 #define HTOTAL_MASK 0xfff
218 #define HTOTAL_SHIFT 16
219 #define HACTIVE_MASK 0x7ff
220 #define HACTIVE_SHIFT 0
221 #define HBLANKEND_MASK 0xfff
222 #define HBLANKEND_SHIFT 16
223 #define HBLANKSTART_MASK 0xfff
224 #define HBLANKSTART_SHIFT 0
225 #define HSYNCEND_MASK 0xfff
226 #define HSYNCEND_SHIFT 16
227 #define HSYNCSTART_MASK 0xfff
228 #define HSYNCSTART_SHIFT 0
229 #define VTOTAL_MASK 0xfff
230 #define VTOTAL_SHIFT 16
231 #define VACTIVE_MASK 0x7ff
232 #define VACTIVE_SHIFT 0
233 #define VBLANKEND_MASK 0xfff
234 #define VBLANKEND_SHIFT 16
235 #define VBLANKSTART_MASK 0xfff
236 #define VBLANKSTART_SHIFT 0
237 #define VSYNCEND_MASK 0xfff
238 #define VSYNCEND_SHIFT 16
239 #define VSYNCSTART_MASK 0xfff
240 #define VSYNCSTART_SHIFT 0
241 #define SRC_SIZE_HORIZ_MASK 0x7ff
242 #define SRC_SIZE_HORIZ_SHIFT 16
243 #define SRC_SIZE_VERT_MASK 0x7ff
244 #define SRC_SIZE_VERT_SHIFT 0
245
246 #define ADPA 0x61100
247 #define ADPA_DAC_ENABLE (1 << 31)
248 #define ADPA_DAC_DISABLE 0
249 #define ADPA_PIPE_SELECT_SHIFT 30
250 #define ADPA_USE_VGA_HVPOLARITY (1 << 15)
251 #define ADPA_SETS_HVPOLARITY 0
252 #define ADPA_DPMS_CONTROL_MASK (0x3 << 10)
253 #define ADPA_DPMS_D0 (0x0 << 10)
254 #define ADPA_DPMS_D2 (0x1 << 10)
255 #define ADPA_DPMS_D1 (0x2 << 10)
256 #define ADPA_DPMS_D3 (0x3 << 10)
257 #define ADPA_VSYNC_ACTIVE_SHIFT 4
258 #define ADPA_HSYNC_ACTIVE_SHIFT 3
259 #define ADPA_SYNC_ACTIVE_MASK 1
260 #define ADPA_SYNC_ACTIVE_HIGH 1
261 #define ADPA_SYNC_ACTIVE_LOW 0
262
263 #define DVOA 0x61120
264 #define DVOB 0x61140
265 #define DVOC 0x61160
266 #define LVDS 0x61180
267 #define PORT_ENABLE (1 << 31)
268 #define PORT_PIPE_SELECT_SHIFT 30
269 #define PORT_TV_FLAGS_MASK 0xFF
270 #define PORT_TV_FLAGS 0xC4 // ripped from my BIOS
271 // to understand and correct
272
273 #define DVOA_SRCDIM 0x61124
274 #define DVOB_SRCDIM 0x61144
275 #define DVOC_SRCDIM 0x61164
276
277 #define PIPEACONF 0x70008
278 #define PIPEBCONF 0x71008
279 #define PIPECONF_ENABLE (1 << 31)
280 #define PIPECONF_DISABLE 0
281 #define PIPECONF_DOUBLE_WIDE (1 << 30)
282 #define PIPECONF_SINGLE_WIDE 0
283 #define PIPECONF_LOCKED (1 << 25)
284 #define PIPECONF_UNLOCKED 0
285 #define PIPECONF_GAMMA (1 << 24)
286 #define PIPECONF_PALETTE 0
287
288 #define DISPARB 0x70030
289 #define DISPARB_AEND_MASK 0x1ff
290 #define DISPARB_AEND_SHIFT 0
291 #define DISPARB_BEND_MASK 0x3ff
292 #define DISPARB_BEND_SHIFT 9
293
294 /* Desktop HW cursor */
295 #define CURSOR_CONTROL 0x70080
296 #define CURSOR_ENABLE (1 << 31)
297 #define CURSOR_GAMMA_ENABLE (1 << 30)
298 #define CURSOR_STRIDE_MASK (0x3 << 28)
299 #define CURSOR_STRIDE_256 (0x0 << 28)
300 #define CURSOR_STRIDE_512 (0x1 << 28)
301 #define CURSOR_STRIDE_1K (0x2 << 28)
302 #define CURSOR_STRIDE_2K (0x3 << 28)
303 #define CURSOR_FORMAT_MASK (0x7 << 24)
304 #define CURSOR_FORMAT_2C (0x0 << 24)
305 #define CURSOR_FORMAT_3C (0x1 << 24)
306 #define CURSOR_FORMAT_4C (0x2 << 24)
307 #define CURSOR_FORMAT_ARGB (0x4 << 24)
308 #define CURSOR_FORMAT_XRGB (0x5 << 24)
309
310 /* Mobile HW cursor (and i810) */
311 #define CURSOR_A_CONTROL CURSOR_CONTROL
312 #define CURSOR_B_CONTROL 0x700c0
313 #define CURSOR_MODE_MASK 0x27
314 #define CURSOR_MODE_DISABLE 0
315 #define CURSOR_MODE_64_3C 0x04
316 #define CURSOR_MODE_64_4C_AX 0x05
317 #define CURSOR_MODE_64_4C 0x06
318 #define CURSOR_MODE_64_32B_AX 0x07
319 #define CURSOR_MODE_64_ARGB_AX 0x27
320 #define CURSOR_PIPE_SELECT_SHIFT 28
321 #define CURSOR_MOBILE_GAMMA_ENABLE (1 << 26)
322 #define CURSOR_MEM_TYPE_LOCAL (1 << 25)
323
324 /* All platforms (desktop has no pipe B) */
325 #define CURSOR_A_BASEADDR 0x70084
326 #define CURSOR_B_BASEADDR 0x700c4
327 #define CURSOR_BASE_MASK 0xffffff00
328
329 #define CURSOR_A_POSITION 0x70088
330 #define CURSOR_B_POSITION 0x700c8
331 #define CURSOR_POS_SIGN (1 << 15)
332 #define CURSOR_POS_MASK 0x7ff
333 #define CURSOR_X_SHIFT 0
334 #define CURSOR_Y_SHIFT 16
335
336 #define CURSOR_A_PALETTE0 0x70090
337 #define CURSOR_A_PALETTE1 0x70094
338 #define CURSOR_A_PALETTE2 0x70098
339 #define CURSOR_A_PALETTE3 0x7009c
340 #define CURSOR_B_PALETTE0 0x700d0
341 #define CURSOR_B_PALETTE1 0x700d4
342 #define CURSOR_B_PALETTE2 0x700d8
343 #define CURSOR_B_PALETTE3 0x700dc
344 #define CURSOR_COLOR_MASK 0xff
345 #define CURSOR_RED_SHIFT 16
346 #define CURSOR_GREEN_SHIFT 8
347 #define CURSOR_BLUE_SHIFT 0
348 #define CURSOR_PALETTE_MASK 0xffffff
349
350 /* Desktop only */
351 #define CURSOR_SIZE 0x700a0
352 #define CURSOR_SIZE_MASK 0x3ff
353 #define CURSOR_SIZE_H_SHIFT 0
354 #define CURSOR_SIZE_V_SHIFT 12
355
356 #define DSPACNTR 0x70180
357 #define DSPBCNTR 0x71180
358 #define DISPPLANE_PLANE_ENABLE (1 << 31)
359 #define DISPPLANE_PLANE_DISABLE 0
360 #define DISPPLANE_GAMMA_ENABLE (1<<30)
361 #define DISPPLANE_GAMMA_DISABLE 0
362 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
363 #define DISPPLANE_8BPP (0x2<<26)
364 #define DISPPLANE_15_16BPP (0x4<<26)
365 #define DISPPLANE_16BPP (0x5<<26)
366 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
367 #define DISPPLANE_32BPP (0x7<<26)
368 #define DISPPLANE_STEREO_ENABLE (1<<25)
369 #define DISPPLANE_STEREO_DISABLE 0
370 #define DISPPLANE_SEL_PIPE_SHIFT 24
371 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
372 #define DISPPLANE_SRC_KEY_DISABLE 0
373 #define DISPPLANE_LINE_DOUBLE (1<<20)
374 #define DISPPLANE_NO_LINE_DOUBLE 0
375 #define DISPPLANE_STEREO_POLARITY_FIRST 0
376 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
377 /* plane B only */
378 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
379 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
380 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
381 #define DISPPLANE_SPRITE_ABOVE_OVERLAY 1
382
383 #define DSPABASE 0x70184
384 #define DSPASTRIDE 0x70188
385
386 #define DSPBBASE 0x71184
387 #define DSPBSTRIDE 0x71188
388
389 #define VGACNTRL 0x71400
390 #define VGA_DISABLE (1 << 31)
391 #define VGA_ENABLE 0
392 #define VGA_PIPE_SELECT_SHIFT 29
393 #define VGA_PALETTE_READ_SELECT 23
394 #define VGA_PALETTE_A_WRITE_DISABLE (1 << 22)
395 #define VGA_PALETTE_B_WRITE_DISABLE (1 << 21)
396 #define VGA_LEGACY_PALETTE (1 << 20)
397 #define VGA_6BIT_DAC 0
398 #define VGA_8BIT_DAC (1 << 20)
399
400 #define ADD_ID 0x71408
401 #define ADD_ID_MASK 0xff
402
403 /* BIOS scratch area registers (830M and 845G). */
404 #define SWF0 0x71410
405 #define SWF1 0x71414
406 #define SWF2 0x71418
407 #define SWF3 0x7141c
408 #define SWF4 0x71420
409 #define SWF5 0x71424
410 #define SWF6 0x71428
411
412 /* BIOS scratch area registers (852GM, 855GM, 865G). */
413 #define SWF00 0x70410
414 #define SWF01 0x70414
415 #define SWF02 0x70418
416 #define SWF03 0x7041c
417 #define SWF04 0x70420
418 #define SWF05 0x70424
419 #define SWF06 0x70428
420
421 #define SWF10 SWF0
422 #define SWF11 SWF1
423 #define SWF12 SWF2
424 #define SWF13 SWF3
425 #define SWF14 SWF4
426 #define SWF15 SWF5
427 #define SWF16 SWF6
428
429 #define SWF30 0x72414
430 #define SWF31 0x72418
431 #define SWF32 0x7241c
432
433 /* Memory Commands */
434 #define MI_NOOP (0x00 << 23)
435 #define MI_NOOP_WRITE_ID (1 << 22)
436 #define MI_NOOP_ID_MASK ((1 << 22) - 1)
437
438 #define MI_FLUSH (0x04 << 23)
439 #define MI_WRITE_DIRTY_STATE (1 << 4)
440 #define MI_END_SCENE (1 << 3)
441 #define MI_INHIBIT_RENDER_CACHE_FLUSH (1 << 2)
442 #define MI_INVALIDATE_MAP_CACHE (1 << 0)
443
444 #define MI_STORE_DWORD_IMM ((0x20 << 23) | 1)
445
446 /* 2D Commands */
447 #define COLOR_BLT_CMD ((2 << 29) | (0x40 << 22) | 3)
448 #define XY_COLOR_BLT_CMD ((2 << 29) | (0x50 << 22) | 4)
449 #define XY_SETUP_CLIP_BLT_CMD ((2 << 29) | (0x03 << 22) | 1)
450 #define XY_SRC_COPY_BLT_CMD ((2 << 29) | (0x53 << 22) | 6)
451 #define SRC_COPY_BLT_CMD ((2 << 29) | (0x43 << 22) | 4)
452 #define XY_MONO_PAT_BLT_CMD ((2 << 29) | (0x52 << 22) | 7)
453 #define XY_MONO_SRC_BLT_CMD ((2 << 29) | (0x54 << 22) | 6)
454 #define XY_MONO_SRC_IMM_BLT_CMD ((2 << 29) | (0x71 << 22) | 5)
455 #define TXT_IMM_BLT_CMD ((2 << 29) | (0x30 << 22) | 2)
456 #define SETUP_BLT_CMD ((2 << 29) | (0x00 << 22) | 6)
457
458 #define DW_LENGTH_MASK 0xff
459
460 #define WRITE_ALPHA (1 << 21)
461 #define WRITE_RGB (1 << 20)
462 #define VERT_SEED (3 << 8)
463 #define HORIZ_SEED (3 << 12)
464
465 #define COLOR_DEPTH_8 (0 << 24)
466 #define COLOR_DEPTH_16 (1 << 24)
467 #define COLOR_DEPTH_32 (3 << 24)
468
469 #define SRC_ROP_GXCOPY 0xcc
470 #define SRC_ROP_GXXOR 0x66
471
472 #define PAT_ROP_GXCOPY 0xf0
473 #define PAT_ROP_GXXOR 0x5a
474
475 #define PITCH_SHIFT 0
476 #define ROP_SHIFT 16
477 #define WIDTH_SHIFT 0
478 #define HEIGHT_SHIFT 16
479
480 /* in bytes */
481 #define MAX_MONO_IMM_SIZE 128
482
483
484 /*** Macros ***/
485
486 /* I/O macros */
487 #define INREG8(addr) readb((u8 __iomem *)(dinfo->mmio_base + (addr)))
488 #define INREG(addr) readl((u32 __iomem *)(dinfo->mmio_base + (addr)))
489 #define OUTREG8(addr, val) writeb((val),(u8 __iomem *)(dinfo->mmio_base + \
490 (addr)))
491 #define OUTREG(addr, val) writel((val),(u32 __iomem *)(dinfo->mmio_base + \
492 (addr)))
493
494 /* Ring buffer macros */
495 #define OUT_RING(n) do { \
496 writel((n), (u32 __iomem *)(dinfo->ring.virtual + dinfo->ring_tail));\
497 dinfo->ring_tail += 4; \
498 dinfo->ring_tail &= dinfo->ring_tail_mask; \
499 } while (0)
500
501 #define START_RING(n) do { \
502 if (dinfo->ring_space < (n) * 4) \
503 wait_ring(dinfo,(n) * 4); \
504 dinfo->ring_space -= (n) * 4; \
505 } while (0)
506
507 #define ADVANCE_RING() do { \
508 OUTREG(PRI_RING_TAIL, dinfo->ring_tail); \
509 } while (0)
510
511 #define DO_RING_IDLE() do { \
512 u32 head, tail; \
513 do { \
514 head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; \
515 tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; \
516 udelay(10); \
517 } while (head != tail); \
518 } while (0)
519
520
521 /* function protoypes */
522 extern int intelfbhw_get_chipset(struct pci_dev *pdev, const char **name,
523 int *chipset, int *mobile);
524 extern int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
525 int *stolen_size);
526 extern int intelfbhw_check_non_crt(struct intelfb_info *dinfo);
527 extern const char *intelfbhw_dvo_to_string(int dvo);
528 extern int intelfbhw_validate_mode(struct intelfb_info *dinfo,
529 struct fb_var_screeninfo *var);
530 extern int intelfbhw_pan_display(struct fb_var_screeninfo *var,
531 struct fb_info *info);
532 extern void intelfbhw_do_blank(int blank, struct fb_info *info);
533 extern void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
534 unsigned red, unsigned green, unsigned blue,
535 unsigned transp);
536 extern int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
537 struct intelfb_hwstate *hw, int flag);
538 extern void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
539 struct intelfb_hwstate *hw);
540 extern int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
541 struct intelfb_hwstate *hw,
542 struct fb_var_screeninfo *var);
543 extern int intelfbhw_program_mode(struct intelfb_info *dinfo,
544 const struct intelfb_hwstate *hw, int blank);
545 extern void intelfbhw_do_sync(struct intelfb_info *dinfo);
546 extern void intelfbhw_2d_stop(struct intelfb_info *dinfo);
547 extern void intelfbhw_2d_start(struct intelfb_info *dinfo);
548 extern void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y,
549 u32 w, u32 h, u32 color, u32 pitch, u32 bpp,
550 u32 rop);
551 extern void intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
552 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch,
553 u32 bpp);
554 extern int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg,
555 u32 w, u32 h, const u8* cdat, u32 x, u32 y,
556 u32 pitch, u32 bpp);
557 extern void intelfbhw_cursor_init(struct intelfb_info *dinfo);
558 extern void intelfbhw_cursor_hide(struct intelfb_info *dinfo);
559 extern void intelfbhw_cursor_show(struct intelfb_info *dinfo);
560 extern void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y);
561 extern void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg,
562 u32 fg);
563 extern void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width,
564 int height, u8 *data);
565 extern void intelfbhw_cursor_reset(struct intelfb_info *dinfo);
566
567 #endif /* _INTELFBHW_H */
568
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