1 /*
2 * BRIEF MODULE DESCRIPTION
3 * Hardware definitions for the Au1100 LCD controller
4 *
5 * Copyright 2002 MontaVista Software
6 * Copyright 2002 Alchemy Semiconductor
7 * Author: Alchemy Semiconductor, MontaVista Software
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30 #ifndef _AU1100LCD_H
31 #define _AU1100LCD_H
32
33 #include <asm/mach-au1x00/au1000.h>
34
35 #define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
36 #define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
37 #define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
38
39 #if DEBUG
40 #define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg)
41 #else
42 #define print_dbg(f, arg...) do {} while (0)
43 #endif
44
45 #if defined(__BIG_ENDIAN)
46 #define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
47 #else
48 #define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
49 #endif
50 #define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
51
52 /********************************************************************/
53
54 /* LCD controller restrictions */
55 #define AU1100_LCD_MAX_XRES 800
56 #define AU1100_LCD_MAX_YRES 600
57 #define AU1100_LCD_MAX_BPP 16
58 #define AU1100_LCD_MAX_CLK 48000000
59 #define AU1100_LCD_NBR_PALETTE_ENTRIES 256
60
61 /* Default number of visible screen buffer to allocate */
62 #define AU1100FB_NBR_VIDEO_BUFFERS 4
63
64 /********************************************************************/
65
66 struct au1100fb_panel
67 {
68 const char name[25]; /* Full name <vendor>_<model> */
69
70 u32 control_base; /* Mode-independent control values */
71 u32 clkcontrol_base; /* Panel pixclock preferences */
72
73 u32 horztiming;
74 u32 verttiming;
75
76 u32 xres; /* Maximum horizontal resolution */
77 u32 yres; /* Maximum vertical resolution */
78 u32 bpp; /* Maximum depth supported */
79 };
80
81 struct au1100fb_regs
82 {
83 u32 lcd_control;
84 u32 lcd_intstatus;
85 u32 lcd_intenable;
86 u32 lcd_horztiming;
87 u32 lcd_verttiming;
88 u32 lcd_clkcontrol;
89 u32 lcd_dmaaddr0;
90 u32 lcd_dmaaddr1;
91 u32 lcd_words;
92 u32 lcd_pwmdiv;
93 u32 lcd_pwmhi;
94 u32 reserved[(0x0400-0x002C)/4];
95 u32 lcd_pallettebase[256];
96 };
97
98 struct au1100fb_device {
99
100 struct fb_info info; /* FB driver info record */
101
102 struct au1100fb_panel *panel; /* Panel connected to this device */
103
104 struct au1100fb_regs* regs; /* Registers memory map */
105 size_t regs_len;
106 unsigned int regs_phys;
107
108 unsigned char* fb_mem; /* FrameBuffer memory map */
109 size_t fb_len;
110 dma_addr_t fb_phys;
111 };
112
113 /********************************************************************/
114
115 #define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
116 #define LCD_CONTROL_SBB_BIT 21
117 #define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
118 #define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
119 #define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
120 #define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
121 #define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
122 #define LCD_CONTROL_SBPPF_BIT 18
123 #define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
124 #define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
125 #define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
126 #define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
127 #define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
128 #define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
129 #define LCD_CONTROL_WP (1<<17)
130 #define LCD_CONTROL_WD (1<<16)
131 #define LCD_CONTROL_C (1<<15)
132 #define LCD_CONTROL_SM_BIT 13
133 #define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
134 #define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
135 #define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
136 #define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
137 #define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
138 #define LCD_CONTROL_DB (1<<12)
139 #define LCD_CONTROL_CCO (1<<11)
140 #define LCD_CONTROL_DP (1<<10)
141 #define LCD_CONTROL_PO_BIT 8
142 #define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
143 #define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
144 #define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
145 #define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
146 #define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
147 #define LCD_CONTROL_MPI (1<<7)
148 #define LCD_CONTROL_PT (1<<6)
149 #define LCD_CONTROL_PC (1<<5)
150 #define LCD_CONTROL_BPP_BIT 1
151 #define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
152 #define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
153 #define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
154 #define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
155 #define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
156 #define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
157 #define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
158 #define LCD_CONTROL_GO (1<<0)
159
160 #define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
161 #define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
162 #define LCD_INT_SD (1<<7)
163 #define LCD_INT_OF (1<<6)
164 #define LCD_INT_UF (1<<5)
165 #define LCD_INT_SA (1<<3)
166 #define LCD_INT_SS (1<<2)
167 #define LCD_INT_S1 (1<<1)
168 #define LCD_INT_S0 (1<<0)
169
170 #define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
171 #define LCD_HORZTIMING_HN2_BIT 24
172 #define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
173 #define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
174 #define LCD_HORZTIMING_HN1_BIT 16
175 #define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
176 #define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
177 #define LCD_HORZTIMING_HPW_BIT 10
178 #define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
179 #define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
180 #define LCD_HORZTIMING_PPL_BIT 0
181 #define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
182 #define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
183
184 #define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
185 #define LCD_VERTTIMING_VN2_BIT 24
186 #define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
187 #define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
188 #define LCD_VERTTIMING_VN1_BIT 16
189 #define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
190 #define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
191 #define LCD_VERTTIMING_VPW_BIT 10
192 #define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
193 #define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
194 #define LCD_VERTTIMING_LPP_BIT 0
195 #define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
196 #define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
197
198 #define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
199 #define LCD_CLKCONTROL_IB (1<<18)
200 #define LCD_CLKCONTROL_IC (1<<17)
201 #define LCD_CLKCONTROL_IH (1<<16)
202 #define LCD_CLKCONTROL_IV (1<<15)
203 #define LCD_CLKCONTROL_BF_BIT 10
204 #define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
205 #define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
206 #define LCD_CLKCONTROL_PCD_BIT 0
207 #define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
208 #define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
209
210 #define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
211 #define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
212 #define LCD_DMA_SA_BIT 5
213 #define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
214 #define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
215
216 #define LCD_WORDS (AU1100_LCD_BASE + 0x20)
217 #define LCD_WRD_WRDS_BIT 0
218 #define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
219 #define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
220
221 #define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
222 #define LCD_PWMDIV_EN (1<<12)
223 #define LCD_PWMDIV_PWMDIV_BIT 0
224 #define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
225 #define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
226
227 #define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
228 #define LCD_PWMHI_PWMHI1_BIT 12
229 #define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
230 #define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
231 #define LCD_PWMHI_PWMHI0_BIT 0
232 #define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
233 #define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
234
235 #define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
236 #define LCD_PALLETTE_MONO_MI_BIT 0
237 #define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
238 #define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
239
240 #define LCD_PALLETTE_COLOR_RI_BIT 8
241 #define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
242 #define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
243 #define LCD_PALLETTE_COLOR_GI_BIT 4
244 #define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
245 #define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
246 #define LCD_PALLETTE_COLOR_BI_BIT 0
247 #define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
248 #define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
249
250 #define LCD_PALLETTE_TFT_DC_BIT 0
251 #define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
252 #define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
253
254 /********************************************************************/
255
256 /* List of panels known to work with the AU1100 LCD controller.
257 * To add a new panel, enter the same specifications as the
258 * Generic_TFT one, and MAKE SURE that it doesn't conflicts
259 * with the controller restrictions. Restrictions are:
260 *
261 * STN color panels: max_bpp <= 12
262 * STN mono panels: max_bpp <= 4
263 * TFT panels: max_bpp <= 16
264 * max_xres <= 800
265 * max_yres <= 600
266 */
267 static struct au1100fb_panel known_lcd_panels[] =
268 {
269 /* 800x600x16bpp CRT */
270 [0] = {
271 .name = "CRT_800x600_16",
272 .xres = 800,
273 .yres = 600,
274 .bpp = 16,
275 .control_base = 0x0004886A |
276 LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
277 LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4,
278 .clkcontrol_base = 0x00020000,
279 .horztiming = 0x005aff1f,
280 .verttiming = 0x16000e57,
281 },
282 /* just the standard LCD */
283 [1] = {
284 .name = "WWPC LCD",
285 .xres = 240,
286 .yres = 320,
287 .bpp = 16,
288 .control_base = 0x0006806A,
289 .horztiming = 0x0A1010EF,
290 .verttiming = 0x0301013F,
291 .clkcontrol_base = 0x00018001,
292 },
293 /* Sharp 320x240 TFT panel */
294 [2] = {
295 .name = "Sharp_LQ038Q5DR01",
296 .xres = 320,
297 .yres = 240,
298 .bpp = 16,
299 .control_base =
300 ( LCD_CONTROL_SBPPF_565
301 | LCD_CONTROL_C
302 | LCD_CONTROL_SM_0
303 | LCD_CONTROL_DEFAULT_PO
304 | LCD_CONTROL_PT
305 | LCD_CONTROL_PC
306 | LCD_CONTROL_BPP_16 ),
307 .horztiming =
308 ( LCD_HORZTIMING_HN2_N(8)
309 | LCD_HORZTIMING_HN1_N(60)
310 | LCD_HORZTIMING_HPW_N(12)
311 | LCD_HORZTIMING_PPL_N(320) ),
312 .verttiming =
313 ( LCD_VERTTIMING_VN2_N(5)
314 | LCD_VERTTIMING_VN1_N(17)
315 | LCD_VERTTIMING_VPW_N(1)
316 | LCD_VERTTIMING_LPP_N(240) ),
317 .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
318 },
319
320 /* Hitachi SP14Q005 and possibly others */
321 [3] = {
322 .name = "Hitachi_SP14Qxxx",
323 .xres = 320,
324 .yres = 240,
325 .bpp = 4,
326 .control_base =
327 ( LCD_CONTROL_C
328 | LCD_CONTROL_BPP_4 ),
329 .horztiming =
330 ( LCD_HORZTIMING_HN2_N(1)
331 | LCD_HORZTIMING_HN1_N(1)
332 | LCD_HORZTIMING_HPW_N(1)
333 | LCD_HORZTIMING_PPL_N(320) ),
334 .verttiming =
335 ( LCD_VERTTIMING_VN2_N(1)
336 | LCD_VERTTIMING_VN1_N(1)
337 | LCD_VERTTIMING_VPW_N(1)
338 | LCD_VERTTIMING_LPP_N(240) ),
339 .clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
340 },
341
342 /* Generic 640x480 TFT panel */
343 [4] = {
344 .name = "TFT_640x480_16",
345 .xres = 640,
346 .yres = 480,
347 .bpp = 16,
348 .control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
349 .horztiming = 0x3434d67f,
350 .verttiming = 0x0e0e39df,
351 .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
352 },
353
354 /* Pb1100 LCDB 640x480 PrimeView TFT panel */
355 [5] = {
356 .name = "PrimeView_640x480_16",
357 .xres = 640,
358 .yres = 480,
359 .bpp = 16,
360 .control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
361 .horztiming = 0x0e4bfe7f,
362 .verttiming = 0x210805df,
363 .clkcontrol_base = 0x00038001,
364 },
365 };
366
367 struct au1100fb_drv_info {
368 int panel_idx;
369 char *opt_mode;
370 };
371
372 /********************************************************************/
373
374 /* Inline helpers */
375
376 #define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
377 #define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
378 #define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
379 #define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
380
381 #endif /* _AU1100LCD_H */
382
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