1
2 /*
3 * ATI Mach64 CT/VT/GT/LT Support
4 */
5
6 #include <linux/fb.h>
7 #include <linux/delay.h>
8 #include <asm/io.h>
9 #include <video/mach64.h>
10 #include "atyfb.h"
11
12 #undef DEBUG
13
14 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
15 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
16 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
17 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
18
19 u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par)
20 {
21 u8 res;
22
23 /* write addr byte */
24 aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par);
25 /* read the register value */
26 res = aty_ld_8(CLOCK_CNTL_DATA, par);
27 return res;
28 }
29
30 void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par)
31 {
32 /* write addr byte */
33 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par);
34 /* write the register value */
35 aty_st_8(CLOCK_CNTL_DATA, val & PLL_DATA, par);
36 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par);
37 }
38
39 /*
40 * by Daniel Mantione
41 * <daniel.mantione@freepascal.org>
42 *
43 *
44 * ATI Mach64 CT clock synthesis description.
45 *
46 * All clocks on the Mach64 can be calculated using the same principle:
47 *
48 * XTALIN * x * FB_DIV
49 * CLK = ----------------------
50 * PLL_REF_DIV * POST_DIV
51 *
52 * XTALIN is a fixed speed clock. Common speeds are 14.31 MHz and 29.50 MHz.
53 * PLL_REF_DIV can be set by the user, but is the same for all clocks.
54 * FB_DIV can be set by the user for each clock individually, it should be set
55 * between 128 and 255, the chip will generate a bad clock signal for too low
56 * values.
57 * x depends on the type of clock; usually it is 2, but for the MCLK it can also
58 * be set to 4.
59 * POST_DIV can be set by the user for each clock individually, Possible values
60 * are 1,2,4,8 and for some clocks other values are available too.
61 * CLK is of course the clock speed that is generated.
62 *
63 * The Mach64 has these clocks:
64 *
65 * MCLK The clock rate of the chip
66 * XCLK The clock rate of the on-chip memory
67 * VCLK0 First pixel clock of first CRT controller
68 * VCLK1 Second pixel clock of first CRT controller
69 * VCLK2 Third pixel clock of first CRT controller
70 * VCLK3 Fourth pixel clock of first CRT controller
71 * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3
72 * V2CLK Pixel clock of the second CRT controller.
73 * SCLK Multi-purpose clock
74 *
75 * - MCLK and XCLK use the same FB_DIV
76 * - VCLK0 .. VCLK3 use the same FB_DIV
77 * - V2CLK is needed when the second CRTC is used (can be used for dualhead);
78 * i.e. CRT monitor connected to laptop has different resolution than built
79 * in LCD monitor.
80 * - SCLK is not available on all cards; it is know to exist on the Rage LT-PRO,
81 * Rage XL and Rage Mobility. It is know not to exist on the Mach64 VT.
82 * - V2CLK is not available on all cards, most likely only the Rage LT-PRO,
83 * the Rage XL and the Rage Mobility
84 *
85 * SCLK can be used to:
86 * - Clock the chip instead of MCLK
87 * - Replace XTALIN with a user defined frequency
88 * - Generate the pixel clock for the LCD monitor (instead of VCLK)
89 */
90
91 /*
92 * It can be quite hard to calculate XCLK and MCLK if they don't run at the
93 * same frequency. Luckily, until now all cards that need asynchrone clock
94 * speeds seem to have SCLK.
95 * So this driver uses SCLK to clock the chip and XCLK to clock the memory.
96 */
97
98 /* ------------------------------------------------------------------------- */
99
100 /*
101 * PLL programming (Mach64 CT family)
102 *
103 *
104 * This procedure sets the display fifo. The display fifo is a buffer that
105 * contains data read from the video memory that waits to be processed by
106 * the CRT controller.
107 *
108 * On the more modern Mach64 variants, the chip doesn't calculate the
109 * interval after which the display fifo has to be reloaded from memory
110 * automatically, the driver has to do it instead.
111 */
112
113 #define Maximum_DSP_PRECISION 7
114 static u8 postdividers[] = {1,2,4,8,3};
115
116 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll)
117 {
118 u32 dsp_off, dsp_on, dsp_xclks;
119 u32 multiplier, divider, ras_multiplier, ras_divider, tmp;
120 u8 vshift, xshift;
121 s8 dsp_precision;
122
123 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real;
124 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div;
125
126 ras_multiplier = pll->xclkmaxrasdelay;
127 ras_divider = 1;
128
129 if (bpp>=8)
130 divider = divider * (bpp >> 2);
131
132 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */
133
134 if (bpp == 0)
135 vshift--; /* ... but only 32 bits in VGA mode. */
136
137 #ifdef CONFIG_FB_ATY_GENERIC_LCD
138 if (pll->xres != 0) {
139 struct atyfb_par *par = (struct atyfb_par *) info->par;
140
141 multiplier = multiplier * par->lcd_width;
142 divider = divider * pll->xres & ~7;
143
144 ras_multiplier = ras_multiplier * par->lcd_width;
145 ras_divider = ras_divider * pll->xres & ~7;
146 }
147 #endif
148 /* If we don't do this, 32 bits for multiplier & divider won't be
149 enough in certain situations! */
150 while (((multiplier | divider) & 1) == 0) {
151 multiplier = multiplier >> 1;
152 divider = divider >> 1;
153 }
154
155 /* Determine DSP precision first */
156 tmp = ((multiplier * pll->fifo_size) << vshift) / divider;
157
158 for (dsp_precision = -5; tmp; dsp_precision++)
159 tmp >>= 1;
160 if (dsp_precision < 0)
161 dsp_precision = 0;
162 else if (dsp_precision > Maximum_DSP_PRECISION)
163 dsp_precision = Maximum_DSP_PRECISION;
164
165 xshift = 6 - dsp_precision;
166 vshift += xshift;
167
168 /* Move on to dsp_off */
169 dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider -
170 (1 << (vshift - xshift));
171
172 /* if (bpp == 0)
173 dsp_on = ((multiplier * 20 << vshift) + divider) / divider;
174 else */
175 {
176 dsp_on = ((multiplier << vshift) + divider) / divider;
177 tmp = ((ras_multiplier << xshift) + ras_divider) / ras_divider;
178 if (dsp_on < tmp)
179 dsp_on = tmp;
180 dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift);
181 }
182
183 /* Calculate rounding factor and apply it to dsp_on */
184 tmp = ((1 << (Maximum_DSP_PRECISION - dsp_precision)) - 1) >> 1;
185 dsp_on = ((dsp_on + tmp) / (tmp + 1)) * (tmp + 1);
186
187 if (dsp_on >= ((dsp_off / (tmp + 1)) * (tmp + 1))) {
188 dsp_on = dsp_off - (multiplier << vshift) / divider;
189 dsp_on = (dsp_on / (tmp + 1)) * (tmp + 1);
190 }
191
192 /* Last but not least: dsp_xclks */
193 dsp_xclks = ((multiplier << (vshift + 5)) + divider) / divider;
194
195 /* Get register values. */
196 pll->dsp_on_off = (dsp_on << 16) + dsp_off;
197 pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks;
198 #ifdef DEBUG
199 printk("atyfb(%s): dsp_config 0x%08x, dsp_on_off 0x%08x\n",
200 __FUNCTION__, pll->dsp_config, pll->dsp_on_off);
201 #endif
202 return 0;
203 }
204
205 static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll)
206 {
207 u32 q;
208 struct atyfb_par *par = (struct atyfb_par *) info->par;
209 #ifdef DEBUG
210 int pllvclk;
211 #endif
212
213 /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */
214 q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per;
215 if (q < 16*8 || q > 255*8) {
216 printk(KERN_CRIT "atyfb: vclk out of range\n");
217 return -EINVAL;
218 } else {
219 pll->vclk_post_div = (q < 128*8);
220 pll->vclk_post_div += (q < 64*8);
221 pll->vclk_post_div += (q < 32*8);
222 }
223 pll->vclk_post_div_real = postdividers[pll->vclk_post_div];
224 // pll->vclk_post_div <<= 6;
225 pll->vclk_fb_div = q * pll->vclk_post_div_real / 8;
226 #ifdef DEBUG
227 pllvclk = (1000000 * 2 * pll->vclk_fb_div) /
228 (par->ref_clk_per * pll->pll_ref_div);
229 printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n",
230 __FUNCTION__, pllvclk, pllvclk / pll->vclk_post_div_real);
231 #endif
232 pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */
233 return 0;
234 }
235
236 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll)
237 {
238 struct atyfb_par *par = (struct atyfb_par *) info->par;
239 int err;
240
241 if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
242 return err;
243 if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
244 return err;
245 /*aty_calc_pll_ct(info, &pll->ct);*/
246 return 0;
247 }
248
249 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll)
250 {
251 struct atyfb_par *par = (struct atyfb_par *) info->par;
252 u32 ret;
253 ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
254 #ifdef CONFIG_FB_ATY_GENERIC_LCD
255 if(pll->ct.xres > 0) {
256 ret *= par->lcd_width;
257 ret /= pll->ct.xres;
258 }
259 #endif
260 #ifdef DEBUG
261 printk("atyfb(%s): calculated 0x%08X(%i)\n", __FUNCTION__, ret, ret);
262 #endif
263 return ret;
264 }
265
266 void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll)
267 {
268 struct atyfb_par *par = (struct atyfb_par *) info->par;
269 u32 crtc_gen_cntl, lcd_gen_cntrl;
270 u8 tmp, tmp2;
271
272 lcd_gen_cntrl = 0;
273 #ifdef DEBUG
274 printk("atyfb(%s): about to program:\n"
275 "pll_ext_cntl=0x%02x pll_gen_cntl=0x%02x pll_vclk_cntl=0x%02x\n",
276 __FUNCTION__,
277 pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl);
278
279 printk("atyfb(%s): setting clock %lu for FeedBackDivider %i, ReferenceDivider %i, PostDivider %i(%i)\n",
280 __FUNCTION__,
281 par->clk_wr_offset, pll->ct.vclk_fb_div,
282 pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real);
283 #endif
284 #ifdef CONFIG_FB_ATY_GENERIC_LCD
285 if (par->lcd_table != 0) {
286 /* turn off LCD */
287 lcd_gen_cntrl = aty_ld_lcd(LCD_GEN_CNTL, par);
288 aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl & ~LCD_ON, par);
289 }
290 #endif
291 aty_st_8(CLOCK_CNTL, par->clk_wr_offset | CLOCK_STROBE, par);
292
293 /* Temporarily switch to accelerator mode */
294 crtc_gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
295 if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN))
296 aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN, par);
297
298 /* Reset VCLK generator */
299 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
300
301 /* Set post-divider */
302 tmp2 = par->clk_wr_offset << 1;
303 tmp = aty_ld_pll_ct(VCLK_POST_DIV, par);
304 tmp &= ~(0x03U << tmp2);
305 tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2);
306 aty_st_pll_ct(VCLK_POST_DIV, tmp, par);
307
308 /* Set extended post-divider */
309 tmp = aty_ld_pll_ct(PLL_EXT_CNTL, par);
310 tmp &= ~(0x10U << par->clk_wr_offset);
311 tmp &= 0xF0U;
312 tmp |= pll->ct.pll_ext_cntl;
313 aty_st_pll_ct(PLL_EXT_CNTL, tmp, par);
314
315 /* Set feedback divider */
316 tmp = VCLK0_FB_DIV + par->clk_wr_offset;
317 aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
318
319 aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
320
321 /* End VCLK generator reset */
322 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
323 mdelay(5);
324
325 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
326 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
327 mdelay(1);
328
329 /* Restore mode register */
330 if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN))
331 aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl, par);
332
333 if (M64_HAS(GTB_DSP)) {
334 u8 dll_cntl;
335
336 if (M64_HAS(XL_DLL))
337 dll_cntl = 0x80;
338 else if (par->ram_type >= SDRAM)
339 dll_cntl = 0xa6;
340 else
341 dll_cntl = 0xa0;
342 aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
343 aty_st_pll_ct(VFC_CNTL, 0x1b, par);
344 aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
345 aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
346
347 mdelay(10);
348 aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
349 mdelay(10);
350 aty_st_pll_ct(DLL_CNTL, dll_cntl | 0x40, par);
351 mdelay(10);
352 aty_st_pll_ct(DLL_CNTL, dll_cntl & ~0x40, par);
353 }
354 #ifdef CONFIG_FB_ATY_GENERIC_LCD
355 if (par->lcd_table != 0) {
356 /* restore LCD */
357 aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl, par);
358 }
359 #endif
360 }
361
362 void __init aty_get_pll_ct(const struct fb_info *info, union aty_pll *pll)
363 {
364 struct atyfb_par *par = (struct atyfb_par *) info->par;
365 u8 tmp, clock;
366
367 clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
368 tmp = clock << 1;
369 pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
370
371 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
372 pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
373 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
374 pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
375
376 pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
377 pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
378
379 if (M64_HAS(GTB_DSP)) {
380 pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
381 pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
382 }
383 }
384
385 int __init aty_init_pll_ct(const struct fb_info *info, union aty_pll *pll) {
386 struct atyfb_par *par = (struct atyfb_par *) info->par;
387 u8 mpost_div, xpost_div, sclk_post_div_real, sclk_fb_div, spll_cntl2;
388 u32 q, i, memcntl, trp;
389 u32 dsp_config, dsp_on_off, vga_dsp_config, vga_dsp_on_off;
390 #ifdef DEBUG
391 int pllmclk, pllsclk;
392 #endif
393 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
394 pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07;
395 pll->ct.xclk_ref_div = 1;
396 switch (pll->ct.xclk_post_div) {
397 case 0: case 1: case 2: case 3:
398 break;
399
400 case 4:
401 pll->ct.xclk_ref_div = 3;
402 pll->ct.xclk_post_div = 0;
403 break;
404
405 default:
406 printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div);
407 return -EINVAL;
408 }
409 pll->ct.mclk_fb_mult = 2;
410 if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) {
411 pll->ct.mclk_fb_mult = 4;
412 pll->ct.xclk_post_div -= 1;
413 }
414
415 #ifdef DEBUG
416 printk("atyfb(%s): mclk_fb_mult=%d, xclk_post_div=%d\n",
417 __FUNCTION__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div);
418 #endif
419
420 memcntl = aty_ld_le32(MEM_CNTL, par);
421 trp = (memcntl & 0x300) >> 8;
422
423 pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2;
424 pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2;
425
426 if (M64_HAS(FIFO_32)) {
427 pll->ct.fifo_size = 32;
428 } else {
429 pll->ct.fifo_size = 24;
430 pll->ct.xclkpagefaultdelay += 2;
431 pll->ct.xclkmaxrasdelay += 3;
432 }
433
434 switch (par->ram_type) {
435 case DRAM:
436 if (info->fix.smem_len<=ONE_MB) {
437 pll->ct.dsp_loop_latency = 10;
438 } else {
439 pll->ct.dsp_loop_latency = 8;
440 pll->ct.xclkpagefaultdelay += 2;
441 }
442 break;
443 case EDO:
444 case PSEUDO_EDO:
445 if (info->fix.smem_len<=ONE_MB) {
446 pll->ct.dsp_loop_latency = 9;
447 } else {
448 pll->ct.dsp_loop_latency = 8;
449 pll->ct.xclkpagefaultdelay += 1;
450 }
451 break;
452 case SDRAM:
453 if (info->fix.smem_len<=ONE_MB) {
454 pll->ct.dsp_loop_latency = 11;
455 } else {
456 pll->ct.dsp_loop_latency = 10;
457 pll->ct.xclkpagefaultdelay += 1;
458 }
459 break;
460 case SGRAM:
461 pll->ct.dsp_loop_latency = 8;
462 pll->ct.xclkpagefaultdelay += 3;
463 break;
464 default:
465 pll->ct.dsp_loop_latency = 11;
466 pll->ct.xclkpagefaultdelay += 3;
467 break;
468 }
469
470 if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay)
471 pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1;
472
473 /* Allow BIOS to override */
474 dsp_config = aty_ld_le32(DSP_CONFIG, par);
475 dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
476 vga_dsp_config = aty_ld_le32(VGA_DSP_CONFIG, par);
477 vga_dsp_on_off = aty_ld_le32(VGA_DSP_ON_OFF, par);
478
479 if (dsp_config)
480 pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16;
481 #if 0
482 FIXME: is it relevant for us?
483 if ((!dsp_on_off && !M64_HAS(RESET_3D)) ||
484 ((dsp_on_off == vga_dsp_on_off) &&
485 (!dsp_config || !((dsp_config ^ vga_dsp_config) & DSP_XCLKS_PER_QW)))) {
486 vga_dsp_on_off &= VGA_DSP_OFF;
487 vga_dsp_config &= VGA_DSP_XCLKS_PER_QW;
488 if (ATIDivide(vga_dsp_on_off, vga_dsp_config, 5, 1) > 24)
489 pll->ct.fifo_size = 32;
490 else
491 pll->ct.fifo_size = 24;
492 }
493 #endif
494 /* Exit if the user does not want us to tamper with the clock
495 rates of her chip. */
496 if (par->mclk_per == 0) {
497 u8 mclk_fb_div, pll_ext_cntl;
498 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
499 pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
500 pll->ct.xclk_post_div_real = postdividers[pll_ext_cntl & 0x07];
501 mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
502 if (pll_ext_cntl & PLL_MFB_TIMES_4_2B)
503 mclk_fb_div <<= 1;
504 pll->ct.mclk_fb_div = mclk_fb_div;
505 return 0;
506 }
507
508 pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
509
510 /* FIXME: use the VTB/GTB /3 post divider if it's better suited */
511 q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
512 (pll->ct.mclk_fb_mult * par->xclk_per);
513
514 if (q < 16*8 || q > 255*8) {
515 printk(KERN_CRIT "atxfb: xclk out of range\n");
516 return -EINVAL;
517 } else {
518 xpost_div = (q < 128*8);
519 xpost_div += (q < 64*8);
520 xpost_div += (q < 32*8);
521 }
522 pll->ct.xclk_post_div_real = postdividers[xpost_div];
523 pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8;
524
525 #ifdef DEBUG
526 pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) /
527 (par->ref_clk_per * pll->ct.pll_ref_div);
528 printk("atyfb(%s): pllmclk=%d MHz, xclk=%d MHz\n",
529 __FUNCTION__, pllmclk, pllmclk / pll->ct.xclk_post_div_real);
530 #endif
531
532 if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM))
533 pll->ct.pll_gen_cntl = OSC_EN;
534 else
535 pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */;
536
537 if (M64_HAS(MAGIC_POSTDIV))
538 pll->ct.pll_ext_cntl = 0;
539 else
540 pll->ct.pll_ext_cntl = xpost_div;
541
542 if (pll->ct.mclk_fb_mult == 4)
543 pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B;
544
545 if (par->mclk_per == par->xclk_per) {
546 pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */
547 } else {
548 /*
549 * The chip clock is not equal to the memory clock.
550 * Therefore we will use sclk to clock the chip.
551 */
552 pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */
553
554 q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
555 if (q < 16*8 || q > 255*8) {
556 printk(KERN_CRIT "atyfb: mclk out of range\n");
557 return -EINVAL;
558 } else {
559 mpost_div = (q < 128*8);
560 mpost_div += (q < 64*8);
561 mpost_div += (q < 32*8);
562 }
563 sclk_post_div_real = postdividers[mpost_div];
564 sclk_fb_div = q * sclk_post_div_real / 8;
565 spll_cntl2 = mpost_div << 4;
566 #ifdef DEBUG
567 pllsclk = (1000000 * 2 * sclk_fb_div) /
568 (par->ref_clk_per * pll->ct.pll_ref_div);
569 printk("atyfb(%s): use sclk, pllsclk=%d MHz, sclk=mclk=%d MHz\n",
570 __FUNCTION__, pllsclk, pllsclk / sclk_post_div_real);
571 #endif
572 /*
573 * This disables the sclk, crashes the computer as reported:
574 * aty_st_pll_ct(SPLL_CNTL2, 3, info);
575 *
576 * So it seems the sclk must be enabled before it is used;
577 * so PLL_GEN_CNTL must be programmed *after* the sclk.
578 */
579 aty_st_pll_ct(SCLK_FB_DIV, sclk_fb_div, par);
580 aty_st_pll_ct(SPLL_CNTL2, spll_cntl2, par);
581 /*
582 * The sclk has been started. However, I believe the first clock
583 * ticks it generates are not very stable. Hope this primitive loop
584 * helps for Rage Mobilities that sometimes crash when
585 * we switch to sclk. (Daniel Mantione, 13-05-2003)
586 */
587 for (i=0;i<=0x1ffff;i++);
588 }
589
590 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
591 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
592 aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
593 aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
594 /* Disable the extra precision pixel clock controls since we do not use them. */
595 aty_st_pll_ct(EXT_VPLL_CNTL, aty_ld_pll_ct(EXT_VPLL_CNTL, par) &
596 ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC), par);
597
598 return 0;
599 }
600
601 static int dummy(void)
602 {
603 return 0;
604 }
605
606 const struct aty_dac_ops aty_dac_ct = {
607 .set_dac = (void *) dummy,
608 };
609
610 const struct aty_pll_ops aty_pll_ct = {
611 .var_to_pll = aty_var_to_pll_ct,
612 .pll_to_var = aty_pll_to_var_ct,
613 .set_pll = aty_set_pll_ct,
614 .get_pll = aty_get_pll_ct,
615 .init_pll = aty_init_pll_ct
616 };
617
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