1 /*
2 * ATI Frame Buffer Device Driver Core Definitions
3 */
4
5 #include <linux/spinlock.h>
6 #include <linux/wait.h>
7 /*
8 * Elements of the hardware specific atyfb_par structure
9 */
10
11 struct crtc {
12 u32 vxres;
13 u32 vyres;
14 u32 xoffset;
15 u32 yoffset;
16 u32 bpp;
17 u32 h_tot_disp;
18 u32 h_sync_strt_wid;
19 u32 v_tot_disp;
20 u32 v_sync_strt_wid;
21 u32 vline_crnt_vline;
22 u32 off_pitch;
23 u32 gen_cntl;
24 u32 dp_pix_width; /* acceleration */
25 u32 dp_chain_mask; /* acceleration */
26 #ifdef CONFIG_FB_ATY_GENERIC_LCD
27 u32 horz_stretching;
28 u32 vert_stretching;
29 u32 ext_vert_stretch;
30 u32 shadow_h_tot_disp;
31 u32 shadow_h_sync_strt_wid;
32 u32 shadow_v_tot_disp;
33 u32 shadow_v_sync_strt_wid;
34 u32 lcd_gen_cntl;
35 u32 lcd_config_panel;
36 u32 lcd_index;
37 #endif
38 };
39
40 struct aty_interrupt {
41 wait_queue_head_t wait;
42 unsigned int count;
43 int pan_display;
44 };
45
46 struct pll_info {
47 int pll_max;
48 int pll_min;
49 int sclk, mclk, mclk_pm, xclk;
50 int ref_div;
51 int ref_clk;
52 int ecp_max;
53 };
54
55 typedef struct {
56 u16 unknown1;
57 u16 PCLK_min_freq;
58 u16 PCLK_max_freq;
59 u16 unknown2;
60 u16 ref_freq;
61 u16 ref_divider;
62 u16 unknown3;
63 u16 MCLK_pwd;
64 u16 MCLK_max_freq;
65 u16 XCLK_max_freq;
66 u16 SCLK_freq;
67 } __attribute__ ((packed)) PLL_BLOCK_MACH64;
68
69 struct pll_514 {
70 u8 m;
71 u8 n;
72 };
73
74 struct pll_18818 {
75 u32 program_bits;
76 u32 locationAddr;
77 u32 period_in_ps;
78 u32 post_divider;
79 };
80
81 struct pll_ct {
82 u8 pll_ref_div;
83 u8 pll_gen_cntl;
84 u8 mclk_fb_div;
85 u8 mclk_fb_mult; /* 2 ro 4 */
86 u8 sclk_fb_div;
87 u8 pll_vclk_cntl;
88 u8 vclk_post_div;
89 u8 vclk_fb_div;
90 u8 pll_ext_cntl;
91 u8 ext_vpll_cntl;
92 u8 spll_cntl2;
93 u32 dsp_config; /* Mach64 GTB DSP */
94 u32 dsp_on_off; /* Mach64 GTB DSP */
95 u32 dsp_loop_latency;
96 u32 fifo_size;
97 u32 xclkpagefaultdelay;
98 u32 xclkmaxrasdelay;
99 u8 xclk_ref_div;
100 u8 xclk_post_div;
101 u8 mclk_post_div_real;
102 u8 xclk_post_div_real;
103 u8 vclk_post_div_real;
104 u8 features;
105 #ifdef CONFIG_FB_ATY_GENERIC_LCD
106 u32 xres; /* use for LCD stretching/scaling */
107 #endif
108 };
109
110 /*
111 for pll_ct.features
112 */
113 #define DONT_USE_SPLL 0x1
114 #define DONT_USE_XDLL 0x2
115 #define USE_CPUCLK 0x4
116 #define POWERDOWN_PLL 0x8
117
118 union aty_pll {
119 struct pll_ct ct;
120 struct pll_514 ibm514;
121 struct pll_18818 ics2595;
122 };
123
124 /*
125 * The hardware parameters for each card
126 */
127
128 struct atyfb_par {
129 u32 pseudo_palette[16];
130 struct { u8 red, green, blue; } palette[256];
131 const struct aty_dac_ops *dac_ops;
132 const struct aty_pll_ops *pll_ops;
133 void __iomem *ati_regbase;
134 unsigned long clk_wr_offset; /* meaning overloaded, clock id by CT */
135 struct crtc crtc;
136 union aty_pll pll;
137 struct pll_info pll_limits;
138 u32 features;
139 u32 ref_clk_per;
140 u32 pll_per;
141 u32 mclk_per;
142 u32 xclk_per;
143 u8 bus_type;
144 u8 ram_type;
145 u8 mem_refresh_rate;
146 u16 pci_id;
147 u32 accel_flags;
148 int blitter_may_be_busy;
149 int asleep;
150 int lock_blank;
151 unsigned long res_start;
152 unsigned long res_size;
153 struct pci_dev *pdev;
154 #ifdef __sparc__
155 struct pci_mmap_map *mmap_map;
156 u8 mmaped;
157 #endif
158 int open;
159 #ifdef CONFIG_FB_ATY_GENERIC_LCD
160 unsigned long bios_base_phys;
161 unsigned long bios_base;
162 unsigned long lcd_table;
163 u16 lcd_width;
164 u16 lcd_height;
165 u32 lcd_pixclock;
166 u16 lcd_refreshrate;
167 u16 lcd_htotal;
168 u16 lcd_hdisp;
169 u16 lcd_hsync_dly;
170 u16 lcd_hsync_len;
171 u16 lcd_vtotal;
172 u16 lcd_vdisp;
173 u16 lcd_vsync_len;
174 u16 lcd_right_margin;
175 u16 lcd_lower_margin;
176 u16 lcd_hblank_len;
177 u16 lcd_vblank_len;
178 #endif
179 unsigned long aux_start; /* auxiliary aperture */
180 unsigned long aux_size;
181 struct aty_interrupt vblank;
182 unsigned long irq_flags;
183 unsigned int irq;
184 spinlock_t int_lock;
185 #ifdef CONFIG_MTRR
186 int mtrr_aper;
187 int mtrr_reg;
188 #endif
189 u32 mem_cntl;
190 struct crtc saved_crtc;
191 union aty_pll saved_pll;
192 };
193
194 /*
195 * ATI Mach64 features
196 */
197
198 #define M64_HAS(feature) ((par)->features & (M64F_##feature))
199
200 #define M64F_RESET_3D 0x00000001
201 #define M64F_MAGIC_FIFO 0x00000002
202 #define M64F_GTB_DSP 0x00000004
203 #define M64F_FIFO_32 0x00000008
204 #define M64F_SDRAM_MAGIC_PLL 0x00000010
205 #define M64F_MAGIC_POSTDIV 0x00000020
206 #define M64F_INTEGRATED 0x00000040
207 #define M64F_CT_BUS 0x00000080
208 #define M64F_VT_BUS 0x00000100
209 #define M64F_MOBIL_BUS 0x00000200
210 #define M64F_GX 0x00000400
211 #define M64F_CT 0x00000800
212 #define M64F_VT 0x00001000
213 #define M64F_GT 0x00002000
214 #define M64F_MAGIC_VRAM_SIZE 0x00004000
215 #define M64F_G3_PB_1_1 0x00008000
216 #define M64F_G3_PB_1024x768 0x00010000
217 #define M64F_EXTRA_BRIGHT 0x00020000
218 #define M64F_LT_LCD_REGS 0x00040000
219 #define M64F_XL_DLL 0x00080000
220 #define M64F_MFB_FORCE_4 0x00100000
221 #define M64F_HW_TRIPLE 0x00200000
222 #define M64F_XL_MEM 0x00400000
223 /*
224 * Register access
225 */
226
227 static inline u32 aty_ld_le32(int regindex, const struct atyfb_par *par)
228 {
229 /* Hack for bloc 1, should be cleanly optimized by compiler */
230 if (regindex >= 0x400)
231 regindex -= 0x800;
232
233 #ifdef CONFIG_ATARI
234 return in_le32(par->ati_regbase + regindex);
235 #else
236 return readl(par->ati_regbase + regindex);
237 #endif
238 }
239
240 static inline void aty_st_le32(int regindex, u32 val, const struct atyfb_par *par)
241 {
242 /* Hack for bloc 1, should be cleanly optimized by compiler */
243 if (regindex >= 0x400)
244 regindex -= 0x800;
245
246 #ifdef CONFIG_ATARI
247 out_le32(par->ati_regbase + regindex, val);
248 #else
249 writel(val, par->ati_regbase + regindex);
250 #endif
251 }
252
253 static inline void aty_st_le16(int regindex, u16 val,
254 const struct atyfb_par *par)
255 {
256 /* Hack for bloc 1, should be cleanly optimized by compiler */
257 if (regindex >= 0x400)
258 regindex -= 0x800;
259 #ifdef CONFIG_ATARI
260 out_le16(par->ati_regbase + regindex, val);
261 #else
262 writel(val, par->ati_regbase + regindex);
263 #endif
264 }
265
266 static inline u8 aty_ld_8(int regindex, const struct atyfb_par *par)
267 {
268 /* Hack for bloc 1, should be cleanly optimized by compiler */
269 if (regindex >= 0x400)
270 regindex -= 0x800;
271 #ifdef CONFIG_ATARI
272 return in_8(par->ati_regbase + regindex);
273 #else
274 return readb(par->ati_regbase + regindex);
275 #endif
276 }
277
278 static inline void aty_st_8(int regindex, u8 val, const struct atyfb_par *par)
279 {
280 /* Hack for bloc 1, should be cleanly optimized by compiler */
281 if (regindex >= 0x400)
282 regindex -= 0x800;
283
284 #ifdef CONFIG_ATARI
285 out_8(par->ati_regbase + regindex, val);
286 #else
287 writeb(val, par->ati_regbase + regindex);
288 #endif
289 }
290
291 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
292 defined (CONFIG_FB_ATY_GENERIC_LCD) || defined (CONFIG_FB_ATY_BACKLIGHT)
293 extern void aty_st_lcd(int index, u32 val, const struct atyfb_par *par);
294 extern u32 aty_ld_lcd(int index, const struct atyfb_par *par);
295 #endif
296
297 /*
298 * DAC operations
299 */
300
301 struct aty_dac_ops {
302 int (*set_dac) (const struct fb_info * info,
303 const union aty_pll * pll, u32 bpp, u32 accel);
304 };
305
306 extern const struct aty_dac_ops aty_dac_ibm514; /* IBM RGB514 */
307 extern const struct aty_dac_ops aty_dac_ati68860b; /* ATI 68860-B */
308 extern const struct aty_dac_ops aty_dac_att21c498; /* AT&T 21C498 */
309 extern const struct aty_dac_ops aty_dac_unsupported; /* unsupported */
310 extern const struct aty_dac_ops aty_dac_ct; /* Integrated */
311
312
313 /*
314 * Clock operations
315 */
316
317 struct aty_pll_ops {
318 int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll);
319 u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll);
320 void (*set_pll) (const struct fb_info * info, const union aty_pll * pll);
321 void (*get_pll) (const struct fb_info *info, union aty_pll * pll);
322 int (*init_pll) (const struct fb_info * info, union aty_pll * pll);
323 void (*resume_pll)(const struct fb_info *info, union aty_pll *pll);
324 };
325
326 extern const struct aty_pll_ops aty_pll_ati18818_1; /* ATI 18818 */
327 extern const struct aty_pll_ops aty_pll_stg1703; /* STG 1703 */
328 extern const struct aty_pll_ops aty_pll_ch8398; /* Chrontel 8398 */
329 extern const struct aty_pll_ops aty_pll_att20c408; /* AT&T 20C408 */
330 extern const struct aty_pll_ops aty_pll_ibm514; /* IBM RGB514 */
331 extern const struct aty_pll_ops aty_pll_unsupported; /* unsupported */
332 extern const struct aty_pll_ops aty_pll_ct; /* Integrated */
333
334
335 extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll);
336 extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par);
337
338
339 /*
340 * Hardware cursor support
341 */
342
343 extern int aty_init_cursor(struct fb_info *info);
344
345 /*
346 * Hardware acceleration
347 */
348
349 static inline void wait_for_fifo(u16 entries, const struct atyfb_par *par)
350 {
351 while ((aty_ld_le32(FIFO_STAT, par) & 0xffff) >
352 ((u32) (0x8000 >> entries)));
353 }
354
355 static inline void wait_for_idle(struct atyfb_par *par)
356 {
357 wait_for_fifo(16, par);
358 while ((aty_ld_le32(GUI_STAT, par) & 1) != 0);
359 par->blitter_may_be_busy = 0;
360 }
361
362 extern void aty_reset_engine(const struct atyfb_par *par);
363 extern void aty_init_engine(struct atyfb_par *par, struct fb_info *info);
364 extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par);
365
366 void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
367 void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
368 void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
369
370
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