1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Michel Danzer <michdaen@iiic.ethz.ch>
11 * - 15/16 bit cleanup
12 * - fix panning
13 *
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 * - various fixes & cleanups
17 *
18 * Andreas Hundt <andi@convergence.de>
19 * - FB_ACTIVATE fixes
20 *
21 * Paul Mackerras <paulus@samba.org>
22 * - Convert to new framebuffer API,
23 * fix colormap setting at 16 bits/pixel (565)
24 *
25 * Paul Mundt
26 * - PCI hotplug
27 *
28 * Jon Smirl <jonsmirl@yahoo.com>
29 * - PCI ID update
30 * - replace ROM BIOS search
31 *
32 * Based off of Geert's atyfb.c and vfb.c.
33 *
34 * TODO:
35 * - monitor sensing (DDC)
36 * - virtual display
37 * - other platform support (only ppc/x86 supported)
38 * - hardware cursor support
39 *
40 * Please cc: your patches to brad@neruo.com.
41 */
42
43 /*
44 * A special note of gratitude to ATI's devrel for providing documentation,
45 * example code and hardware. Thanks Nitya. -atong and brad
46 */
47
48
49 #include <linux/config.h>
50 #include <linux/module.h>
51 #include <linux/moduleparam.h>
52 #include <linux/kernel.h>
53 #include <linux/errno.h>
54 #include <linux/string.h>
55 #include <linux/mm.h>
56 #include <linux/tty.h>
57 #include <linux/slab.h>
58 #include <linux/vmalloc.h>
59 #include <linux/delay.h>
60 #include <linux/interrupt.h>
61 #include <asm/uaccess.h>
62 #include <linux/fb.h>
63 #include <linux/init.h>
64 #include <linux/pci.h>
65 #include <linux/ioport.h>
66 #include <linux/console.h>
67 #include <asm/io.h>
68
69 #ifdef CONFIG_PPC_PMAC
70 #include <asm/pmac_feature.h>
71 #include <asm/prom.h>
72 #include <asm/pci-bridge.h>
73 #include "../macmodes.h"
74 #endif
75
76 #ifdef CONFIG_PMAC_BACKLIGHT
77 #include <asm/backlight.h>
78 #endif
79
80 #ifdef CONFIG_BOOTX_TEXT
81 #include <asm/btext.h>
82 #endif /* CONFIG_BOOTX_TEXT */
83
84 #ifdef CONFIG_MTRR
85 #include <asm/mtrr.h>
86 #endif
87
88 #include <video/aty128.h>
89
90 /* Debug flag */
91 #undef DEBUG
92
93 #ifdef DEBUG
94 #define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
95 #else
96 #define DBG(fmt, args...)
97 #endif
98
99 #ifndef CONFIG_PPC_PMAC
100 /* default mode */
101 static struct fb_var_screeninfo default_var __initdata = {
102 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
103 640, 480, 640, 480, 0, 0, 8, 0,
104 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
105 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
106 0, FB_VMODE_NONINTERLACED
107 };
108
109 #else /* CONFIG_PPC_PMAC */
110 /* default to 1024x768 at 75Hz on PPC - this will work
111 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
112 static struct fb_var_screeninfo default_var = {
113 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
114 1024, 768, 1024, 768, 0, 0, 8, 0,
115 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
116 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
117 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
118 FB_VMODE_NONINTERLACED
119 };
120 #endif /* CONFIG_PPC_PMAC */
121
122 /* default modedb mode */
123 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
124 static struct fb_videomode defaultmode __initdata = {
125 .refresh = 60,
126 .xres = 640,
127 .yres = 480,
128 .pixclock = 39722,
129 .left_margin = 48,
130 .right_margin = 16,
131 .upper_margin = 33,
132 .lower_margin = 10,
133 .hsync_len = 96,
134 .vsync_len = 2,
135 .sync = 0,
136 .vmode = FB_VMODE_NONINTERLACED
137 };
138
139 /* Chip generations */
140 enum {
141 rage_128,
142 rage_128_pci,
143 rage_128_pro,
144 rage_128_pro_pci,
145 rage_M3,
146 rage_M3_pci,
147 rage_M4,
148 rage_128_ultra,
149 };
150
151 /* Must match above enum */
152 static const char *r128_family[] __devinitdata = {
153 "AGP",
154 "PCI",
155 "PRO AGP",
156 "PRO PCI",
157 "M3 AGP",
158 "M3 PCI",
159 "M4 AGP",
160 "Ultra AGP",
161 };
162
163 /*
164 * PCI driver prototypes
165 */
166 static int aty128_probe(struct pci_dev *pdev,
167 const struct pci_device_id *ent);
168 static void aty128_remove(struct pci_dev *pdev);
169 static int aty128_pci_suspend(struct pci_dev *pdev, u32 state);
170 static int aty128_pci_resume(struct pci_dev *pdev);
171 static int aty128_do_resume(struct pci_dev *pdev);
172
173 /* supported Rage128 chipsets */
174 static struct pci_device_id aty128_pci_tbl[] = {
175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
267 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
269 { 0, }
270 };
271
272 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
273
274 static struct pci_driver aty128fb_driver = {
275 .name = "aty128fb",
276 .id_table = aty128_pci_tbl,
277 .probe = aty128_probe,
278 .remove = __devexit_p(aty128_remove),
279 .suspend = aty128_pci_suspend,
280 .resume = aty128_pci_resume,
281 };
282
283 /* packed BIOS settings */
284 #ifndef CONFIG_PPC
285 typedef struct {
286 u8 clock_chip_type;
287 u8 struct_size;
288 u8 accelerator_entry;
289 u8 VGA_entry;
290 u16 VGA_table_offset;
291 u16 POST_table_offset;
292 u16 XCLK;
293 u16 MCLK;
294 u8 num_PLL_blocks;
295 u8 size_PLL_blocks;
296 u16 PCLK_ref_freq;
297 u16 PCLK_ref_divider;
298 u32 PCLK_min_freq;
299 u32 PCLK_max_freq;
300 u16 MCLK_ref_freq;
301 u16 MCLK_ref_divider;
302 u32 MCLK_min_freq;
303 u32 MCLK_max_freq;
304 u16 XCLK_ref_freq;
305 u16 XCLK_ref_divider;
306 u32 XCLK_min_freq;
307 u32 XCLK_max_freq;
308 } __attribute__ ((packed)) PLL_BLOCK;
309 #endif /* !CONFIG_PPC */
310
311 /* onboard memory information */
312 struct aty128_meminfo {
313 u8 ML;
314 u8 MB;
315 u8 Trcd;
316 u8 Trp;
317 u8 Twr;
318 u8 CL;
319 u8 Tr2w;
320 u8 LoopLatency;
321 u8 DspOn;
322 u8 Rloop;
323 const char *name;
324 };
325
326 /* various memory configurations */
327 static const struct aty128_meminfo sdr_128 =
328 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
329 static const struct aty128_meminfo sdr_64 =
330 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
331 static const struct aty128_meminfo sdr_sgram =
332 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
333 static const struct aty128_meminfo ddr_sgram =
334 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
335
336 static struct fb_fix_screeninfo aty128fb_fix __initdata = {
337 .id = "ATY Rage128",
338 .type = FB_TYPE_PACKED_PIXELS,
339 .visual = FB_VISUAL_PSEUDOCOLOR,
340 .xpanstep = 8,
341 .ypanstep = 1,
342 .mmio_len = 0x2000,
343 .accel = FB_ACCEL_ATI_RAGE128,
344 };
345
346 static char *mode_option __initdata = NULL;
347
348 #ifdef CONFIG_PPC_PMAC
349 static int default_vmode __initdata = VMODE_1024_768_60;
350 static int default_cmode __initdata = CMODE_8;
351 #endif
352
353 #ifdef CONFIG_PMAC_PBOOK
354 static int default_crt_on __initdata = 0;
355 static int default_lcd_on __initdata = 1;
356 #endif
357
358 #ifdef CONFIG_MTRR
359 static int mtrr = 1;
360 #endif
361
362 /* PLL constants */
363 struct aty128_constants {
364 u32 ref_clk;
365 u32 ppll_min;
366 u32 ppll_max;
367 u32 ref_divider;
368 u32 xclk;
369 u32 fifo_width;
370 u32 fifo_depth;
371 };
372
373 struct aty128_crtc {
374 u32 gen_cntl;
375 u32 h_total, h_sync_strt_wid;
376 u32 v_total, v_sync_strt_wid;
377 u32 pitch;
378 u32 offset, offset_cntl;
379 u32 xoffset, yoffset;
380 u32 vxres, vyres;
381 u32 depth, bpp;
382 };
383
384 struct aty128_pll {
385 u32 post_divider;
386 u32 feedback_divider;
387 u32 vclk;
388 };
389
390 struct aty128_ddafifo {
391 u32 dda_config;
392 u32 dda_on_off;
393 };
394
395 /* register values for a specific mode */
396 struct aty128fb_par {
397 struct aty128_crtc crtc;
398 struct aty128_pll pll;
399 struct aty128_ddafifo fifo_reg;
400 u32 accel_flags;
401 struct aty128_constants constants; /* PLL and others */
402 void __iomem *regbase; /* remapped mmio */
403 u32 vram_size; /* onboard video ram */
404 int chip_gen;
405 const struct aty128_meminfo *mem; /* onboard mem info */
406 #ifdef CONFIG_MTRR
407 struct { int vram; int vram_valid; } mtrr;
408 #endif
409 int blitter_may_be_busy;
410 int fifo_slots; /* free slots in FIFO (64 max) */
411
412 int pm_reg;
413 int crt_on, lcd_on;
414 struct pci_dev *pdev;
415 struct fb_info *next;
416 int asleep;
417 int lock_blank;
418
419 u8 red[32]; /* see aty128fb_setcolreg */
420 u8 green[64];
421 u8 blue[32];
422 u32 pseudo_palette[16]; /* used for TRUECOLOR */
423 };
424
425
426 #define round_div(n, d) ((n+(d/2))/d)
427
428 /*
429 * Interface used by the world
430 */
431 int aty128fb_init(void);
432
433 static int aty128fb_check_var(struct fb_var_screeninfo *var,
434 struct fb_info *info);
435 static int aty128fb_set_par(struct fb_info *info);
436 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
437 u_int transp, struct fb_info *info);
438 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
439 struct fb_info *fb);
440 static int aty128fb_blank(int blank, struct fb_info *fb);
441 static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
442 u_long arg, struct fb_info *info);
443 static int aty128fb_sync(struct fb_info *info);
444
445 /*
446 * Internal routines
447 */
448
449 static int aty128_encode_var(struct fb_var_screeninfo *var,
450 const struct aty128fb_par *par);
451 static int aty128_decode_var(struct fb_var_screeninfo *var,
452 struct aty128fb_par *par);
453 #if 0
454 static void __init aty128_get_pllinfo(struct aty128fb_par *par,
455 void __iomem *bios);
456 static void __init __iomem *aty128_map_ROM(struct pci_dev *pdev, const struct aty128fb_par *par);
457 #endif
458 static void aty128_timings(struct aty128fb_par *par);
459 static void aty128_init_engine(struct aty128fb_par *par);
460 static void aty128_reset_engine(const struct aty128fb_par *par);
461 static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
462 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
463 static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
464 static void wait_for_idle(struct aty128fb_par *par);
465 static u32 depth_to_dst(u32 depth);
466
467 #define BIOS_IN8(v) (readb(bios + (v)))
468 #define BIOS_IN16(v) (readb(bios + (v)) | \
469 (readb(bios + (v) + 1) << 8))
470 #define BIOS_IN32(v) (readb(bios + (v)) | \
471 (readb(bios + (v) + 1) << 8) | \
472 (readb(bios + (v) + 2) << 16) | \
473 (readb(bios + (v) + 3) << 24))
474
475
476 static struct fb_ops aty128fb_ops = {
477 .owner = THIS_MODULE,
478 .fb_check_var = aty128fb_check_var,
479 .fb_set_par = aty128fb_set_par,
480 .fb_setcolreg = aty128fb_setcolreg,
481 .fb_pan_display = aty128fb_pan_display,
482 .fb_blank = aty128fb_blank,
483 .fb_ioctl = aty128fb_ioctl,
484 .fb_sync = aty128fb_sync,
485 .fb_fillrect = cfb_fillrect,
486 .fb_copyarea = cfb_copyarea,
487 .fb_imageblit = cfb_imageblit,
488 .fb_cursor = soft_cursor,
489 };
490
491 #ifdef CONFIG_PMAC_BACKLIGHT
492 static int aty128_set_backlight_enable(int on, int level, void* data);
493 static int aty128_set_backlight_level(int level, void* data);
494
495 static struct backlight_controller aty128_backlight_controller = {
496 aty128_set_backlight_enable,
497 aty128_set_backlight_level
498 };
499 #endif /* CONFIG_PMAC_BACKLIGHT */
500
501 /*
502 * Functions to read from/write to the mmio registers
503 * - endian conversions may possibly be avoided by
504 * using the other register aperture. TODO.
505 */
506 static inline u32 _aty_ld_le32(volatile unsigned int regindex,
507 const struct aty128fb_par *par)
508 {
509 return readl (par->regbase + regindex);
510 }
511
512 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
513 const struct aty128fb_par *par)
514 {
515 writel (val, par->regbase + regindex);
516 }
517
518 static inline u8 _aty_ld_8(unsigned int regindex,
519 const struct aty128fb_par *par)
520 {
521 return readb (par->regbase + regindex);
522 }
523
524 static inline void _aty_st_8(unsigned int regindex, u8 val,
525 const struct aty128fb_par *par)
526 {
527 writeb (val, par->regbase + regindex);
528 }
529
530 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
531 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
532 #define aty_ld_8(regindex) _aty_ld_8(regindex, par)
533 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
534
535 /*
536 * Functions to read from/write to the pll registers
537 */
538
539 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
540 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
541
542
543 static u32 _aty_ld_pll(unsigned int pll_index,
544 const struct aty128fb_par *par)
545 {
546 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
547 return aty_ld_le32(CLOCK_CNTL_DATA);
548 }
549
550
551 static void _aty_st_pll(unsigned int pll_index, u32 val,
552 const struct aty128fb_par *par)
553 {
554 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
555 aty_st_le32(CLOCK_CNTL_DATA, val);
556 }
557
558
559 /* return true when the PLL has completed an atomic update */
560 static int aty_pll_readupdate(const struct aty128fb_par *par)
561 {
562 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
563 }
564
565
566 static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
567 {
568 unsigned long timeout = jiffies + HZ/100; // should be more than enough
569 int reset = 1;
570
571 while (time_before(jiffies, timeout))
572 if (aty_pll_readupdate(par)) {
573 reset = 0;
574 break;
575 }
576
577 if (reset) /* reset engine?? */
578 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
579 }
580
581
582 /* tell PLL to update */
583 static void aty_pll_writeupdate(const struct aty128fb_par *par)
584 {
585 aty_pll_wait_readupdate(par);
586
587 aty_st_pll(PPLL_REF_DIV,
588 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
589 }
590
591
592 /* write to the scratch register to test r/w functionality */
593 static int __init register_test(const struct aty128fb_par *par)
594 {
595 u32 val;
596 int flag = 0;
597
598 val = aty_ld_le32(BIOS_0_SCRATCH);
599
600 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
601 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
602 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
603
604 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
605 flag = 1;
606 }
607
608 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
609 return flag;
610 }
611
612
613 /*
614 * Accelerator engine functions
615 */
616 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
617 {
618 int i;
619
620 for (;;) {
621 for (i = 0; i < 2000000; i++) {
622 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
623 if (par->fifo_slots >= entries)
624 return;
625 }
626 aty128_reset_engine(par);
627 }
628 }
629
630
631 static void wait_for_idle(struct aty128fb_par *par)
632 {
633 int i;
634
635 do_wait_for_fifo(64, par);
636
637 for (;;) {
638 for (i = 0; i < 2000000; i++) {
639 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
640 aty128_flush_pixel_cache(par);
641 par->blitter_may_be_busy = 0;
642 return;
643 }
644 }
645 aty128_reset_engine(par);
646 }
647 }
648
649
650 static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
651 {
652 if (par->fifo_slots < entries)
653 do_wait_for_fifo(64, par);
654 par->fifo_slots -= entries;
655 }
656
657
658 static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
659 {
660 int i;
661 u32 tmp;
662
663 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
664 tmp &= ~(0x00ff);
665 tmp |= 0x00ff;
666 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
667
668 for (i = 0; i < 2000000; i++)
669 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
670 break;
671 }
672
673
674 static void aty128_reset_engine(const struct aty128fb_par *par)
675 {
676 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
677
678 aty128_flush_pixel_cache(par);
679
680 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
681 mclk_cntl = aty_ld_pll(MCLK_CNTL);
682
683 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
684
685 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
686 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
687 aty_ld_le32(GEN_RESET_CNTL);
688 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
689 aty_ld_le32(GEN_RESET_CNTL);
690
691 aty_st_pll(MCLK_CNTL, mclk_cntl);
692 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
693 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
694
695 /* use old pio mode */
696 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
697
698 DBG("engine reset");
699 }
700
701
702 static void aty128_init_engine(struct aty128fb_par *par)
703 {
704 u32 pitch_value;
705
706 wait_for_idle(par);
707
708 /* 3D scaler not spoken here */
709 wait_for_fifo(1, par);
710 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
711
712 aty128_reset_engine(par);
713
714 pitch_value = par->crtc.pitch;
715 if (par->crtc.bpp == 24) {
716 pitch_value = pitch_value * 3;
717 }
718
719 wait_for_fifo(4, par);
720 /* setup engine offset registers */
721 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
722
723 /* setup engine pitch registers */
724 aty_st_le32(DEFAULT_PITCH, pitch_value);
725
726 /* set the default scissor register to max dimensions */
727 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
728
729 /* set the drawing controls registers */
730 aty_st_le32(DP_GUI_MASTER_CNTL,
731 GMC_SRC_PITCH_OFFSET_DEFAULT |
732 GMC_DST_PITCH_OFFSET_DEFAULT |
733 GMC_SRC_CLIP_DEFAULT |
734 GMC_DST_CLIP_DEFAULT |
735 GMC_BRUSH_SOLIDCOLOR |
736 (depth_to_dst(par->crtc.depth) << 8) |
737 GMC_SRC_DSTCOLOR |
738 GMC_BYTE_ORDER_MSB_TO_LSB |
739 GMC_DP_CONVERSION_TEMP_6500 |
740 ROP3_PATCOPY |
741 GMC_DP_SRC_RECT |
742 GMC_3D_FCN_EN_CLR |
743 GMC_DST_CLR_CMP_FCN_CLEAR |
744 GMC_AUX_CLIP_CLEAR |
745 GMC_WRITE_MASK_SET);
746
747 wait_for_fifo(8, par);
748 /* clear the line drawing registers */
749 aty_st_le32(DST_BRES_ERR, 0);
750 aty_st_le32(DST_BRES_INC, 0);
751 aty_st_le32(DST_BRES_DEC, 0);
752
753 /* set brush color registers */
754 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
755 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
756
757 /* set source color registers */
758 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
759 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
760
761 /* default write mask */
762 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
763
764 /* Wait for all the writes to be completed before returning */
765 wait_for_idle(par);
766 }
767
768
769 /* convert depth values to their register representation */
770 static u32 depth_to_dst(u32 depth)
771 {
772 if (depth <= 8)
773 return DST_8BPP;
774 else if (depth <= 15)
775 return DST_15BPP;
776 else if (depth == 16)
777 return DST_16BPP;
778 else if (depth <= 24)
779 return DST_24BPP;
780 else if (depth <= 32)
781 return DST_32BPP;
782
783 return -EINVAL;
784 }
785
786 /*
787 * PLL informations retreival
788 */
789
790
791 #ifndef __sparc__
792 static void __iomem * __init aty128_map_ROM(const struct aty128fb_par *par, struct pci_dev *dev)
793 {
794 u16 dptr;
795 u8 rom_type;
796 void __iomem *bios;
797 size_t rom_size;
798
799 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
800 unsigned int temp;
801 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
802 temp &= 0x00ffffffu;
803 temp |= 0x04 << 24;
804 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
805 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
806
807 bios = pci_map_rom(dev, &rom_size);
808
809 if (!bios) {
810 printk(KERN_ERR "aty128fb: ROM failed to map\n");
811 return NULL;
812 }
813
814 /* Very simple test to make sure it appeared */
815 if (BIOS_IN16(0) != 0xaa55) {
816 printk(KERN_ERR "aty128fb: Invalid ROM signature %x should be 0xaa55\n",
817 BIOS_IN16(0));
818 goto failed;
819 }
820
821 /* Look for the PCI data to check the ROM type */
822 dptr = BIOS_IN16(0x18);
823
824 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
825 * for now, until I've verified this works everywhere. The goal here is more
826 * to phase out Open Firmware images.
827 *
828 * Currently, we only look at the first PCI data, we could iteratre and deal with
829 * them all, and we should use fb_bios_start relative to start of image and not
830 * relative start of ROM, but so far, I never found a dual-image ATI card
831 *
832 * typedef struct {
833 * u32 signature; + 0x00
834 * u16 vendor; + 0x04
835 * u16 device; + 0x06
836 * u16 reserved_1; + 0x08
837 * u16 dlen; + 0x0a
838 * u8 drevision; + 0x0c
839 * u8 class_hi; + 0x0d
840 * u16 class_lo; + 0x0e
841 * u16 ilen; + 0x10
842 * u16 irevision; + 0x12
843 * u8 type; + 0x14
844 * u8 indicator; + 0x15
845 * u16 reserved_2; + 0x16
846 * } pci_data_t;
847 */
848 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
849 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
850 BIOS_IN32(dptr));
851 goto anyway;
852 }
853 rom_type = BIOS_IN8(dptr + 0x14);
854 switch(rom_type) {
855 case 0:
856 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
857 break;
858 case 1:
859 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
860 goto failed;
861 case 2:
862 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
863 goto failed;
864 default:
865 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", rom_type);
866 goto failed;
867 }
868 anyway:
869 return bios;
870
871 failed:
872 pci_unmap_rom(dev, bios);
873 return NULL;
874 }
875
876 static void __init aty128_get_pllinfo(struct aty128fb_par *par, unsigned char __iomem *bios)
877 {
878 unsigned int bios_hdr;
879 unsigned int bios_pll;
880
881 bios_hdr = BIOS_IN16(0x48);
882 bios_pll = BIOS_IN16(bios_hdr + 0x30);
883
884 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
885 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
886 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
887 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
888 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
889
890 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
891 par->constants.ppll_max, par->constants.ppll_min,
892 par->constants.xclk, par->constants.ref_divider,
893 par->constants.ref_clk);
894
895 }
896
897 #ifdef CONFIG_X86
898 static void __iomem * __devinit aty128_find_mem_vbios(struct aty128fb_par *par)
899 {
900 /* I simplified this code as we used to miss the signatures in
901 * a lot of case. It's now closer to XFree, we just don't check
902 * for signatures at all... Something better will have to be done
903 * if we end up having conflicts
904 */
905 u32 segstart;
906 unsigned char __iomem *rom_base = NULL;
907
908 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
909 rom_base = ioremap(segstart, 0x10000);
910 if (rom_base == NULL)
911 return NULL;
912 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
913 break;
914 iounmap(rom_base);
915 rom_base = NULL;
916 }
917 return rom_base;
918 }
919 #endif
920 #endif /* ndef(__sparc__) */
921
922 /* fill in known card constants if pll_block is not available */
923 static void __init aty128_timings(struct aty128fb_par *par)
924 {
925 #ifdef CONFIG_PPC_OF
926 /* instead of a table lookup, assume OF has properly
927 * setup the PLL registers and use their values
928 * to set the XCLK values and reference divider values */
929
930 u32 x_mpll_ref_fb_div;
931 u32 xclk_cntl;
932 u32 Nx, M;
933 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
934 #endif
935
936 if (!par->constants.ref_clk)
937 par->constants.ref_clk = 2950;
938
939 #ifdef CONFIG_PPC_OF
940 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
941 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
942 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
943 M = x_mpll_ref_fb_div & 0x0000ff;
944
945 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
946 (M * PostDivSet[xclk_cntl]));
947
948 par->constants.ref_divider =
949 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
950 #endif
951
952 if (!par->constants.ref_divider) {
953 par->constants.ref_divider = 0x3b;
954
955 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
956 aty_pll_writeupdate(par);
957 }
958 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
959 aty_pll_writeupdate(par);
960
961 /* from documentation */
962 if (!par->constants.ppll_min)
963 par->constants.ppll_min = 12500;
964 if (!par->constants.ppll_max)
965 par->constants.ppll_max = 25000; /* 23000 on some cards? */
966 if (!par->constants.xclk)
967 par->constants.xclk = 0x1d4d; /* same as mclk */
968
969 par->constants.fifo_width = 128;
970 par->constants.fifo_depth = 32;
971
972 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
973 case 0:
974 par->mem = &sdr_128;
975 break;
976 case 1:
977 par->mem = &sdr_sgram;
978 break;
979 case 2:
980 par->mem = &ddr_sgram;
981 break;
982 default:
983 par->mem = &sdr_sgram;
984 }
985 }
986
987
988
989 /*
990 * CRTC programming
991 */
992
993 /* Program the CRTC registers */
994 static void aty128_set_crtc(const struct aty128_crtc *crtc,
995 const struct aty128fb_par *par)
996 {
997 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
998 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
999 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
1000 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
1001 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
1002 aty_st_le32(CRTC_PITCH, crtc->pitch);
1003 aty_st_le32(CRTC_OFFSET, crtc->offset);
1004 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
1005 /* Disable ATOMIC updating. Is this the right place? */
1006 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
1007 }
1008
1009
1010 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1011 struct aty128_crtc *crtc,
1012 const struct aty128fb_par *par)
1013 {
1014 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1015 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1016 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1017 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1018 u32 depth, bytpp;
1019 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1020
1021 /* input */
1022 xres = var->xres;
1023 yres = var->yres;
1024 vxres = var->xres_virtual;
1025 vyres = var->yres_virtual;
1026 xoffset = var->xoffset;
1027 yoffset = var->yoffset;
1028 bpp = var->bits_per_pixel;
1029 left = var->left_margin;
1030 right = var->right_margin;
1031 upper = var->upper_margin;
1032 lower = var->lower_margin;
1033 hslen = var->hsync_len;
1034 vslen = var->vsync_len;
1035 sync = var->sync;
1036 vmode = var->vmode;
1037
1038 if (bpp != 16)
1039 depth = bpp;
1040 else
1041 depth = (var->green.length == 6) ? 16 : 15;
1042
1043 /* check for mode eligibility
1044 * accept only non interlaced modes */
1045 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1046 return -EINVAL;
1047
1048 /* convert (and round up) and validate */
1049 xres = (xres + 7) & ~7;
1050 xoffset = (xoffset + 7) & ~7;
1051
1052 if (vxres < xres + xoffset)
1053 vxres = xres + xoffset;
1054
1055 if (vyres < yres + yoffset)
1056 vyres = yres + yoffset;
1057
1058 /* convert depth into ATI register depth */
1059 dst = depth_to_dst(depth);
1060
1061 if (dst == -EINVAL) {
1062 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1063 return -EINVAL;
1064 }
1065
1066 /* convert register depth to bytes per pixel */
1067 bytpp = mode_bytpp[dst];
1068
1069 /* make sure there is enough video ram for the mode */
1070 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1071 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1072 return -EINVAL;
1073 }
1074
1075 h_disp = (xres >> 3) - 1;
1076 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1077
1078 v_disp = yres - 1;
1079 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1080
1081 /* check to make sure h_total and v_total are in range */
1082 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1083 printk(KERN_ERR "aty128fb: invalid width ranges\n");
1084 return -EINVAL;
1085 }
1086
1087 h_sync_wid = (hslen + 7) >> 3;
1088 if (h_sync_wid == 0)
1089 h_sync_wid = 1;
1090 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
1091 h_sync_wid = 0x3f;
1092
1093 h_sync_strt = (h_disp << 3) + right;
1094
1095 v_sync_wid = vslen;
1096 if (v_sync_wid == 0)
1097 v_sync_wid = 1;
1098 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
1099 v_sync_wid = 0x1f;
1100
1101 v_sync_strt = v_disp + lower;
1102
1103 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1104 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1105
1106 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1107
1108 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1109
1110 crtc->h_total = h_total | (h_disp << 16);
1111 crtc->v_total = v_total | (v_disp << 16);
1112
1113 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1114 (h_sync_pol << 23);
1115 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1116 (v_sync_pol << 23);
1117
1118 crtc->pitch = vxres >> 3;
1119
1120 crtc->offset = 0;
1121
1122 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1123 crtc->offset_cntl = 0x00010000;
1124 else
1125 crtc->offset_cntl = 0;
1126
1127 crtc->vxres = vxres;
1128 crtc->vyres = vyres;
1129 crtc->xoffset = xoffset;
1130 crtc->yoffset = yoffset;
1131 crtc->depth = depth;
1132 crtc->bpp = bpp;
1133
1134 return 0;
1135 }
1136
1137
1138 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1139 {
1140
1141 /* fill in pixel info */
1142 var->red.msb_right = 0;
1143 var->green.msb_right = 0;
1144 var->blue.offset = 0;
1145 var->blue.msb_right = 0;
1146 var->transp.offset = 0;
1147 var->transp.length = 0;
1148 var->transp.msb_right = 0;
1149 switch (pix_width) {
1150 case CRTC_PIX_WIDTH_8BPP:
1151 var->bits_per_pixel = 8;
1152 var->red.offset = 0;
1153 var->red.length = 8;
1154 var->green.offset = 0;
1155 var->green.length = 8;
1156 var->blue.length = 8;
1157 break;
1158 case CRTC_PIX_WIDTH_15BPP:
1159 var->bits_per_pixel = 16;
1160 var->red.offset = 10;
1161 var->red.length = 5;
1162 var->green.offset = 5;
1163 var->green.length = 5;
1164 var->blue.length = 5;
1165 break;
1166 case CRTC_PIX_WIDTH_16BPP:
1167 var->bits_per_pixel = 16;
1168 var->red.offset = 11;
1169 var->red.length = 5;
1170 var->green.offset = 5;
1171 var->green.length = 6;
1172 var->blue.length = 5;
1173 break;
1174 case CRTC_PIX_WIDTH_24BPP:
1175 var->bits_per_pixel = 24;
1176 var->red.offset = 16;
1177 var->red.length = 8;
1178 var->green.offset = 8;
1179 var->green.length = 8;
1180 var->blue.length = 8;
1181 break;
1182 case CRTC_PIX_WIDTH_32BPP:
1183 var->bits_per_pixel = 32;
1184 var->red.offset = 16;
1185 var->red.length = 8;
1186 var->green.offset = 8;
1187 var->green.length = 8;
1188 var->blue.length = 8;
1189 var->transp.offset = 24;
1190 var->transp.length = 8;
1191 break;
1192 default:
1193 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1194 return -EINVAL;
1195 }
1196
1197 return 0;
1198 }
1199
1200
1201 static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1202 struct fb_var_screeninfo *var)
1203 {
1204 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1205 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1206 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1207 u32 pix_width;
1208
1209 /* fun with masking */
1210 h_total = crtc->h_total & 0x1ff;
1211 h_disp = (crtc->h_total >> 16) & 0xff;
1212 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1213 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1214 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1215 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1216 v_total = crtc->v_total & 0x7ff;
1217 v_disp = (crtc->v_total >> 16) & 0x7ff;
1218 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1219 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1220 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1221 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1222 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1223
1224 /* do conversions */
1225 xres = (h_disp + 1) << 3;
1226 yres = v_disp + 1;
1227 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1228 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1229 hslen = h_sync_wid << 3;
1230 upper = v_total - v_sync_strt - v_sync_wid;
1231 lower = v_sync_strt - v_disp;
1232 vslen = v_sync_wid;
1233 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1234 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1235 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1236
1237 aty128_pix_width_to_var(pix_width, var);
1238
1239 var->xres = xres;
1240 var->yres = yres;
1241 var->xres_virtual = crtc->vxres;
1242 var->yres_virtual = crtc->vyres;
1243 var->xoffset = crtc->xoffset;
1244 var->yoffset = crtc->yoffset;
1245 var->left_margin = left;
1246 var->right_margin = right;
1247 var->upper_margin = upper;
1248 var->lower_margin = lower;
1249 var->hsync_len = hslen;
1250 var->vsync_len = vslen;
1251 var->sync = sync;
1252 var->vmode = FB_VMODE_NONINTERLACED;
1253
1254 return 0;
1255 }
1256
1257 #ifdef CONFIG_PMAC_PBOOK
1258 static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1259 {
1260 if (on) {
1261 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON);
1262 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN));
1263 } else
1264 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON);
1265 }
1266
1267 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1268 {
1269 u32 reg;
1270
1271 if (on) {
1272 reg = aty_ld_le32(LVDS_GEN_CNTL);
1273 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1274 reg &= ~LVDS_DISPLAY_DIS;
1275 aty_st_le32(LVDS_GEN_CNTL, reg);
1276 #ifdef CONFIG_PMAC_BACKLIGHT
1277 aty128_set_backlight_enable(get_backlight_enable(),
1278 get_backlight_level(), par);
1279 #endif
1280 } else {
1281 #ifdef CONFIG_PMAC_BACKLIGHT
1282 aty128_set_backlight_enable(0, 0, par);
1283 #endif
1284 reg = aty_ld_le32(LVDS_GEN_CNTL);
1285 reg |= LVDS_DISPLAY_DIS;
1286 aty_st_le32(LVDS_GEN_CNTL, reg);
1287 mdelay(100);
1288 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1289 aty_st_le32(LVDS_GEN_CNTL, reg);
1290 }
1291 }
1292 #endif /* CONFIG_PMAC_PBOOK */
1293
1294 static void aty128_set_pll(struct aty128_pll *pll, const struct aty128fb_par *par)
1295 {
1296 u32 div3;
1297
1298 unsigned char post_conv[] = /* register values for post dividers */
1299 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1300
1301 /* select PPLL_DIV_3 */
1302 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1303
1304 /* reset PLL */
1305 aty_st_pll(PPLL_CNTL,
1306 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1307
1308 /* write the reference divider */
1309 aty_pll_wait_readupdate(par);
1310 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1311 aty_pll_writeupdate(par);
1312
1313 div3 = aty_ld_pll(PPLL_DIV_3);
1314 div3 &= ~PPLL_FB3_DIV_MASK;
1315 div3 |= pll->feedback_divider;
1316 div3 &= ~PPLL_POST3_DIV_MASK;
1317 div3 |= post_conv[pll->post_divider] << 16;
1318
1319 /* write feedback and post dividers */
1320 aty_pll_wait_readupdate(par);
1321 aty_st_pll(PPLL_DIV_3, div3);
1322 aty_pll_writeupdate(par);
1323
1324 aty_pll_wait_readupdate(par);
1325 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1326 aty_pll_writeupdate(par);
1327
1328 /* clear the reset, just in case */
1329 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1330 }
1331
1332
1333 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1334 const struct aty128fb_par *par)
1335 {
1336 const struct aty128_constants c = par->constants;
1337 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1338 u32 output_freq;
1339 u32 vclk; /* in .01 MHz */
1340 int i;
1341 u32 n, d;
1342
1343 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1344
1345 /* adjust pixel clock if necessary */
1346 if (vclk > c.ppll_max)
1347 vclk = c.ppll_max;
1348 if (vclk * 12 < c.ppll_min)
1349 vclk = c.ppll_min/12;
1350
1351 /* now, find an acceptable divider */
1352 for (i = 0; i < sizeof(post_dividers); i++) {
1353 output_freq = post_dividers[i] * vclk;
1354 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max)
1355 break;
1356 }
1357
1358 /* calculate feedback divider */
1359 n = c.ref_divider * output_freq;
1360 d = c.ref_clk;
1361
1362 pll->post_divider = post_dividers[i];
1363 pll->feedback_divider = round_div(n, d);
1364 pll->vclk = vclk;
1365
1366 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1367 "vclk_per: %d\n", pll->post_divider,
1368 pll->feedback_divider, vclk, output_freq,
1369 c.ref_divider, period_in_ps);
1370
1371 return 0;
1372 }
1373
1374
1375 static int aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var)
1376 {
1377 var->pixclock = 100000000 / pll->vclk;
1378
1379 return 0;
1380 }
1381
1382
1383 static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1384 const struct aty128fb_par *par)
1385 {
1386 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1387 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1388 }
1389
1390
1391 static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1392 const struct aty128_pll *pll,
1393 u32 depth,
1394 const struct aty128fb_par *par)
1395 {
1396 const struct aty128_meminfo *m = par->mem;
1397 u32 xclk = par->constants.xclk;
1398 u32 fifo_width = par->constants.fifo_width;
1399 u32 fifo_depth = par->constants.fifo_depth;
1400 s32 x, b, p, ron, roff;
1401 u32 n, d, bpp;
1402
1403 /* round up to multiple of 8 */
1404 bpp = (depth+7) & ~7;
1405
1406 n = xclk * fifo_width;
1407 d = pll->vclk * bpp;
1408 x = round_div(n, d);
1409
1410 ron = 4 * m->MB +
1411 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1412 2 * m->Trp +
1413 m->Twr +
1414 m->CL +
1415 m->Tr2w +
1416 x;
1417
1418 DBG("x %x\n", x);
1419
1420 b = 0;
1421 while (x) {
1422 x >>= 1;
1423 b++;
1424 }
1425 p = b + 1;
1426
1427 ron <<= (11 - p);
1428
1429 n <<= (11 - p);
1430 x = round_div(n, d);
1431 roff = x * (fifo_depth - 4);
1432
1433 if ((ron + m->Rloop) >= roff) {
1434 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1435 return -EINVAL;
1436 }
1437
1438 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1439 p, m->Rloop, x, ron, roff);
1440
1441 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1442 dsp->dda_on_off = ron << 16 | roff;
1443
1444 return 0;
1445 }
1446
1447
1448 /*
1449 * This actually sets the video mode.
1450 */
1451 static int aty128fb_set_par(struct fb_info *info)
1452 {
1453 struct aty128fb_par *par = info->par;
1454 u32 config;
1455 int err;
1456
1457 if ((err = aty128_decode_var(&info->var, par)) != 0)
1458 return err;
1459
1460 if (par->blitter_may_be_busy)
1461 wait_for_idle(par);
1462
1463 /* clear all registers that may interfere with mode setting */
1464 aty_st_le32(OVR_CLR, 0);
1465 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1466 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1467 aty_st_le32(OV0_SCALE_CNTL, 0);
1468 aty_st_le32(MPP_TB_CONFIG, 0);
1469 aty_st_le32(MPP_GP_CONFIG, 0);
1470 aty_st_le32(SUBPIC_CNTL, 0);
1471 aty_st_le32(VIPH_CONTROL, 0);
1472 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1473 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1474 aty_st_le32(CAP0_TRIG_CNTL, 0);
1475 aty_st_le32(CAP1_TRIG_CNTL, 0);
1476
1477 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1478
1479 aty128_set_crtc(&par->crtc, par);
1480 aty128_set_pll(&par->pll, par);
1481 aty128_set_fifo(&par->fifo_reg, par);
1482
1483 config = aty_ld_le32(CONFIG_CNTL) & ~3;
1484
1485 #if defined(__BIG_ENDIAN)
1486 if (par->crtc.bpp == 32)
1487 config |= 2; /* make aperture do 32 bit swapping */
1488 else if (par->crtc.bpp == 16)
1489 config |= 1; /* make aperture do 16 bit swapping */
1490 #endif
1491
1492 aty_st_le32(CONFIG_CNTL, config);
1493 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1494
1495 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1496 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1497 : FB_VISUAL_DIRECTCOLOR;
1498
1499 #ifdef CONFIG_PMAC_PBOOK
1500 if (par->chip_gen == rage_M3) {
1501 aty128_set_crt_enable(par, par->crt_on);
1502 aty128_set_lcd_enable(par, par->lcd_on);
1503 }
1504 #endif
1505 if (par->accel_flags & FB_ACCELF_TEXT)
1506 aty128_init_engine(par);
1507
1508 #ifdef CONFIG_BOOTX_TEXT
1509 btext_update_display(info->fix.smem_start,
1510 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1511 ((par->crtc.v_total>>16) & 0x7ff)+1,
1512 par->crtc.bpp,
1513 par->crtc.vxres*par->crtc.bpp/8);
1514 #endif /* CONFIG_BOOTX_TEXT */
1515
1516 return 0;
1517 }
1518
1519 /*
1520 * encode/decode the User Defined Part of the Display
1521 */
1522
1523 static int aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par)
1524 {
1525 int err;
1526 struct aty128_crtc crtc;
1527 struct aty128_pll pll;
1528 struct aty128_ddafifo fifo_reg;
1529
1530 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1531 return err;
1532
1533 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1534 return err;
1535
1536 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1537 return err;
1538
1539 par->crtc = crtc;
1540 par->pll = pll;
1541 par->fifo_reg = fifo_reg;
1542 par->accel_flags = var->accel_flags;
1543
1544 return 0;
1545 }
1546
1547
1548 static int aty128_encode_var(struct fb_var_screeninfo *var,
1549 const struct aty128fb_par *par)
1550 {
1551 int err;
1552
1553 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1554 return err;
1555
1556 if ((err = aty128_pll_to_var(&par->pll, var)))
1557 return err;
1558
1559 var->nonstd = 0;
1560 var->activate = 0;
1561
1562 var->height = -1;
1563 var->width = -1;
1564 var->accel_flags = par->accel_flags;
1565
1566 return 0;
1567 }
1568
1569
1570 static int aty128fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1571 {
1572 struct aty128fb_par par;
1573 int err;
1574
1575 par = *(struct aty128fb_par *)info->par;
1576 if ((err = aty128_decode_var(var, &par)) != 0)
1577 return err;
1578 aty128_encode_var(var, &par);
1579 return 0;
1580 }
1581
1582
1583 /*
1584 * Pan or Wrap the Display
1585 */
1586 static int aty128fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fb)
1587 {
1588 struct aty128fb_par *par = fb->par;
1589 u32 xoffset, yoffset;
1590 u32 offset;
1591 u32 xres, yres;
1592
1593 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1594 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1595
1596 xoffset = (var->xoffset +7) & ~7;
1597 yoffset = var->yoffset;
1598
1599 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1600 return -EINVAL;
1601
1602 par->crtc.xoffset = xoffset;
1603 par->crtc.yoffset = yoffset;
1604
1605 offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7;
1606
1607 if (par->crtc.bpp == 24)
1608 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1609
1610 aty_st_le32(CRTC_OFFSET, offset);
1611
1612 return 0;
1613 }
1614
1615
1616 /*
1617 * Helper function to store a single palette register
1618 */
1619 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1620 struct aty128fb_par *par)
1621 {
1622 if (par->chip_gen == rage_M3) {
1623 #if 0
1624 /* Note: For now, on M3, we set palette on both heads, which may
1625 * be useless. Can someone with a M3 check this ?
1626 *
1627 * This code would still be useful if using the second CRTC to
1628 * do mirroring
1629 */
1630
1631 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL);
1632 aty_st_8(PALETTE_INDEX, regno);
1633 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1634 #endif
1635 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
1636 }
1637
1638 aty_st_8(PALETTE_INDEX, regno);
1639 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1640 }
1641
1642 static int aty128fb_sync(struct fb_info *info)
1643 {
1644 struct aty128fb_par *par = info->par;
1645
1646 if (par->blitter_may_be_busy)
1647 wait_for_idle(par);
1648 return 0;
1649 }
1650
1651 int __init aty128fb_setup(char *options)
1652 {
1653 char *this_opt;
1654
1655 if (!options || !*options)
1656 return 0;
1657
1658 while ((this_opt = strsep(&options, ",")) != NULL) {
1659 #ifdef CONFIG_PMAC_PBOOK
1660 if (!strncmp(this_opt, "lcd:", 4)) {
1661 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1662 continue;
1663 } else if (!strncmp(this_opt, "crt:", 4)) {
1664 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1665 continue;
1666 }
1667 #endif
1668 #ifdef CONFIG_MTRR
1669 if(!strncmp(this_opt, "nomtrr", 6)) {
1670 mtrr = 0;
1671 continue;
1672 }
1673 #endif
1674 #ifdef CONFIG_PPC_PMAC
1675 /* vmode and cmode deprecated */
1676 if (!strncmp(this_opt, "vmode:", 6)) {
1677 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1678 if (vmode > 0 && vmode <= VMODE_MAX)
1679 default_vmode = vmode;
1680 continue;
1681 } else if (!strncmp(this_opt, "cmode:", 6)) {
1682 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1683 switch (cmode) {
1684 case 0:
1685 case 8:
1686 default_cmode = CMODE_8;
1687 break;
1688 case 15:
1689 case 16:
1690 default_cmode = CMODE_16;
1691 break;
1692 case 24:
1693 case 32:
1694 default_cmode = CMODE_32;
1695 break;
1696 }
1697 continue;
1698 }
1699 #endif /* CONFIG_PPC_PMAC */
1700 mode_option = this_opt;
1701 }
1702 return 0;
1703 }
1704
1705
1706 /*
1707 * Initialisation
1708 */
1709
1710 #ifdef CONFIG_PPC_PMAC
1711 static void aty128_early_resume(void *data)
1712 {
1713 struct aty128fb_par *par = data;
1714
1715 if (try_acquire_console_sem())
1716 return;
1717 aty128_do_resume(par->pdev);
1718 release_console_sem();
1719 }
1720 #endif /* CONFIG_PPC_PMAC */
1721
1722 static int __init aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1723 {
1724 struct fb_info *info = pci_get_drvdata(pdev);
1725 struct aty128fb_par *par = info->par;
1726 struct fb_var_screeninfo var;
1727 char video_card[DEVICE_NAME_SIZE];
1728 u8 chip_rev;
1729 u32 dac;
1730
1731 if (!par->vram_size) /* may have already been probed */
1732 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1733
1734 /* Get the chip revision */
1735 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1736
1737 strcpy(video_card, "Rage128 XX ");
1738 video_card[8] = ent->device >> 8;
1739 video_card[9] = ent->device & 0xFF;
1740
1741 /* range check to make sure */
1742 if (ent->driver_data < (sizeof(r128_family)/sizeof(char *)))
1743 strncat(video_card, r128_family[ent->driver_data], sizeof(video_card));
1744
1745 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1746
1747 if (par->vram_size % (1024 * 1024) == 0)
1748 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1749 else
1750 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1751
1752 par->chip_gen = ent->driver_data;
1753
1754 /* fill in info */
1755 info->fbops = &aty128fb_ops;
1756 info->flags = FBINFO_FLAG_DEFAULT;
1757
1758 #ifdef CONFIG_PMAC_PBOOK
1759 par->lcd_on = default_lcd_on;
1760 par->crt_on = default_crt_on;
1761 #endif
1762
1763 var = default_var;
1764 #ifdef CONFIG_PPC_PMAC
1765 if (_machine == _MACH_Pmac) {
1766 /* Indicate sleep capability */
1767 if (par->chip_gen == rage_M3) {
1768 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1769 pmac_set_early_video_resume(aty128_early_resume, par);
1770 }
1771
1772 /* Find default mode */
1773 if (mode_option) {
1774 if (!mac_find_mode(&var, info, mode_option, 8))
1775 var = default_var;
1776 } else {
1777 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1778 default_vmode = VMODE_1024_768_60;
1779
1780 /* iMacs need that resolution
1781 * PowerMac2,1 first r128 iMacs
1782 * PowerMac2,2 summer 2000 iMacs
1783 * PowerMac4,1 january 2001 iMacs "flower power"
1784 */
1785 if (machine_is_compatible("PowerMac2,1") ||
1786 machine_is_compatible("PowerMac2,2") ||
1787 machine_is_compatible("PowerMac4,1"))
1788 default_vmode = VMODE_1024_768_75;
1789
1790 /* iBook SE */
1791 if (machine_is_compatible("PowerBook2,2"))
1792 default_vmode = VMODE_800_600_60;
1793
1794 /* PowerBook Firewire (Pismo), iBook Dual USB */
1795 if (machine_is_compatible("PowerBook3,1") ||
1796 machine_is_compatible("PowerBook4,1"))
1797 default_vmode = VMODE_1024_768_60;
1798
1799 /* PowerBook Titanium */
1800 if (machine_is_compatible("PowerBook3,2"))
1801 default_vmode = VMODE_1152_768_60;
1802
1803 if (default_cmode > 16)
1804 default_cmode = CMODE_32;
1805 else if (default_cmode > 8)
1806 default_cmode = CMODE_16;
1807 else
1808 default_cmode = CMODE_8;
1809
1810 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1811 var = default_var;
1812 }
1813 } else
1814 #endif /* CONFIG_PPC_PMAC */
1815 {
1816 if (mode_option)
1817 if (fb_find_mode(&var, info, mode_option, NULL,
1818 0, &defaultmode, 8) == 0)
1819 var = default_var;
1820 }
1821
1822 var.accel_flags &= ~FB_ACCELF_TEXT;
1823 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
1824
1825 if (aty128fb_check_var(&var, info)) {
1826 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1827 return 0;
1828 }
1829
1830 /* setup the DAC the way we like it */
1831 dac = aty_ld_le32(DAC_CNTL);
1832 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
1833 dac |= DAC_MASK;
1834 if (par->chip_gen == rage_M3)
1835 dac |= DAC_PALETTE2_SNOOP_EN;
1836 aty_st_le32(DAC_CNTL, dac);
1837
1838 /* turn off bus mastering, just in case */
1839 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
1840
1841 info->var = var;
1842 fb_alloc_cmap(&info->cmap, 256, 0);
1843
1844 var.activate = FB_ACTIVATE_NOW;
1845
1846 aty128_init_engine(par);
1847
1848 if (register_framebuffer(info) < 0)
1849 return 0;
1850
1851 #ifdef CONFIG_PMAC_BACKLIGHT
1852 /* Could be extended to Rage128Pro LVDS output too */
1853 if (par->chip_gen == rage_M3)
1854 register_backlight_controller(&aty128_backlight_controller, par, "ati");
1855 #endif /* CONFIG_PMAC_BACKLIGHT */
1856
1857 par->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
1858 par->pdev = pdev;
1859 par->asleep = 0;
1860 par->lock_blank = 0;
1861
1862 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
1863 info->node, info->fix.id, video_card);
1864
1865 return 1; /* success! */
1866 }
1867
1868 #ifdef CONFIG_PCI
1869 /* register a card ++ajoshi */
1870 static int __init aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1871 {
1872 unsigned long fb_addr, reg_addr;
1873 struct aty128fb_par *par;
1874 struct fb_info *info;
1875 int err;
1876 #ifndef __sparc__
1877 void __iomem *bios = NULL;
1878 #endif
1879
1880 /* Enable device in PCI config */
1881 if ((err = pci_enable_device(pdev))) {
1882 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
1883 err);
1884 return -ENODEV;
1885 }
1886
1887 fb_addr = pci_resource_start(pdev, 0);
1888 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
1889 "aty128fb FB")) {
1890 printk(KERN_ERR "aty128fb: cannot reserve frame "
1891 "buffer memory\n");
1892 return -ENODEV;
1893 }
1894
1895 reg_addr = pci_resource_start(pdev, 2);
1896 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
1897 "aty128fb MMIO")) {
1898 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
1899 goto err_free_fb;
1900 }
1901
1902 /* We have the resources. Now virtualize them */
1903 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
1904 if (info == NULL) {
1905 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
1906 goto err_free_mmio;
1907 }
1908 par = info->par;
1909
1910 info->pseudo_palette = par->pseudo_palette;
1911 info->fix = aty128fb_fix;
1912
1913 /* Virtualize mmio region */
1914 info->fix.mmio_start = reg_addr;
1915 par->regbase = ioremap(reg_addr, pci_resource_len(pdev, 2));
1916 if (!par->regbase)
1917 goto err_free_info;
1918
1919 /* Grab memory size from the card */
1920 // How does this relate to the resource length from the PCI hardware?
1921 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1922
1923 /* Virtualize the framebuffer */
1924 info->screen_base = ioremap(fb_addr, par->vram_size);
1925 if (!info->screen_base)
1926 goto err_unmap_out;
1927
1928 /* Set up info->fix */
1929 info->fix = aty128fb_fix;
1930 info->fix.smem_start = fb_addr;
1931 info->fix.smem_len = par->vram_size;
1932 info->fix.mmio_start = reg_addr;
1933
1934 /* If we can't test scratch registers, something is seriously wrong */
1935 if (!register_test(par)) {
1936 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
1937 goto err_out;
1938 }
1939
1940 #ifndef __sparc__
1941 bios = aty128_map_ROM(par, pdev);
1942 #ifdef CONFIG_X86
1943 if (bios == NULL)
1944 bios = aty128_find_mem_vbios(par);
1945 #endif
1946 if (bios == NULL)
1947 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
1948 else {
1949 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
1950 aty128_get_pllinfo(par, bios);
1951 pci_unmap_rom(pdev, bios);
1952 }
1953 #endif /* __sparc__ */
1954
1955 aty128_timings(par);
1956 pci_set_drvdata(pdev, info);
1957
1958 if (!aty128_init(pdev, ent))
1959 goto err_out;
1960
1961 #ifdef CONFIG_MTRR
1962 if (mtrr) {
1963 par->mtrr.vram = mtrr_add(info->fix.smem_start,
1964 par->vram_size, MTRR_TYPE_WRCOMB, 1);
1965 par->mtrr.vram_valid = 1;
1966 /* let there be speed */
1967 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
1968 }
1969 #endif /* CONFIG_MTRR */
1970 return 0;
1971
1972 err_out:
1973 iounmap(info->screen_base);
1974 err_unmap_out:
1975 iounmap(par->regbase);
1976 err_free_info:
1977 framebuffer_release(info);
1978 err_free_mmio:
1979 release_mem_region(pci_resource_start(pdev, 2),
1980 pci_resource_len(pdev, 2));
1981 err_free_fb:
1982 release_mem_region(pci_resource_start(pdev, 0),
1983 pci_resource_len(pdev, 0));
1984 return -ENODEV;
1985 }
1986
1987 static void __devexit aty128_remove(struct pci_dev *pdev)
1988 {
1989 struct fb_info *info = pci_get_drvdata(pdev);
1990 struct aty128fb_par *par;
1991
1992 if (!info)
1993 return;
1994
1995 par = info->par;
1996
1997 unregister_framebuffer(info);
1998 #ifdef CONFIG_MTRR
1999 if (par->mtrr.vram_valid)
2000 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2001 par->vram_size);
2002 #endif /* CONFIG_MTRR */
2003 iounmap(par->regbase);
2004 iounmap(info->screen_base);
2005
2006 release_mem_region(pci_resource_start(pdev, 0),
2007 pci_resource_len(pdev, 0));
2008 release_mem_region(pci_resource_start(pdev, 2),
2009 pci_resource_len(pdev, 2));
2010 framebuffer_release(info);
2011 }
2012 #endif /* CONFIG_PCI */
2013
2014
2015
2016 /*
2017 * Blank the display.
2018 */
2019 static int aty128fb_blank(int blank, struct fb_info *fb)
2020 {
2021 struct aty128fb_par *par = fb->par;
2022 u8 state = 0;
2023
2024 if (par->lock_blank || par->asleep)
2025 return 0;
2026
2027 #ifdef CONFIG_PMAC_BACKLIGHT
2028 if ((_machine == _MACH_Pmac) && blank)
2029 set_backlight_enable(0);
2030 #endif /* CONFIG_PMAC_BACKLIGHT */
2031
2032 if (blank & FB_BLANK_VSYNC_SUSPEND)
2033 state |= 2;
2034 if (blank & FB_BLANK_HSYNC_SUSPEND)
2035 state |= 1;
2036 if (blank & FB_BLANK_POWERDOWN)
2037 state |= 4;
2038
2039 aty_st_8(CRTC_EXT_CNTL+1, state);
2040
2041 #ifdef CONFIG_PMAC_PBOOK
2042 if (par->chip_gen == rage_M3) {
2043 aty128_set_crt_enable(par, par->crt_on && !blank);
2044 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2045 }
2046 #endif
2047 #ifdef CONFIG_PMAC_BACKLIGHT
2048 if ((_machine == _MACH_Pmac) && !blank)
2049 set_backlight_enable(1);
2050 #endif /* CONFIG_PMAC_BACKLIGHT */
2051 return 0;
2052 }
2053
2054 /*
2055 * Set a single color register. The values supplied are already
2056 * rounded down to the hardware's capabilities (according to the
2057 * entries in the var structure). Return != 0 for invalid regno.
2058 */
2059 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2060 u_int transp, struct fb_info *info)
2061 {
2062 struct aty128fb_par *par = info->par;
2063
2064 if (regno > 255
2065 || (par->crtc.depth == 16 && regno > 63)
2066 || (par->crtc.depth == 15 && regno > 31))
2067 return 1;
2068
2069 red >>= 8;
2070 green >>= 8;
2071 blue >>= 8;
2072
2073 if (regno < 16) {
2074 int i;
2075 u32 *pal = info->pseudo_palette;
2076
2077 switch (par->crtc.depth) {
2078 case 15:
2079 pal[regno] = (regno << 10) | (regno << 5) | regno;
2080 break;
2081 case 16:
2082 pal[regno] = (regno << 11) | (regno << 6) | regno;
2083 break;
2084 case 24:
2085 pal[regno] = (regno << 16) | (regno << 8) | regno;
2086 break;
2087 case 32:
2088 i = (regno << 8) | regno;
2089 pal[regno] = (i << 16) | i;
2090 break;
2091 }
2092 }
2093
2094 if (par->crtc.depth == 16 && regno > 0) {
2095 /*
2096 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2097 * have 32 slots for R and B values but 64 slots for G values.
2098 * Thus the R and B values go in one slot but the G value
2099 * goes in a different slot, and we have to avoid disturbing
2100 * the other fields in the slots we touch.
2101 */
2102 par->green[regno] = green;
2103 if (regno < 32) {
2104 par->red[regno] = red;
2105 par->blue[regno] = blue;
2106 aty128_st_pal(regno * 8, red, par->green[regno*2],
2107 blue, par);
2108 }
2109 red = par->red[regno/2];
2110 blue = par->blue[regno/2];
2111 regno <<= 2;
2112 } else if (par->crtc.bpp == 16)
2113 regno <<= 3;
2114 aty128_st_pal(regno, red, green, blue, par);
2115
2116 return 0;
2117 }
2118
2119 #define ATY_MIRROR_LCD_ON 0x00000001
2120 #define ATY_MIRROR_CRT_ON 0x00000002
2121
2122 /* out param: u32* backlight value: 0 to 15 */
2123 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2124 /* in param: u32* backlight value: 0 to 15 */
2125 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2126
2127 static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
2128 u_long arg, struct fb_info *info)
2129 {
2130 #ifdef CONFIG_PMAC_PBOOK
2131 struct aty128fb_par *par = info->par;
2132 u32 value;
2133 int rc;
2134
2135 switch (cmd) {
2136 case FBIO_ATY128_SET_MIRROR:
2137 if (par->chip_gen != rage_M3)
2138 return -EINVAL;
2139 rc = get_user(value, (__u32 __user *)arg);
2140 if (rc)
2141 return rc;
2142 par->lcd_on = (value & 0x01) != 0;
2143 par->crt_on = (value & 0x02) != 0;
2144 if (!par->crt_on && !par->lcd_on)
2145 par->lcd_on = 1;
2146 aty128_set_crt_enable(par, par->crt_on);
2147 aty128_set_lcd_enable(par, par->lcd_on);
2148 return 0;
2149 case FBIO_ATY128_GET_MIRROR:
2150 if (par->chip_gen != rage_M3)
2151 return -EINVAL;
2152 value = (par->crt_on << 1) | par->lcd_on;
2153 return put_user(value, (__u32 __user *)arg);
2154 }
2155 #endif
2156 return -EINVAL;
2157 }
2158
2159 #ifdef CONFIG_PMAC_BACKLIGHT
2160 static int backlight_conv[] = {
2161 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2162 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2163 };
2164
2165 /* We turn off the LCD completely instead of just dimming the backlight.
2166 * This provides greater power saving and the display is useless without
2167 * backlight anyway
2168 */
2169 #define BACKLIGHT_LVDS_OFF
2170 /* That one prevents proper CRT output with LCD off */
2171 #undef BACKLIGHT_DAC_OFF
2172
2173 static int aty128_set_backlight_enable(int on, int level, void *data)
2174 {
2175 struct aty128fb_par *par = data;
2176 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
2177
2178 if (!par->lcd_on)
2179 on = 0;
2180 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
2181 if (on && level > BACKLIGHT_OFF) {
2182 reg |= LVDS_DIGION;
2183 if (!(reg & LVDS_ON)) {
2184 reg &= ~LVDS_BLON;
2185 aty_st_le32(LVDS_GEN_CNTL, reg);
2186 (void)aty_ld_le32(LVDS_GEN_CNTL);
2187 mdelay(10);
2188 reg |= LVDS_BLON;
2189 aty_st_le32(LVDS_GEN_CNTL, reg);
2190 }
2191 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2192 reg |= (backlight_conv[level] << LVDS_BL_MOD_LEVEL_SHIFT);
2193 #ifdef BACKLIGHT_LVDS_OFF
2194 reg |= LVDS_ON | LVDS_EN;
2195 reg &= ~LVDS_DISPLAY_DIS;
2196 #endif
2197 aty_st_le32(LVDS_GEN_CNTL, reg);
2198 #ifdef BACKLIGHT_DAC_OFF
2199 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
2200 #endif
2201 } else {
2202 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2203 reg |= (backlight_conv[0] << LVDS_BL_MOD_LEVEL_SHIFT);
2204 #ifdef BACKLIGHT_LVDS_OFF
2205 reg |= LVDS_DISPLAY_DIS;
2206 aty_st_le32(LVDS_GEN_CNTL, reg);
2207 (void)aty_ld_le32(LVDS_GEN_CNTL);
2208 udelay(10);
2209 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
2210 #endif
2211 aty_st_le32(LVDS_GEN_CNTL, reg);
2212 #ifdef BACKLIGHT_DAC_OFF
2213 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
2214 #endif
2215 }
2216
2217 return 0;
2218 }
2219
2220 static int aty128_set_backlight_level(int level, void* data)
2221 {
2222 return aty128_set_backlight_enable(1, level, data);
2223 }
2224 #endif /* CONFIG_PMAC_BACKLIGHT */
2225
2226 #if 0
2227 /*
2228 * Accelerated functions
2229 */
2230
2231 static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2232 u_int width, u_int height,
2233 struct fb_info_aty128 *par)
2234 {
2235 u32 save_dp_datatype, save_dp_cntl, dstval;
2236
2237 if (!width || !height)
2238 return;
2239
2240 dstval = depth_to_dst(par->current_par.crtc.depth);
2241 if (dstval == DST_24BPP) {
2242 srcx *= 3;
2243 dstx *= 3;
2244 width *= 3;
2245 } else if (dstval == -EINVAL) {
2246 printk("aty128fb: invalid depth or RGBA\n");
2247 return;
2248 }
2249
2250 wait_for_fifo(2, par);
2251 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2252 save_dp_cntl = aty_ld_le32(DP_CNTL);
2253
2254 wait_for_fifo(6, par);
2255 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2256 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2257 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2258 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2259
2260 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2261 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2262
2263 par->blitter_may_be_busy = 1;
2264
2265 wait_for_fifo(2, par);
2266 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2267 aty_st_le32(DP_CNTL, save_dp_cntl);
2268 }
2269
2270
2271 /*
2272 * Text mode accelerated functions
2273 */
2274
2275 static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
2276 int height, int width)
2277 {
2278 sx *= fontwidth(p);
2279 sy *= fontheight(p);
2280 dx *= fontwidth(p);
2281 dy *= fontheight(p);
2282 width *= fontwidth(p);
2283 height *= fontheight(p);
2284
2285 aty128_rectcopy(sx, sy, dx, dy, width, height,
2286 (struct fb_info_aty128 *)p->fb_info);
2287 }
2288 #endif /* 0 */
2289
2290 static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2291 {
2292 u32 pmgt;
2293 u16 pwr_command;
2294 struct pci_dev *pdev = par->pdev;
2295
2296 if (!par->pm_reg)
2297 return;
2298
2299 /* Set the chip into the appropriate suspend mode (we use D2,
2300 * D3 would require a complete re-initialisation of the chip,
2301 * including PCI config registers, clocks, AGP configuration, ...)
2302 */
2303 if (suspend) {
2304 /* Make sure CRTC2 is reset. Remove that the day we decide to
2305 * actually use CRTC2 and replace it with real code for disabling
2306 * the CRTC2 output during sleep
2307 */
2308 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2309 ~(CRTC2_EN));
2310
2311 /* Set the power management mode to be PCI based */
2312 /* Use this magic value for now */
2313 pmgt = 0x0c005407;
2314 aty_st_pll(POWER_MANAGEMENT, pmgt);
2315 (void)aty_ld_pll(POWER_MANAGEMENT);
2316 aty_st_le32(BUS_CNTL1, 0x00000010);
2317 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2318 mdelay(100);
2319 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2320 /* Switch PCI power management to D2 */
2321 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL,
2322 (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2);
2323 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2324 } else {
2325 /* Switch back PCI power management to D0 */
2326 mdelay(100);
2327 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 0);
2328 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2329 mdelay(100);
2330 }
2331 }
2332
2333 static int aty128_pci_suspend(struct pci_dev *pdev, u32 state)
2334 {
2335 struct fb_info *info = pci_get_drvdata(pdev);
2336 struct aty128fb_par *par = info->par;
2337
2338 /* We don't do anything but D2, for now we return 0, but
2339 * we may want to change that. How do we know if the BIOS
2340 * can properly take care of D3 ? Also, with swsusp, we
2341 * know we'll be rebooted, ...
2342 */
2343 #ifdef CONFIG_PPC_PMAC
2344 /* HACK ALERT ! Once I find a proper way to say to each driver
2345 * individually what will happen with it's PCI slot, I'll change
2346 * that. On laptops, the AGP slot is just unclocked, so D2 is
2347 * expected, while on desktops, the card is powered off
2348 */
2349 if (state >= 3)
2350 state = 2;
2351 #endif /* CONFIG_PPC_PMAC */
2352
2353 if (state != 2 || state == pdev->dev.power.power_state)
2354 return 0;
2355
2356 printk(KERN_DEBUG "aty128fb: suspending...\n");
2357
2358 acquire_console_sem();
2359
2360 fb_set_suspend(info, 1);
2361
2362 /* Make sure engine is reset */
2363 wait_for_idle(par);
2364 aty128_reset_engine(par);
2365 wait_for_idle(par);
2366
2367 /* Blank display and LCD */
2368 aty128fb_blank(VESA_POWERDOWN, info);
2369
2370 /* Sleep */
2371 par->asleep = 1;
2372 par->lock_blank = 1;
2373
2374 /* We need a way to make sure the fbdev layer will _not_ touch the
2375 * framebuffer before we put the chip to suspend state. On 2.4, I
2376 * used dummy fb ops, 2.5 need proper support for this at the
2377 * fbdev level
2378 */
2379 if (state == 2)
2380 aty128_set_suspend(par, 1);
2381
2382 release_console_sem();
2383
2384 pdev->dev.power.power_state = state;
2385
2386 return 0;
2387 }
2388
2389 static int aty128_do_resume(struct pci_dev *pdev)
2390 {
2391 struct fb_info *info = pci_get_drvdata(pdev);
2392 struct aty128fb_par *par = info->par;
2393
2394 if (pdev->dev.power.power_state == 0)
2395 return 0;
2396
2397 /* Wakeup chip */
2398 if (pdev->dev.power.power_state == 2)
2399 aty128_set_suspend(par, 0);
2400 par->asleep = 0;
2401
2402 /* Restore display & engine */
2403 aty128_reset_engine(par);
2404 wait_for_idle(par);
2405 aty128fb_set_par(info);
2406 fb_pan_display(info, &info->var);
2407 fb_set_cmap(&info->cmap, info);
2408
2409 /* Refresh */
2410 fb_set_suspend(info, 0);
2411
2412 /* Unblank */
2413 par->lock_blank = 0;
2414 aty128fb_blank(0, info);
2415
2416 pdev->dev.power.power_state = 0;
2417
2418 printk(KERN_DEBUG "aty128fb: resumed !\n");
2419
2420 return 0;
2421 }
2422
2423 static int aty128_pci_resume(struct pci_dev *pdev)
2424 {
2425 int rc;
2426
2427 acquire_console_sem();
2428 rc = aty128_do_resume(pdev);
2429 release_console_sem();
2430
2431 return rc;
2432 }
2433
2434
2435 int __init aty128fb_init(void)
2436 {
2437 #ifndef MODULE
2438 char *option = NULL;
2439
2440 if (fb_get_options("aty128fb", &option))
2441 return -ENODEV;
2442 aty128fb_setup(option);
2443 #endif
2444
2445 return pci_module_init(&aty128fb_driver);
2446 }
2447
2448 static void __exit aty128fb_exit(void)
2449 {
2450 pci_unregister_driver(&aty128fb_driver);
2451 }
2452
2453 module_init(aty128fb_init);
2454
2455 #ifdef MODULE
2456 module_exit(aty128fb_exit);
2457
2458 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2459 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2460 MODULE_LICENSE("GPL");
2461 module_param(mode_option, charp, 0);
2462 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2463 #ifdef CONFIG_MTRR
2464 module_param_named(nomtrr, mtrr, invbool, 0);
2465 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
2466 #endif
2467 #endif
2468
2469
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