1 /*
2 * MUSB OTG peripheral driver ep0 handling
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/spinlock.h>
40 #include <linux/init.h>
41 #include <linux/device.h>
42 #include <linux/interrupt.h>
43
44 #include "musb_core.h"
45
46 /* ep0 is always musb->endpoints[0].ep_in */
47 #define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
48
49 /*
50 * locking note: we use only the controller lock, for simpler correctness.
51 * It's always held with IRQs blocked.
52 *
53 * It protects the ep0 request queue as well as ep0_state, not just the
54 * controller and indexed registers. And that lock stays held unless it
55 * needs to be dropped to allow reentering this driver ... like upcalls to
56 * the gadget driver, or adjusting endpoint halt status.
57 */
58
59 static char *decode_ep0stage(u8 stage)
60 {
61 switch (stage) {
62 case MUSB_EP0_STAGE_IDLE: return "idle";
63 case MUSB_EP0_STAGE_SETUP: return "setup";
64 case MUSB_EP0_STAGE_TX: return "in";
65 case MUSB_EP0_STAGE_RX: return "out";
66 case MUSB_EP0_STAGE_ACKWAIT: return "wait";
67 case MUSB_EP0_STAGE_STATUSIN: return "in/status";
68 case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
69 default: return "?";
70 }
71 }
72
73 /* handle a standard GET_STATUS request
74 * Context: caller holds controller lock
75 */
76 static int service_tx_status_request(
77 struct musb *musb,
78 const struct usb_ctrlrequest *ctrlrequest)
79 {
80 void __iomem *mbase = musb->mregs;
81 int handled = 1;
82 u8 result[2], epnum = 0;
83 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
84
85 result[1] = 0;
86
87 switch (recip) {
88 case USB_RECIP_DEVICE:
89 result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
90 result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
91 #ifdef CONFIG_USB_MUSB_OTG
92 if (musb->g.is_otg) {
93 result[0] |= musb->g.b_hnp_enable
94 << USB_DEVICE_B_HNP_ENABLE;
95 result[0] |= musb->g.a_alt_hnp_support
96 << USB_DEVICE_A_ALT_HNP_SUPPORT;
97 result[0] |= musb->g.a_hnp_support
98 << USB_DEVICE_A_HNP_SUPPORT;
99 }
100 #endif
101 break;
102
103 case USB_RECIP_INTERFACE:
104 result[0] = 0;
105 break;
106
107 case USB_RECIP_ENDPOINT: {
108 int is_in;
109 struct musb_ep *ep;
110 u16 tmp;
111 void __iomem *regs;
112
113 epnum = (u8) ctrlrequest->wIndex;
114 if (!epnum) {
115 result[0] = 0;
116 break;
117 }
118
119 is_in = epnum & USB_DIR_IN;
120 if (is_in) {
121 epnum &= 0x0f;
122 ep = &musb->endpoints[epnum].ep_in;
123 } else {
124 ep = &musb->endpoints[epnum].ep_out;
125 }
126 regs = musb->endpoints[epnum].regs;
127
128 if (epnum >= MUSB_C_NUM_EPS || !ep->desc) {
129 handled = -EINVAL;
130 break;
131 }
132
133 musb_ep_select(mbase, epnum);
134 if (is_in)
135 tmp = musb_readw(regs, MUSB_TXCSR)
136 & MUSB_TXCSR_P_SENDSTALL;
137 else
138 tmp = musb_readw(regs, MUSB_RXCSR)
139 & MUSB_RXCSR_P_SENDSTALL;
140 musb_ep_select(mbase, 0);
141
142 result[0] = tmp ? 1 : 0;
143 } break;
144
145 default:
146 /* class, vendor, etc ... delegate */
147 handled = 0;
148 break;
149 }
150
151 /* fill up the fifo; caller updates csr0 */
152 if (handled > 0) {
153 u16 len = le16_to_cpu(ctrlrequest->wLength);
154
155 if (len > 2)
156 len = 2;
157 musb_write_fifo(&musb->endpoints[0], len, result);
158 }
159
160 return handled;
161 }
162
163 /*
164 * handle a control-IN request, the end0 buffer contains the current request
165 * that is supposed to be a standard control request. Assumes the fifo to
166 * be at least 2 bytes long.
167 *
168 * @return 0 if the request was NOT HANDLED,
169 * < 0 when error
170 * > 0 when the request is processed
171 *
172 * Context: caller holds controller lock
173 */
174 static int
175 service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
176 {
177 int handled = 0; /* not handled */
178
179 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
180 == USB_TYPE_STANDARD) {
181 switch (ctrlrequest->bRequest) {
182 case USB_REQ_GET_STATUS:
183 handled = service_tx_status_request(musb,
184 ctrlrequest);
185 break;
186
187 /* case USB_REQ_SYNC_FRAME: */
188
189 default:
190 break;
191 }
192 }
193 return handled;
194 }
195
196 /*
197 * Context: caller holds controller lock
198 */
199 static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
200 {
201 musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
202 }
203
204 /*
205 * Tries to start B-device HNP negotiation if enabled via sysfs
206 */
207 static inline void musb_try_b_hnp_enable(struct musb *musb)
208 {
209 void __iomem *mbase = musb->mregs;
210 u8 devctl;
211
212 DBG(1, "HNP: Setting HR\n");
213 devctl = musb_readb(mbase, MUSB_DEVCTL);
214 musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
215 }
216
217 /*
218 * Handle all control requests with no DATA stage, including standard
219 * requests such as:
220 * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
221 * always delegated to the gadget driver
222 * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
223 * always handled here, except for class/vendor/... features
224 *
225 * Context: caller holds controller lock
226 */
227 static int
228 service_zero_data_request(struct musb *musb,
229 struct usb_ctrlrequest *ctrlrequest)
230 __releases(musb->lock)
231 __acquires(musb->lock)
232 {
233 int handled = -EINVAL;
234 void __iomem *mbase = musb->mregs;
235 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
236
237 /* the gadget driver handles everything except what we MUST handle */
238 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
239 == USB_TYPE_STANDARD) {
240 switch (ctrlrequest->bRequest) {
241 case USB_REQ_SET_ADDRESS:
242 /* change it after the status stage */
243 musb->set_address = true;
244 musb->address = (u8) (ctrlrequest->wValue & 0x7f);
245 handled = 1;
246 break;
247
248 case USB_REQ_CLEAR_FEATURE:
249 switch (recip) {
250 case USB_RECIP_DEVICE:
251 if (ctrlrequest->wValue
252 != USB_DEVICE_REMOTE_WAKEUP)
253 break;
254 musb->may_wakeup = 0;
255 handled = 1;
256 break;
257 case USB_RECIP_INTERFACE:
258 break;
259 case USB_RECIP_ENDPOINT:{
260 const u8 num = ctrlrequest->wIndex & 0x0f;
261 struct musb_ep *musb_ep;
262
263 if (num == 0
264 || num >= MUSB_C_NUM_EPS
265 || ctrlrequest->wValue
266 != USB_ENDPOINT_HALT)
267 break;
268
269 if (ctrlrequest->wIndex & USB_DIR_IN)
270 musb_ep = &musb->endpoints[num].ep_in;
271 else
272 musb_ep = &musb->endpoints[num].ep_out;
273 if (!musb_ep->desc)
274 break;
275
276 /* REVISIT do it directly, no locking games */
277 spin_unlock(&musb->lock);
278 musb_gadget_set_halt(&musb_ep->end_point, 0);
279 spin_lock(&musb->lock);
280
281 /* select ep0 again */
282 musb_ep_select(mbase, 0);
283 handled = 1;
284 } break;
285 default:
286 /* class, vendor, etc ... delegate */
287 handled = 0;
288 break;
289 }
290 break;
291
292 case USB_REQ_SET_FEATURE:
293 switch (recip) {
294 case USB_RECIP_DEVICE:
295 handled = 1;
296 switch (ctrlrequest->wValue) {
297 case USB_DEVICE_REMOTE_WAKEUP:
298 musb->may_wakeup = 1;
299 break;
300 case USB_DEVICE_TEST_MODE:
301 if (musb->g.speed != USB_SPEED_HIGH)
302 goto stall;
303 if (ctrlrequest->wIndex & 0xff)
304 goto stall;
305
306 switch (ctrlrequest->wIndex >> 8) {
307 case 1:
308 pr_debug("TEST_J\n");
309 /* TEST_J */
310 musb->test_mode_nr =
311 MUSB_TEST_J;
312 break;
313 case 2:
314 /* TEST_K */
315 pr_debug("TEST_K\n");
316 musb->test_mode_nr =
317 MUSB_TEST_K;
318 break;
319 case 3:
320 /* TEST_SE0_NAK */
321 pr_debug("TEST_SE0_NAK\n");
322 musb->test_mode_nr =
323 MUSB_TEST_SE0_NAK;
324 break;
325 case 4:
326 /* TEST_PACKET */
327 pr_debug("TEST_PACKET\n");
328 musb->test_mode_nr =
329 MUSB_TEST_PACKET;
330 break;
331 default:
332 goto stall;
333 }
334
335 /* enter test mode after irq */
336 if (handled > 0)
337 musb->test_mode = true;
338 break;
339 #ifdef CONFIG_USB_MUSB_OTG
340 case USB_DEVICE_B_HNP_ENABLE:
341 if (!musb->g.is_otg)
342 goto stall;
343 musb->g.b_hnp_enable = 1;
344 musb_try_b_hnp_enable(musb);
345 break;
346 case USB_DEVICE_A_HNP_SUPPORT:
347 if (!musb->g.is_otg)
348 goto stall;
349 musb->g.a_hnp_support = 1;
350 break;
351 case USB_DEVICE_A_ALT_HNP_SUPPORT:
352 if (!musb->g.is_otg)
353 goto stall;
354 musb->g.a_alt_hnp_support = 1;
355 break;
356 #endif
357 stall:
358 default:
359 handled = -EINVAL;
360 break;
361 }
362 break;
363
364 case USB_RECIP_INTERFACE:
365 break;
366
367 case USB_RECIP_ENDPOINT:{
368 const u8 epnum =
369 ctrlrequest->wIndex & 0x0f;
370 struct musb_ep *musb_ep;
371 struct musb_hw_ep *ep;
372 void __iomem *regs;
373 int is_in;
374 u16 csr;
375
376 if (epnum == 0
377 || epnum >= MUSB_C_NUM_EPS
378 || ctrlrequest->wValue
379 != USB_ENDPOINT_HALT)
380 break;
381
382 ep = musb->endpoints + epnum;
383 regs = ep->regs;
384 is_in = ctrlrequest->wIndex & USB_DIR_IN;
385 if (is_in)
386 musb_ep = &ep->ep_in;
387 else
388 musb_ep = &ep->ep_out;
389 if (!musb_ep->desc)
390 break;
391
392 musb_ep_select(mbase, epnum);
393 if (is_in) {
394 csr = musb_readw(regs,
395 MUSB_TXCSR);
396 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
397 csr |= MUSB_TXCSR_FLUSHFIFO;
398 csr |= MUSB_TXCSR_P_SENDSTALL
399 | MUSB_TXCSR_CLRDATATOG
400 | MUSB_TXCSR_P_WZC_BITS;
401 musb_writew(regs, MUSB_TXCSR,
402 csr);
403 } else {
404 csr = musb_readw(regs,
405 MUSB_RXCSR);
406 csr |= MUSB_RXCSR_P_SENDSTALL
407 | MUSB_RXCSR_FLUSHFIFO
408 | MUSB_RXCSR_CLRDATATOG
409 | MUSB_RXCSR_P_WZC_BITS;
410 musb_writew(regs, MUSB_RXCSR,
411 csr);
412 }
413
414 /* select ep0 again */
415 musb_ep_select(mbase, 0);
416 handled = 1;
417 } break;
418
419 default:
420 /* class, vendor, etc ... delegate */
421 handled = 0;
422 break;
423 }
424 break;
425 default:
426 /* delegate SET_CONFIGURATION, etc */
427 handled = 0;
428 }
429 } else
430 handled = 0;
431 return handled;
432 }
433
434 /* we have an ep0out data packet
435 * Context: caller holds controller lock
436 */
437 static void ep0_rxstate(struct musb *musb)
438 {
439 void __iomem *regs = musb->control_ep->regs;
440 struct usb_request *req;
441 u16 count, csr;
442
443 req = next_ep0_request(musb);
444
445 /* read packet and ack; or stall because of gadget driver bug:
446 * should have provided the rx buffer before setup() returned.
447 */
448 if (req) {
449 void *buf = req->buf + req->actual;
450 unsigned len = req->length - req->actual;
451
452 /* read the buffer */
453 count = musb_readb(regs, MUSB_COUNT0);
454 if (count > len) {
455 req->status = -EOVERFLOW;
456 count = len;
457 }
458 musb_read_fifo(&musb->endpoints[0], count, buf);
459 req->actual += count;
460 csr = MUSB_CSR0_P_SVDRXPKTRDY;
461 if (count < 64 || req->actual == req->length) {
462 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
463 csr |= MUSB_CSR0_P_DATAEND;
464 } else
465 req = NULL;
466 } else
467 csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
468
469
470 /* Completion handler may choose to stall, e.g. because the
471 * message just received holds invalid data.
472 */
473 if (req) {
474 musb->ackpend = csr;
475 musb_g_ep0_giveback(musb, req);
476 if (!musb->ackpend)
477 return;
478 musb->ackpend = 0;
479 }
480 musb_ep_select(musb->mregs, 0);
481 musb_writew(regs, MUSB_CSR0, csr);
482 }
483
484 /*
485 * transmitting to the host (IN), this code might be called from IRQ
486 * and from kernel thread.
487 *
488 * Context: caller holds controller lock
489 */
490 static void ep0_txstate(struct musb *musb)
491 {
492 void __iomem *regs = musb->control_ep->regs;
493 struct usb_request *request = next_ep0_request(musb);
494 u16 csr = MUSB_CSR0_TXPKTRDY;
495 u8 *fifo_src;
496 u8 fifo_count;
497
498 if (!request) {
499 /* WARN_ON(1); */
500 DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
501 return;
502 }
503
504 /* load the data */
505 fifo_src = (u8 *) request->buf + request->actual;
506 fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
507 request->length - request->actual);
508 musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
509 request->actual += fifo_count;
510
511 /* update the flags */
512 if (fifo_count < MUSB_MAX_END0_PACKET
513 || request->actual == request->length) {
514 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
515 csr |= MUSB_CSR0_P_DATAEND;
516 } else
517 request = NULL;
518
519 /* report completions as soon as the fifo's loaded; there's no
520 * win in waiting till this last packet gets acked. (other than
521 * very precise fault reporting, needed by USB TMC; possible with
522 * this hardware, but not usable from portable gadget drivers.)
523 */
524 if (request) {
525 musb->ackpend = csr;
526 musb_g_ep0_giveback(musb, request);
527 if (!musb->ackpend)
528 return;
529 musb->ackpend = 0;
530 }
531
532 /* send it out, triggering a "txpktrdy cleared" irq */
533 musb_ep_select(musb->mregs, 0);
534 musb_writew(regs, MUSB_CSR0, csr);
535 }
536
537 /*
538 * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
539 * Fields are left in USB byte-order.
540 *
541 * Context: caller holds controller lock.
542 */
543 static void
544 musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
545 {
546 struct usb_request *r;
547 void __iomem *regs = musb->control_ep->regs;
548
549 musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
550
551 /* NOTE: earlier 2.6 versions changed setup packets to host
552 * order, but now USB packets always stay in USB byte order.
553 */
554 DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
555 req->bRequestType,
556 req->bRequest,
557 le16_to_cpu(req->wValue),
558 le16_to_cpu(req->wIndex),
559 le16_to_cpu(req->wLength));
560
561 /* clean up any leftover transfers */
562 r = next_ep0_request(musb);
563 if (r)
564 musb_g_ep0_giveback(musb, r);
565
566 /* For zero-data requests we want to delay the STATUS stage to
567 * avoid SETUPEND errors. If we read data (OUT), delay accepting
568 * packets until there's a buffer to store them in.
569 *
570 * If we write data, the controller acts happier if we enable
571 * the TX FIFO right away, and give the controller a moment
572 * to switch modes...
573 */
574 musb->set_address = false;
575 musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
576 if (req->wLength == 0) {
577 if (req->bRequestType & USB_DIR_IN)
578 musb->ackpend |= MUSB_CSR0_TXPKTRDY;
579 musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
580 } else if (req->bRequestType & USB_DIR_IN) {
581 musb->ep0_state = MUSB_EP0_STAGE_TX;
582 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
583 while ((musb_readw(regs, MUSB_CSR0)
584 & MUSB_CSR0_RXPKTRDY) != 0)
585 cpu_relax();
586 musb->ackpend = 0;
587 } else
588 musb->ep0_state = MUSB_EP0_STAGE_RX;
589 }
590
591 static int
592 forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
593 __releases(musb->lock)
594 __acquires(musb->lock)
595 {
596 int retval;
597 if (!musb->gadget_driver)
598 return -EOPNOTSUPP;
599 spin_unlock(&musb->lock);
600 retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
601 spin_lock(&musb->lock);
602 return retval;
603 }
604
605 /*
606 * Handle peripheral ep0 interrupt
607 *
608 * Context: irq handler; we won't re-enter the driver that way.
609 */
610 irqreturn_t musb_g_ep0_irq(struct musb *musb)
611 {
612 u16 csr;
613 u16 len;
614 void __iomem *mbase = musb->mregs;
615 void __iomem *regs = musb->endpoints[0].regs;
616 irqreturn_t retval = IRQ_NONE;
617
618 musb_ep_select(mbase, 0); /* select ep0 */
619 csr = musb_readw(regs, MUSB_CSR0);
620 len = musb_readb(regs, MUSB_COUNT0);
621
622 DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
623 csr, len,
624 musb_readb(mbase, MUSB_FADDR),
625 decode_ep0stage(musb->ep0_state));
626
627 /* I sent a stall.. need to acknowledge it now.. */
628 if (csr & MUSB_CSR0_P_SENTSTALL) {
629 musb_writew(regs, MUSB_CSR0,
630 csr & ~MUSB_CSR0_P_SENTSTALL);
631 retval = IRQ_HANDLED;
632 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
633 csr = musb_readw(regs, MUSB_CSR0);
634 }
635
636 /* request ended "early" */
637 if (csr & MUSB_CSR0_P_SETUPEND) {
638 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
639 retval = IRQ_HANDLED;
640 /* Transition into the early status phase */
641 switch (musb->ep0_state) {
642 case MUSB_EP0_STAGE_TX:
643 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
644 break;
645 case MUSB_EP0_STAGE_RX:
646 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
647 break;
648 default:
649 ERR("SetupEnd came in a wrong ep0stage %s\n",
650 decode_ep0stage(musb->ep0_state));
651 }
652 csr = musb_readw(regs, MUSB_CSR0);
653 /* NOTE: request may need completion */
654 }
655
656 /* docs from Mentor only describe tx, rx, and idle/setup states.
657 * we need to handle nuances around status stages, and also the
658 * case where status and setup stages come back-to-back ...
659 */
660 switch (musb->ep0_state) {
661
662 case MUSB_EP0_STAGE_TX:
663 /* irq on clearing txpktrdy */
664 if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
665 ep0_txstate(musb);
666 retval = IRQ_HANDLED;
667 }
668 break;
669
670 case MUSB_EP0_STAGE_RX:
671 /* irq on set rxpktrdy */
672 if (csr & MUSB_CSR0_RXPKTRDY) {
673 ep0_rxstate(musb);
674 retval = IRQ_HANDLED;
675 }
676 break;
677
678 case MUSB_EP0_STAGE_STATUSIN:
679 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
680
681 /* update address (if needed) only @ the end of the
682 * status phase per usb spec, which also guarantees
683 * we get 10 msec to receive this irq... until this
684 * is done we won't see the next packet.
685 */
686 if (musb->set_address) {
687 musb->set_address = false;
688 musb_writeb(mbase, MUSB_FADDR, musb->address);
689 }
690
691 /* enter test mode if needed (exit by reset) */
692 else if (musb->test_mode) {
693 DBG(1, "entering TESTMODE\n");
694
695 if (MUSB_TEST_PACKET == musb->test_mode_nr)
696 musb_load_testpacket(musb);
697
698 musb_writeb(mbase, MUSB_TESTMODE,
699 musb->test_mode_nr);
700 }
701 /* FALLTHROUGH */
702
703 case MUSB_EP0_STAGE_STATUSOUT:
704 /* end of sequence #1: write to host (TX state) */
705 {
706 struct usb_request *req;
707
708 req = next_ep0_request(musb);
709 if (req)
710 musb_g_ep0_giveback(musb, req);
711 }
712
713 /*
714 * In case when several interrupts can get coalesced,
715 * check to see if we've already received a SETUP packet...
716 */
717 if (csr & MUSB_CSR0_RXPKTRDY)
718 goto setup;
719
720 retval = IRQ_HANDLED;
721 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
722 break;
723
724 case MUSB_EP0_STAGE_IDLE:
725 /*
726 * This state is typically (but not always) indiscernible
727 * from the status states since the corresponding interrupts
728 * tend to happen within too little period of time (with only
729 * a zero-length packet in between) and so get coalesced...
730 */
731 retval = IRQ_HANDLED;
732 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
733 /* FALLTHROUGH */
734
735 case MUSB_EP0_STAGE_SETUP:
736 setup:
737 if (csr & MUSB_CSR0_RXPKTRDY) {
738 struct usb_ctrlrequest setup;
739 int handled = 0;
740
741 if (len != 8) {
742 ERR("SETUP packet len %d != 8 ?\n", len);
743 break;
744 }
745 musb_read_setup(musb, &setup);
746 retval = IRQ_HANDLED;
747
748 /* sometimes the RESET won't be reported */
749 if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
750 u8 power;
751
752 printk(KERN_NOTICE "%s: peripheral reset "
753 "irq lost!\n",
754 musb_driver_name);
755 power = musb_readb(mbase, MUSB_POWER);
756 musb->g.speed = (power & MUSB_POWER_HSMODE)
757 ? USB_SPEED_HIGH : USB_SPEED_FULL;
758
759 }
760
761 switch (musb->ep0_state) {
762
763 /* sequence #3 (no data stage), includes requests
764 * we can't forward (notably SET_ADDRESS and the
765 * device/endpoint feature set/clear operations)
766 * plus SET_CONFIGURATION and others we must
767 */
768 case MUSB_EP0_STAGE_ACKWAIT:
769 handled = service_zero_data_request(
770 musb, &setup);
771
772 /*
773 * We're expecting no data in any case, so
774 * always set the DATAEND bit -- doing this
775 * here helps avoid SetupEnd interrupt coming
776 * in the idle stage when we're stalling...
777 */
778 musb->ackpend |= MUSB_CSR0_P_DATAEND;
779
780 /* status stage might be immediate */
781 if (handled > 0)
782 musb->ep0_state =
783 MUSB_EP0_STAGE_STATUSIN;
784 break;
785
786 /* sequence #1 (IN to host), includes GET_STATUS
787 * requests that we can't forward, GET_DESCRIPTOR
788 * and others that we must
789 */
790 case MUSB_EP0_STAGE_TX:
791 handled = service_in_request(musb, &setup);
792 if (handled > 0) {
793 musb->ackpend = MUSB_CSR0_TXPKTRDY
794 | MUSB_CSR0_P_DATAEND;
795 musb->ep0_state =
796 MUSB_EP0_STAGE_STATUSOUT;
797 }
798 break;
799
800 /* sequence #2 (OUT from host), always forward */
801 default: /* MUSB_EP0_STAGE_RX */
802 break;
803 }
804
805 DBG(3, "handled %d, csr %04x, ep0stage %s\n",
806 handled, csr,
807 decode_ep0stage(musb->ep0_state));
808
809 /* unless we need to delegate this to the gadget
810 * driver, we know how to wrap this up: csr0 has
811 * not yet been written.
812 */
813 if (handled < 0)
814 goto stall;
815 else if (handled > 0)
816 goto finish;
817
818 handled = forward_to_driver(musb, &setup);
819 if (handled < 0) {
820 musb_ep_select(mbase, 0);
821 stall:
822 DBG(3, "stall (%d)\n", handled);
823 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
824 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
825 finish:
826 musb_writew(regs, MUSB_CSR0,
827 musb->ackpend);
828 musb->ackpend = 0;
829 }
830 }
831 break;
832
833 case MUSB_EP0_STAGE_ACKWAIT:
834 /* This should not happen. But happens with tusb6010 with
835 * g_file_storage and high speed. Do nothing.
836 */
837 retval = IRQ_HANDLED;
838 break;
839
840 default:
841 /* "can't happen" */
842 WARN_ON(1);
843 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
844 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
845 break;
846 }
847
848 return retval;
849 }
850
851
852 static int
853 musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
854 {
855 /* always enabled */
856 return -EINVAL;
857 }
858
859 static int musb_g_ep0_disable(struct usb_ep *e)
860 {
861 /* always enabled */
862 return -EINVAL;
863 }
864
865 static int
866 musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
867 {
868 struct musb_ep *ep;
869 struct musb_request *req;
870 struct musb *musb;
871 int status;
872 unsigned long lockflags;
873 void __iomem *regs;
874
875 if (!e || !r)
876 return -EINVAL;
877
878 ep = to_musb_ep(e);
879 musb = ep->musb;
880 regs = musb->control_ep->regs;
881
882 req = to_musb_request(r);
883 req->musb = musb;
884 req->request.actual = 0;
885 req->request.status = -EINPROGRESS;
886 req->tx = ep->is_in;
887
888 spin_lock_irqsave(&musb->lock, lockflags);
889
890 if (!list_empty(&ep->req_list)) {
891 status = -EBUSY;
892 goto cleanup;
893 }
894
895 switch (musb->ep0_state) {
896 case MUSB_EP0_STAGE_RX: /* control-OUT data */
897 case MUSB_EP0_STAGE_TX: /* control-IN data */
898 case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
899 status = 0;
900 break;
901 default:
902 DBG(1, "ep0 request queued in state %d\n",
903 musb->ep0_state);
904 status = -EINVAL;
905 goto cleanup;
906 }
907
908 /* add request to the list */
909 list_add_tail(&(req->request.list), &(ep->req_list));
910
911 DBG(3, "queue to %s (%s), length=%d\n",
912 ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
913 req->request.length);
914
915 musb_ep_select(musb->mregs, 0);
916
917 /* sequence #1, IN ... start writing the data */
918 if (musb->ep0_state == MUSB_EP0_STAGE_TX)
919 ep0_txstate(musb);
920
921 /* sequence #3, no-data ... issue IN status */
922 else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
923 if (req->request.length)
924 status = -EINVAL;
925 else {
926 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
927 musb_writew(regs, MUSB_CSR0,
928 musb->ackpend | MUSB_CSR0_P_DATAEND);
929 musb->ackpend = 0;
930 musb_g_ep0_giveback(ep->musb, r);
931 }
932
933 /* else for sequence #2 (OUT), caller provides a buffer
934 * before the next packet arrives. deferred responses
935 * (after SETUP is acked) are racey.
936 */
937 } else if (musb->ackpend) {
938 musb_writew(regs, MUSB_CSR0, musb->ackpend);
939 musb->ackpend = 0;
940 }
941
942 cleanup:
943 spin_unlock_irqrestore(&musb->lock, lockflags);
944 return status;
945 }
946
947 static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
948 {
949 /* we just won't support this */
950 return -EINVAL;
951 }
952
953 static int musb_g_ep0_halt(struct usb_ep *e, int value)
954 {
955 struct musb_ep *ep;
956 struct musb *musb;
957 void __iomem *base, *regs;
958 unsigned long flags;
959 int status;
960 u16 csr;
961
962 if (!e || !value)
963 return -EINVAL;
964
965 ep = to_musb_ep(e);
966 musb = ep->musb;
967 base = musb->mregs;
968 regs = musb->control_ep->regs;
969 status = 0;
970
971 spin_lock_irqsave(&musb->lock, flags);
972
973 if (!list_empty(&ep->req_list)) {
974 status = -EBUSY;
975 goto cleanup;
976 }
977
978 musb_ep_select(base, 0);
979 csr = musb->ackpend;
980
981 switch (musb->ep0_state) {
982
983 /* Stalls are usually issued after parsing SETUP packet, either
984 * directly in irq context from setup() or else later.
985 */
986 case MUSB_EP0_STAGE_TX: /* control-IN data */
987 case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
988 case MUSB_EP0_STAGE_RX: /* control-OUT data */
989 csr = musb_readw(regs, MUSB_CSR0);
990 /* FALLTHROUGH */
991
992 /* It's also OK to issue stalls during callbacks when a non-empty
993 * DATA stage buffer has been read (or even written).
994 */
995 case MUSB_EP0_STAGE_STATUSIN: /* control-OUT status */
996 case MUSB_EP0_STAGE_STATUSOUT: /* control-IN status */
997
998 csr |= MUSB_CSR0_P_SENDSTALL;
999 musb_writew(regs, MUSB_CSR0, csr);
1000 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
1001 musb->ackpend = 0;
1002 break;
1003 default:
1004 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
1005 status = -EINVAL;
1006 }
1007
1008 cleanup:
1009 spin_unlock_irqrestore(&musb->lock, flags);
1010 return status;
1011 }
1012
1013 const struct usb_ep_ops musb_g_ep0_ops = {
1014 .enable = musb_g_ep0_enable,
1015 .disable = musb_g_ep0_disable,
1016 .alloc_request = musb_alloc_request,
1017 .free_request = musb_free_request,
1018 .queue = musb_g_ep0_queue,
1019 .dequeue = musb_g_ep0_dequeue,
1020 .set_halt = musb_g_ep0_halt,
1021 };
1022
|
This page was automatically generated by the
LXR engine.
|