1 /*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #ifndef __LINUX_XHCI_HCD_H
24 #define __LINUX_XHCI_HCD_H
25
26 #include <linux/usb.h>
27 #include <linux/timer.h>
28 #include <linux/kernel.h>
29
30 #include "../core/hcd.h"
31 /* Code sharing between pci-quirks and xhci hcd */
32 #include "xhci-ext-caps.h"
33
34 /* xHCI PCI Configuration Registers */
35 #define XHCI_SBRN_OFFSET (0x60)
36
37 /* Max number of USB devices for any host controller - limit in section 6.1 */
38 #define MAX_HC_SLOTS 256
39 /* Section 5.3.3 - MaxPorts */
40 #define MAX_HC_PORTS 127
41
42 /*
43 * xHCI register interface.
44 * This corresponds to the eXtensible Host Controller Interface (xHCI)
45 * Revision 0.95 specification
46 */
47
48 /**
49 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
50 * @hc_capbase: length of the capabilities register and HC version number
51 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
52 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
53 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
54 * @hcc_params: HCCPARAMS - Capability Parameters
55 * @db_off: DBOFF - Doorbell array offset
56 * @run_regs_off: RTSOFF - Runtime register space offset
57 */
58 struct xhci_cap_regs {
59 u32 hc_capbase;
60 u32 hcs_params1;
61 u32 hcs_params2;
62 u32 hcs_params3;
63 u32 hcc_params;
64 u32 db_off;
65 u32 run_regs_off;
66 /* Reserved up to (CAPLENGTH - 0x1C) */
67 };
68
69 /* hc_capbase bitmasks */
70 /* bits 7:0 - how long is the Capabilities register */
71 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
72 /* bits 31:16 */
73 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
74
75 /* HCSPARAMS1 - hcs_params1 - bitmasks */
76 /* bits 0:7, Max Device Slots */
77 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
78 #define HCS_SLOTS_MASK 0xff
79 /* bits 8:18, Max Interrupters */
80 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
81 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
82 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
83
84 /* HCSPARAMS2 - hcs_params2 - bitmasks */
85 /* bits 0:3, frames or uframes that SW needs to queue transactions
86 * ahead of the HW to meet periodic deadlines */
87 #define HCS_IST(p) (((p) >> 0) & 0xf)
88 /* bits 4:7, max number of Event Ring segments */
89 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
90 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
91 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
92 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
93
94 /* HCSPARAMS3 - hcs_params3 - bitmasks */
95 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
96 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
97 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
98 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
99
100 /* HCCPARAMS - hcc_params - bitmasks */
101 /* true: HC can use 64-bit address pointers */
102 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
103 /* true: HC can do bandwidth negotiation */
104 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
105 /* true: HC uses 64-byte Device Context structures
106 * FIXME 64-byte context structures aren't supported yet.
107 */
108 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
109 /* true: HC has port power switches */
110 #define HCC_PPC(p) ((p) & (1 << 3))
111 /* true: HC has port indicators */
112 #define HCS_INDICATOR(p) ((p) & (1 << 4))
113 /* true: HC has Light HC Reset Capability */
114 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
115 /* true: HC supports latency tolerance messaging */
116 #define HCC_LTC(p) ((p) & (1 << 6))
117 /* true: no secondary Stream ID Support */
118 #define HCC_NSS(p) ((p) & (1 << 7))
119 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
120 #define HCC_MAX_PSA (1 << ((((p) >> 12) & 0xf) + 1))
121 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
122 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
123
124 /* db_off bitmask - bits 0:1 reserved */
125 #define DBOFF_MASK (~0x3)
126
127 /* run_regs_off bitmask - bits 0:4 reserved */
128 #define RTSOFF_MASK (~0x1f)
129
130
131 /* Number of registers per port */
132 #define NUM_PORT_REGS 4
133
134 /**
135 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
136 * @command: USBCMD - xHC command register
137 * @status: USBSTS - xHC status register
138 * @page_size: This indicates the page size that the host controller
139 * supports. If bit n is set, the HC supports a page size
140 * of 2^(n+12), up to a 128MB page size.
141 * 4K is the minimum page size.
142 * @cmd_ring: CRP - 64-bit Command Ring Pointer
143 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
144 * @config_reg: CONFIG - Configure Register
145 * @port_status_base: PORTSCn - base address for Port Status and Control
146 * Each port has a Port Status and Control register,
147 * followed by a Port Power Management Status and Control
148 * register, a Port Link Info register, and a reserved
149 * register.
150 * @port_power_base: PORTPMSCn - base address for
151 * Port Power Management Status and Control
152 * @port_link_base: PORTLIn - base address for Port Link Info (current
153 * Link PM state and control) for USB 2.1 and USB 3.0
154 * devices.
155 */
156 struct xhci_op_regs {
157 u32 command;
158 u32 status;
159 u32 page_size;
160 u32 reserved1;
161 u32 reserved2;
162 u32 dev_notification;
163 u64 cmd_ring;
164 /* rsvd: offset 0x20-2F */
165 u32 reserved3[4];
166 u64 dcbaa_ptr;
167 u32 config_reg;
168 /* rsvd: offset 0x3C-3FF */
169 u32 reserved4[241];
170 /* port 1 registers, which serve as a base address for other ports */
171 u32 port_status_base;
172 u32 port_power_base;
173 u32 port_link_base;
174 u32 reserved5;
175 /* registers for ports 2-255 */
176 u32 reserved6[NUM_PORT_REGS*254];
177 };
178
179 /* USBCMD - USB command - command bitmasks */
180 /* start/stop HC execution - do not write unless HC is halted*/
181 #define CMD_RUN XHCI_CMD_RUN
182 /* Reset HC - resets internal HC state machine and all registers (except
183 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
184 * The xHCI driver must reinitialize the xHC after setting this bit.
185 */
186 #define CMD_RESET (1 << 1)
187 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
188 #define CMD_EIE XHCI_CMD_EIE
189 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
190 #define CMD_HSEIE XHCI_CMD_HSEIE
191 /* bits 4:6 are reserved (and should be preserved on writes). */
192 /* light reset (port status stays unchanged) - reset completed when this is 0 */
193 #define CMD_LRESET (1 << 7)
194 /* FIXME: ignoring host controller save/restore state for now. */
195 #define CMD_CSS (1 << 8)
196 #define CMD_CRS (1 << 9)
197 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
198 #define CMD_EWE XHCI_CMD_EWE
199 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
200 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
201 * '' means the xHC can power it off if all ports are in the disconnect,
202 * disabled, or powered-off state.
203 */
204 #define CMD_PM_INDEX (1 << 11)
205 /* bits 12:31 are reserved (and should be preserved on writes). */
206
207 /* USBSTS - USB status - status bitmasks */
208 /* HC not running - set to 1 when run/stop bit is cleared. */
209 #define STS_HALT XHCI_STS_HALT
210 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
211 #define STS_FATAL (1 << 2)
212 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
213 #define STS_EINT (1 << 3)
214 /* port change detect */
215 #define STS_PORT (1 << 4)
216 /* bits 5:7 reserved and zeroed */
217 /* save state status - '1' means xHC is saving state */
218 #define STS_SAVE (1 << 8)
219 /* restore state status - '1' means xHC is restoring state */
220 #define STS_RESTORE (1 << 9)
221 /* true: save or restore error */
222 #define STS_SRE (1 << 10)
223 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
224 #define STS_CNR XHCI_STS_CNR
225 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
226 #define STS_HCE (1 << 12)
227 /* bits 13:31 reserved and should be preserved */
228
229 /*
230 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
231 * Generate a device notification event when the HC sees a transaction with a
232 * notification type that matches a bit set in this bit field.
233 */
234 #define DEV_NOTE_MASK (0xffff)
235 #define ENABLE_DEV_NOTE(x) (1 << x)
236 /* Most of the device notification types should only be used for debug.
237 * SW does need to pay attention to function wake notifications.
238 */
239 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
240
241 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
242 /* bit 0 is the command ring cycle state */
243 /* stop ring operation after completion of the currently executing command */
244 #define CMD_RING_PAUSE (1 << 1)
245 /* stop ring immediately - abort the currently executing command */
246 #define CMD_RING_ABORT (1 << 2)
247 /* true: command ring is running */
248 #define CMD_RING_RUNNING (1 << 3)
249 /* bits 4:5 reserved and should be preserved */
250 /* Command Ring pointer - bit mask for the lower 32 bits. */
251 #define CMD_RING_RSVD_BITS (0x3f)
252
253 /* CONFIG - Configure Register - config_reg bitmasks */
254 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
255 #define MAX_DEVS(p) ((p) & 0xff)
256 /* bits 8:31 - reserved and should be preserved */
257
258 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
259 /* true: device connected */
260 #define PORT_CONNECT (1 << 0)
261 /* true: port enabled */
262 #define PORT_PE (1 << 1)
263 /* bit 2 reserved and zeroed */
264 /* true: port has an over-current condition */
265 #define PORT_OC (1 << 3)
266 /* true: port reset signaling asserted */
267 #define PORT_RESET (1 << 4)
268 /* Port Link State - bits 5:8
269 * A read gives the current link PM state of the port,
270 * a write with Link State Write Strobe set sets the link state.
271 */
272 /* true: port has power (see HCC_PPC) */
273 #define PORT_POWER (1 << 9)
274 /* bits 10:13 indicate device speed:
275 * 0 - undefined speed - port hasn't be initialized by a reset yet
276 * 1 - full speed
277 * 2 - low speed
278 * 3 - high speed
279 * 4 - super speed
280 * 5-15 reserved
281 */
282 #define DEV_SPEED_MASK (0xf << 10)
283 #define XDEV_FS (0x1 << 10)
284 #define XDEV_LS (0x2 << 10)
285 #define XDEV_HS (0x3 << 10)
286 #define XDEV_SS (0x4 << 10)
287 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
288 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
289 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
290 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
291 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
292 /* Bits 20:23 in the Slot Context are the speed for the device */
293 #define SLOT_SPEED_FS (XDEV_FS << 10)
294 #define SLOT_SPEED_LS (XDEV_LS << 10)
295 #define SLOT_SPEED_HS (XDEV_HS << 10)
296 #define SLOT_SPEED_SS (XDEV_SS << 10)
297 /* Port Indicator Control */
298 #define PORT_LED_OFF (0 << 14)
299 #define PORT_LED_AMBER (1 << 14)
300 #define PORT_LED_GREEN (2 << 14)
301 #define PORT_LED_MASK (3 << 14)
302 /* Port Link State Write Strobe - set this when changing link state */
303 #define PORT_LINK_STROBE (1 << 16)
304 /* true: connect status change */
305 #define PORT_CSC (1 << 17)
306 /* true: port enable change */
307 #define PORT_PEC (1 << 18)
308 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
309 * into an enabled state, and the device into the default state. A "warm" reset
310 * also resets the link, forcing the device through the link training sequence.
311 * SW can also look at the Port Reset register to see when warm reset is done.
312 */
313 #define PORT_WRC (1 << 19)
314 /* true: over-current change */
315 #define PORT_OCC (1 << 20)
316 /* true: reset change - 1 to 0 transition of PORT_RESET */
317 #define PORT_RC (1 << 21)
318 /* port link status change - set on some port link state transitions:
319 * Transition Reason
320 * ------------------------------------------------------------------------------
321 * - U3 to Resume Wakeup signaling from a device
322 * - Resume to Recovery to U0 USB 3.0 device resume
323 * - Resume to U0 USB 2.0 device resume
324 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
325 * - U3 to U0 Software resume of USB 2.0 device complete
326 * - U2 to U0 L1 resume of USB 2.1 device complete
327 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
328 * - U0 to disabled L1 entry error with USB 2.1 device
329 * - Any state to inactive Error on USB 3.0 port
330 */
331 #define PORT_PLC (1 << 22)
332 /* port configure error change - port failed to configure its link partner */
333 #define PORT_CEC (1 << 23)
334 /* bit 24 reserved */
335 /* wake on connect (enable) */
336 #define PORT_WKCONN_E (1 << 25)
337 /* wake on disconnect (enable) */
338 #define PORT_WKDISC_E (1 << 26)
339 /* wake on over-current (enable) */
340 #define PORT_WKOC_E (1 << 27)
341 /* bits 28:29 reserved */
342 /* true: device is removable - for USB 3.0 roothub emulation */
343 #define PORT_DEV_REMOVE (1 << 30)
344 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
345 #define PORT_WR (1 << 31)
346
347 /* Port Power Management Status and Control - port_power_base bitmasks */
348 /* Inactivity timer value for transitions into U1, in microseconds.
349 * Timeout can be up to 127us. 0xFF means an infinite timeout.
350 */
351 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
352 /* Inactivity timer value for transitions into U2 */
353 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
354 /* Bits 24:31 for port testing */
355
356
357 /**
358 * struct xhci_intr_reg - Interrupt Register Set
359 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
360 * interrupts and check for pending interrupts.
361 * @irq_control: IMOD - Interrupt Moderation Register.
362 * Used to throttle interrupts.
363 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
364 * @erst_base: ERST base address.
365 * @erst_dequeue: Event ring dequeue pointer.
366 *
367 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
368 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
369 * multiple segments of the same size. The HC places events on the ring and
370 * "updates the Cycle bit in the TRBs to indicate to software the current
371 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
372 * updates the dequeue pointer.
373 */
374 struct xhci_intr_reg {
375 u32 irq_pending;
376 u32 irq_control;
377 u32 erst_size;
378 u32 rsvd;
379 u64 erst_base;
380 u64 erst_dequeue;
381 };
382
383 /* irq_pending bitmasks */
384 #define ER_IRQ_PENDING(p) ((p) & 0x1)
385 /* bits 2:31 need to be preserved */
386 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
387 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
388 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
389 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
390
391 /* irq_control bitmasks */
392 /* Minimum interval between interrupts (in 250ns intervals). The interval
393 * between interrupts will be longer if there are no events on the event ring.
394 * Default is 4000 (1 ms).
395 */
396 #define ER_IRQ_INTERVAL_MASK (0xffff)
397 /* Counter used to count down the time to the next interrupt - HW use only */
398 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
399
400 /* erst_size bitmasks */
401 /* Preserve bits 16:31 of erst_size */
402 #define ERST_SIZE_MASK (0xffff << 16)
403
404 /* erst_dequeue bitmasks */
405 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
406 * where the current dequeue pointer lies. This is an optional HW hint.
407 */
408 #define ERST_DESI_MASK (0x7)
409 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
410 * a work queue (or delayed service routine)?
411 */
412 #define ERST_EHB (1 << 3)
413 #define ERST_PTR_MASK (0xf)
414
415 /**
416 * struct xhci_run_regs
417 * @microframe_index:
418 * MFINDEX - current microframe number
419 *
420 * Section 5.5 Host Controller Runtime Registers:
421 * "Software should read and write these registers using only Dword (32 bit)
422 * or larger accesses"
423 */
424 struct xhci_run_regs {
425 u32 microframe_index;
426 u32 rsvd[7];
427 struct xhci_intr_reg ir_set[128];
428 };
429
430 /**
431 * struct doorbell_array
432 *
433 * Section 5.6
434 */
435 struct xhci_doorbell_array {
436 u32 doorbell[256];
437 };
438
439 #define DB_TARGET_MASK 0xFFFFFF00
440 #define DB_STREAM_ID_MASK 0x0000FFFF
441 #define DB_TARGET_HOST 0x0
442 #define DB_STREAM_ID_HOST 0x0
443 #define DB_MASK (0xff << 8)
444
445 /* Endpoint Target - bits 0:7 */
446 #define EPI_TO_DB(p) (((p) + 1) & 0xff)
447
448
449 /**
450 * struct xhci_container_ctx
451 * @type: Type of context. Used to calculated offsets to contained contexts.
452 * @size: Size of the context data
453 * @bytes: The raw context data given to HW
454 * @dma: dma address of the bytes
455 *
456 * Represents either a Device or Input context. Holds a pointer to the raw
457 * memory used for the context (bytes) and dma address of it (dma).
458 */
459 struct xhci_container_ctx {
460 unsigned type;
461 #define XHCI_CTX_TYPE_DEVICE 0x1
462 #define XHCI_CTX_TYPE_INPUT 0x2
463
464 int size;
465
466 u8 *bytes;
467 dma_addr_t dma;
468 };
469
470 /**
471 * struct xhci_slot_ctx
472 * @dev_info: Route string, device speed, hub info, and last valid endpoint
473 * @dev_info2: Max exit latency for device number, root hub port number
474 * @tt_info: tt_info is used to construct split transaction tokens
475 * @dev_state: slot state and device address
476 *
477 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
478 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
479 * reserved at the end of the slot context for HC internal use.
480 */
481 struct xhci_slot_ctx {
482 u32 dev_info;
483 u32 dev_info2;
484 u32 tt_info;
485 u32 dev_state;
486 /* offset 0x10 to 0x1f reserved for HC internal use */
487 u32 reserved[4];
488 };
489
490 /* dev_info bitmasks */
491 /* Route String - 0:19 */
492 #define ROUTE_STRING_MASK (0xfffff)
493 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
494 #define DEV_SPEED (0xf << 20)
495 /* bit 24 reserved */
496 /* Is this LS/FS device connected through a HS hub? - bit 25 */
497 #define DEV_MTT (0x1 << 25)
498 /* Set if the device is a hub - bit 26 */
499 #define DEV_HUB (0x1 << 26)
500 /* Index of the last valid endpoint context in this device context - 27:31 */
501 #define LAST_CTX_MASK (0x1f << 27)
502 #define LAST_CTX(p) ((p) << 27)
503 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
504 #define SLOT_FLAG (1 << 0)
505 #define EP0_FLAG (1 << 1)
506
507 /* dev_info2 bitmasks */
508 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
509 #define MAX_EXIT (0xffff)
510 /* Root hub port number that is needed to access the USB device */
511 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
512
513 /* tt_info bitmasks */
514 /*
515 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
516 * The Slot ID of the hub that isolates the high speed signaling from
517 * this low or full-speed device. '' if attached to root hub port.
518 */
519 #define TT_SLOT (0xff)
520 /*
521 * The number of the downstream facing port of the high-speed hub
522 * '' if the device is not low or full speed.
523 */
524 #define TT_PORT (0xff << 8)
525
526 /* dev_state bitmasks */
527 /* USB device address - assigned by the HC */
528 #define DEV_ADDR_MASK (0xff)
529 /* bits 8:26 reserved */
530 /* Slot state */
531 #define SLOT_STATE (0x1f << 27)
532 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
533
534
535 /**
536 * struct xhci_ep_ctx
537 * @ep_info: endpoint state, streams, mult, and interval information.
538 * @ep_info2: information on endpoint type, max packet size, max burst size,
539 * error count, and whether the HC will force an event for all
540 * transactions.
541 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
542 * defines one stream, this points to the endpoint transfer ring.
543 * Otherwise, it points to a stream context array, which has a
544 * ring pointer for each flow.
545 * @tx_info:
546 * Average TRB lengths for the endpoint ring and
547 * max payload within an Endpoint Service Interval Time (ESIT).
548 *
549 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
550 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
551 * reserved at the end of the endpoint context for HC internal use.
552 */
553 struct xhci_ep_ctx {
554 u32 ep_info;
555 u32 ep_info2;
556 u64 deq;
557 u32 tx_info;
558 /* offset 0x14 - 0x1f reserved for HC internal use */
559 u32 reserved[3];
560 };
561
562 /* ep_info bitmasks */
563 /*
564 * Endpoint State - bits 0:2
565 * 0 - disabled
566 * 1 - running
567 * 2 - halted due to halt condition - ok to manipulate endpoint ring
568 * 3 - stopped
569 * 4 - TRB error
570 * 5-7 - reserved
571 */
572 #define EP_STATE_MASK (0xf)
573 #define EP_STATE_DISABLED 0
574 #define EP_STATE_RUNNING 1
575 #define EP_STATE_HALTED 2
576 #define EP_STATE_STOPPED 3
577 #define EP_STATE_ERROR 4
578 /* Mult - Max number of burtst within an interval, in EP companion desc. */
579 #define EP_MULT(p) ((p & 0x3) << 8)
580 /* bits 10:14 are Max Primary Streams */
581 /* bit 15 is Linear Stream Array */
582 /* Interval - period between requests to an endpoint - 125u increments. */
583 #define EP_INTERVAL(p) ((p & 0xff) << 16)
584 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
585
586 /* ep_info2 bitmasks */
587 /*
588 * Force Event - generate transfer events for all TRBs for this endpoint
589 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
590 */
591 #define FORCE_EVENT (0x1)
592 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
593 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
594 #define EP_TYPE(p) ((p) << 3)
595 #define ISOC_OUT_EP 1
596 #define BULK_OUT_EP 2
597 #define INT_OUT_EP 3
598 #define CTRL_EP 4
599 #define ISOC_IN_EP 5
600 #define BULK_IN_EP 6
601 #define INT_IN_EP 7
602 /* bit 6 reserved */
603 /* bit 7 is Host Initiate Disable - for disabling stream selection */
604 #define MAX_BURST(p) (((p)&0xff) << 8)
605 #define MAX_PACKET(p) (((p)&0xffff) << 16)
606 #define MAX_PACKET_MASK (0xffff << 16)
607 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
608
609
610 /**
611 * struct xhci_input_control_context
612 * Input control context; see section 6.2.5.
613 *
614 * @drop_context: set the bit of the endpoint context you want to disable
615 * @add_context: set the bit of the endpoint context you want to enable
616 */
617 struct xhci_input_control_ctx {
618 u32 drop_flags;
619 u32 add_flags;
620 u32 rsvd2[6];
621 };
622
623 /* drop context bitmasks */
624 #define DROP_EP(x) (0x1 << x)
625 /* add context bitmasks */
626 #define ADD_EP(x) (0x1 << x)
627
628 struct xhci_virt_device {
629 /*
630 * Commands to the hardware are passed an "input context" that
631 * tells the hardware what to change in its data structures.
632 * The hardware will return changes in an "output context" that
633 * software must allocate for the hardware. We need to keep
634 * track of input and output contexts separately because
635 * these commands might fail and we don't trust the hardware.
636 */
637 struct xhci_container_ctx *out_ctx;
638 /* Used for addressing devices and configuration changes */
639 struct xhci_container_ctx *in_ctx;
640
641 /* FIXME when stream support is added */
642 struct xhci_ring *ep_rings[31];
643 /* Temporary storage in case the configure endpoint command fails and we
644 * have to restore the device state to the previous state
645 */
646 struct xhci_ring *new_ep_rings[31];
647 struct completion cmd_completion;
648 /* Status of the last command issued for this device */
649 u32 cmd_status;
650 };
651
652
653 /**
654 * struct xhci_device_context_array
655 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
656 */
657 struct xhci_device_context_array {
658 /* 64-bit device addresses; we only write 32-bit addresses */
659 u64 dev_context_ptrs[MAX_HC_SLOTS];
660 /* private xHCD pointers */
661 dma_addr_t dma;
662 };
663 /* TODO: write function to set the 64-bit device DMA address */
664 /*
665 * TODO: change this to be dynamically sized at HC mem init time since the HC
666 * might not be able to handle the maximum number of devices possible.
667 */
668
669
670 struct xhci_stream_ctx {
671 /* 64-bit stream ring address, cycle state, and stream type */
672 u64 stream_ring;
673 /* offset 0x14 - 0x1f reserved for HC internal use */
674 u32 reserved[2];
675 };
676
677
678 struct xhci_transfer_event {
679 /* 64-bit buffer address, or immediate data */
680 u64 buffer;
681 u32 transfer_len;
682 /* This field is interpreted differently based on the type of TRB */
683 u32 flags;
684 };
685
686 /** Transfer Event bit fields **/
687 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
688
689 /* Completion Code - only applicable for some types of TRBs */
690 #define COMP_CODE_MASK (0xff << 24)
691 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
692 #define COMP_SUCCESS 1
693 /* Data Buffer Error */
694 #define COMP_DB_ERR 2
695 /* Babble Detected Error */
696 #define COMP_BABBLE 3
697 /* USB Transaction Error */
698 #define COMP_TX_ERR 4
699 /* TRB Error - some TRB field is invalid */
700 #define COMP_TRB_ERR 5
701 /* Stall Error - USB device is stalled */
702 #define COMP_STALL 6
703 /* Resource Error - HC doesn't have memory for that device configuration */
704 #define COMP_ENOMEM 7
705 /* Bandwidth Error - not enough room in schedule for this dev config */
706 #define COMP_BW_ERR 8
707 /* No Slots Available Error - HC ran out of device slots */
708 #define COMP_ENOSLOTS 9
709 /* Invalid Stream Type Error */
710 #define COMP_STREAM_ERR 10
711 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
712 #define COMP_EBADSLT 11
713 /* Endpoint Not Enabled Error */
714 #define COMP_EBADEP 12
715 /* Short Packet */
716 #define COMP_SHORT_TX 13
717 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
718 #define COMP_UNDERRUN 14
719 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
720 #define COMP_OVERRUN 15
721 /* Virtual Function Event Ring Full Error */
722 #define COMP_VF_FULL 16
723 /* Parameter Error - Context parameter is invalid */
724 #define COMP_EINVAL 17
725 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
726 #define COMP_BW_OVER 18
727 /* Context State Error - illegal context state transition requested */
728 #define COMP_CTX_STATE 19
729 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
730 #define COMP_PING_ERR 20
731 /* Event Ring is full */
732 #define COMP_ER_FULL 21
733 /* Missed Service Error - HC couldn't service an isoc ep within interval */
734 #define COMP_MISSED_INT 23
735 /* Successfully stopped command ring */
736 #define COMP_CMD_STOP 24
737 /* Successfully aborted current command and stopped command ring */
738 #define COMP_CMD_ABORT 25
739 /* Stopped - transfer was terminated by a stop endpoint command */
740 #define COMP_STOP 26
741 /* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */
742 #define COMP_STOP_INVAL 27
743 /* Control Abort Error - Debug Capability - control pipe aborted */
744 #define COMP_DBG_ABORT 28
745 /* TRB type 29 and 30 reserved */
746 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
747 #define COMP_BUFF_OVER 31
748 /* Event Lost Error - xHC has an "internal event overrun condition" */
749 #define COMP_ISSUES 32
750 /* Undefined Error - reported when other error codes don't apply */
751 #define COMP_UNKNOWN 33
752 /* Invalid Stream ID Error */
753 #define COMP_STRID_ERR 34
754 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
755 /* FIXME - check for this */
756 #define COMP_2ND_BW_ERR 35
757 /* Split Transaction Error */
758 #define COMP_SPLIT_ERR 36
759
760 struct xhci_link_trb {
761 /* 64-bit segment pointer*/
762 u64 segment_ptr;
763 u32 intr_target;
764 u32 control;
765 };
766
767 /* control bitfields */
768 #define LINK_TOGGLE (0x1<<1)
769
770 /* Command completion event TRB */
771 struct xhci_event_cmd {
772 /* Pointer to command TRB, or the value passed by the event data trb */
773 u64 cmd_trb;
774 u32 status;
775 u32 flags;
776 };
777
778 /* flags bitmasks */
779 /* bits 16:23 are the virtual function ID */
780 /* bits 24:31 are the slot ID */
781 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
782 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
783
784 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
785 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
786 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
787
788
789 /* Port Status Change Event TRB fields */
790 /* Port ID - bits 31:24 */
791 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
792
793 /* Normal TRB fields */
794 /* transfer_len bitmasks - bits 0:16 */
795 #define TRB_LEN(p) ((p) & 0x1ffff)
796 /* TD size - number of bytes remaining in the TD (including this TRB):
797 * bits 17 - 21. Shift the number of bytes by 10. */
798 #define TD_REMAINDER(p) ((((p) >> 10) & 0x1f) << 17)
799 /* Interrupter Target - which MSI-X vector to target the completion event at */
800 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
801 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
802
803 /* Cycle bit - indicates TRB ownership by HC or HCD */
804 #define TRB_CYCLE (1<<0)
805 /*
806 * Force next event data TRB to be evaluated before task switch.
807 * Used to pass OS data back after a TD completes.
808 */
809 #define TRB_ENT (1<<1)
810 /* Interrupt on short packet */
811 #define TRB_ISP (1<<2)
812 /* Set PCIe no snoop attribute */
813 #define TRB_NO_SNOOP (1<<3)
814 /* Chain multiple TRBs into a TD */
815 #define TRB_CHAIN (1<<4)
816 /* Interrupt on completion */
817 #define TRB_IOC (1<<5)
818 /* The buffer pointer contains immediate data */
819 #define TRB_IDT (1<<6)
820
821
822 /* Control transfer TRB specific fields */
823 #define TRB_DIR_IN (1<<16)
824
825 struct xhci_generic_trb {
826 u32 field[4];
827 };
828
829 union xhci_trb {
830 struct xhci_link_trb link;
831 struct xhci_transfer_event trans_event;
832 struct xhci_event_cmd event_cmd;
833 struct xhci_generic_trb generic;
834 };
835
836 /* TRB bit mask */
837 #define TRB_TYPE_BITMASK (0xfc00)
838 #define TRB_TYPE(p) ((p) << 10)
839 /* TRB type IDs */
840 /* bulk, interrupt, isoc scatter/gather, and control data stage */
841 #define TRB_NORMAL 1
842 /* setup stage for control transfers */
843 #define TRB_SETUP 2
844 /* data stage for control transfers */
845 #define TRB_DATA 3
846 /* status stage for control transfers */
847 #define TRB_STATUS 4
848 /* isoc transfers */
849 #define TRB_ISOC 5
850 /* TRB for linking ring segments */
851 #define TRB_LINK 6
852 #define TRB_EVENT_DATA 7
853 /* Transfer Ring No-op (not for the command ring) */
854 #define TRB_TR_NOOP 8
855 /* Command TRBs */
856 /* Enable Slot Command */
857 #define TRB_ENABLE_SLOT 9
858 /* Disable Slot Command */
859 #define TRB_DISABLE_SLOT 10
860 /* Address Device Command */
861 #define TRB_ADDR_DEV 11
862 /* Configure Endpoint Command */
863 #define TRB_CONFIG_EP 12
864 /* Evaluate Context Command */
865 #define TRB_EVAL_CONTEXT 13
866 /* Reset Endpoint Command */
867 #define TRB_RESET_EP 14
868 /* Stop Transfer Ring Command */
869 #define TRB_STOP_RING 15
870 /* Set Transfer Ring Dequeue Pointer Command */
871 #define TRB_SET_DEQ 16
872 /* Reset Device Command */
873 #define TRB_RESET_DEV 17
874 /* Force Event Command (opt) */
875 #define TRB_FORCE_EVENT 18
876 /* Negotiate Bandwidth Command (opt) */
877 #define TRB_NEG_BANDWIDTH 19
878 /* Set Latency Tolerance Value Command (opt) */
879 #define TRB_SET_LT 20
880 /* Get port bandwidth Command */
881 #define TRB_GET_BW 21
882 /* Force Header Command - generate a transaction or link management packet */
883 #define TRB_FORCE_HEADER 22
884 /* No-op Command - not for transfer rings */
885 #define TRB_CMD_NOOP 23
886 /* TRB IDs 24-31 reserved */
887 /* Event TRBS */
888 /* Transfer Event */
889 #define TRB_TRANSFER 32
890 /* Command Completion Event */
891 #define TRB_COMPLETION 33
892 /* Port Status Change Event */
893 #define TRB_PORT_STATUS 34
894 /* Bandwidth Request Event (opt) */
895 #define TRB_BANDWIDTH_EVENT 35
896 /* Doorbell Event (opt) */
897 #define TRB_DOORBELL 36
898 /* Host Controller Event */
899 #define TRB_HC_EVENT 37
900 /* Device Notification Event - device sent function wake notification */
901 #define TRB_DEV_NOTE 38
902 /* MFINDEX Wrap Event - microframe counter wrapped */
903 #define TRB_MFINDEX_WRAP 39
904 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
905
906 /*
907 * TRBS_PER_SEGMENT must be a multiple of 4,
908 * since the command ring is 64-byte aligned.
909 * It must also be greater than 16.
910 */
911 #define TRBS_PER_SEGMENT 64
912 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
913 /* TRB buffer pointers can't cross 64KB boundaries */
914 #define TRB_MAX_BUFF_SHIFT 16
915 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
916
917 struct xhci_segment {
918 union xhci_trb *trbs;
919 /* private to HCD */
920 struct xhci_segment *next;
921 dma_addr_t dma;
922 };
923
924 struct xhci_td {
925 struct list_head td_list;
926 struct list_head cancelled_td_list;
927 struct urb *urb;
928 struct xhci_segment *start_seg;
929 union xhci_trb *first_trb;
930 union xhci_trb *last_trb;
931 };
932
933 struct xhci_dequeue_state {
934 struct xhci_segment *new_deq_seg;
935 union xhci_trb *new_deq_ptr;
936 int new_cycle_state;
937 };
938
939 struct xhci_ring {
940 struct xhci_segment *first_seg;
941 union xhci_trb *enqueue;
942 struct xhci_segment *enq_seg;
943 unsigned int enq_updates;
944 union xhci_trb *dequeue;
945 struct xhci_segment *deq_seg;
946 unsigned int deq_updates;
947 struct list_head td_list;
948 /* ---- Related to URB cancellation ---- */
949 struct list_head cancelled_td_list;
950 unsigned int cancels_pending;
951 unsigned int state;
952 #define SET_DEQ_PENDING (1 << 0)
953 #define EP_HALTED (1 << 1)
954 /* The TRB that was last reported in a stopped endpoint ring */
955 union xhci_trb *stopped_trb;
956 struct xhci_td *stopped_td;
957 /*
958 * Write the cycle state into the TRB cycle field to give ownership of
959 * the TRB to the host controller (if we are the producer), or to check
960 * if we own the TRB (if we are the consumer). See section 4.9.1.
961 */
962 u32 cycle_state;
963 };
964
965 struct xhci_erst_entry {
966 /* 64-bit event ring segment address */
967 u64 seg_addr;
968 u32 seg_size;
969 /* Set to zero */
970 u32 rsvd;
971 };
972
973 struct xhci_erst {
974 struct xhci_erst_entry *entries;
975 unsigned int num_entries;
976 /* xhci->event_ring keeps track of segment dma addresses */
977 dma_addr_t erst_dma_addr;
978 /* Num entries the ERST can contain */
979 unsigned int erst_size;
980 };
981
982 struct xhci_scratchpad {
983 u64 *sp_array;
984 dma_addr_t sp_dma;
985 void **sp_buffers;
986 dma_addr_t *sp_dma_buffers;
987 };
988
989 /*
990 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
991 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
992 * meaning 64 ring segments.
993 * Initial allocated size of the ERST, in number of entries */
994 #define ERST_NUM_SEGS 1
995 /* Initial allocated size of the ERST, in number of entries */
996 #define ERST_SIZE 64
997 /* Initial number of event segment rings allocated */
998 #define ERST_ENTRIES 1
999 /* Poll every 60 seconds */
1000 #define POLL_TIMEOUT 60
1001 /* XXX: Make these module parameters */
1002
1003
1004 /* There is one ehci_hci structure per controller */
1005 struct xhci_hcd {
1006 /* glue to PCI and HCD framework */
1007 struct xhci_cap_regs __iomem *cap_regs;
1008 struct xhci_op_regs __iomem *op_regs;
1009 struct xhci_run_regs __iomem *run_regs;
1010 struct xhci_doorbell_array __iomem *dba;
1011 /* Our HCD's current interrupter register set */
1012 struct xhci_intr_reg __iomem *ir_set;
1013
1014 /* Cached register copies of read-only HC data */
1015 __u32 hcs_params1;
1016 __u32 hcs_params2;
1017 __u32 hcs_params3;
1018 __u32 hcc_params;
1019
1020 spinlock_t lock;
1021
1022 /* packed release number */
1023 u8 sbrn;
1024 u16 hci_version;
1025 u8 max_slots;
1026 u8 max_interrupters;
1027 u8 max_ports;
1028 u8 isoc_threshold;
1029 int event_ring_max;
1030 int addr_64;
1031 /* 4KB min, 128MB max */
1032 int page_size;
1033 /* Valid values are 12 to 20, inclusive */
1034 int page_shift;
1035 /* only one MSI vector for now, but might need more later */
1036 int msix_count;
1037 struct msix_entry *msix_entries;
1038 /* data structures */
1039 struct xhci_device_context_array *dcbaa;
1040 struct xhci_ring *cmd_ring;
1041 struct xhci_ring *event_ring;
1042 struct xhci_erst erst;
1043 /* Scratchpad */
1044 struct xhci_scratchpad *scratchpad;
1045
1046 /* slot enabling and address device helpers */
1047 struct completion addr_dev;
1048 int slot_id;
1049 /* Internal mirror of the HW's dcbaa */
1050 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1051
1052 /* DMA pools */
1053 struct dma_pool *device_pool;
1054 struct dma_pool *segment_pool;
1055
1056 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1057 /* Poll the rings - for debugging */
1058 struct timer_list event_ring_timer;
1059 int zombie;
1060 #endif
1061 /* Statistics */
1062 int noops_submitted;
1063 int noops_handled;
1064 int error_bitmask;
1065 unsigned int quirks;
1066 #define XHCI_LINK_TRB_QUIRK (1 << 0)
1067 #define XHCI_RESET_EP_QUIRK (1 << 1)
1068 };
1069
1070 /* For testing purposes */
1071 #define NUM_TEST_NOOPS 0
1072
1073 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1074 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1075 {
1076 return (struct xhci_hcd *) (hcd->hcd_priv);
1077 }
1078
1079 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1080 {
1081 return container_of((void *) xhci, struct usb_hcd, hcd_priv);
1082 }
1083
1084 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1085 #define XHCI_DEBUG 1
1086 #else
1087 #define XHCI_DEBUG 0
1088 #endif
1089
1090 #define xhci_dbg(xhci, fmt, args...) \
1091 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1092 #define xhci_info(xhci, fmt, args...) \
1093 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1094 #define xhci_err(xhci, fmt, args...) \
1095 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1096 #define xhci_warn(xhci, fmt, args...) \
1097 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1098
1099 /* TODO: copied from ehci.h - can be refactored? */
1100 /* xHCI spec says all registers are little endian */
1101 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1102 __u32 __iomem *regs)
1103 {
1104 return readl(regs);
1105 }
1106 static inline void xhci_writel(struct xhci_hcd *xhci,
1107 const unsigned int val, __u32 __iomem *regs)
1108 {
1109 xhci_dbg(xhci,
1110 "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n",
1111 regs, val);
1112 writel(val, regs);
1113 }
1114
1115 /*
1116 * Registers should always be accessed with double word or quad word accesses.
1117 *
1118 * Some xHCI implementations may support 64-bit address pointers. Registers
1119 * with 64-bit address pointers should be written to with dword accesses by
1120 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1121 * xHCI implementations that do not support 64-bit address pointers will ignore
1122 * the high dword, and write order is irrelevant.
1123 */
1124 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1125 __u64 __iomem *regs)
1126 {
1127 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1128 u64 val_lo = readl(ptr);
1129 u64 val_hi = readl(ptr + 1);
1130 return val_lo + (val_hi << 32);
1131 }
1132 static inline void xhci_write_64(struct xhci_hcd *xhci,
1133 const u64 val, __u64 __iomem *regs)
1134 {
1135 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1136 u32 val_lo = lower_32_bits(val);
1137 u32 val_hi = upper_32_bits(val);
1138
1139 xhci_dbg(xhci,
1140 "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n",
1141 regs, (long unsigned int) val);
1142 writel(val_lo, ptr);
1143 writel(val_hi, ptr + 1);
1144 }
1145
1146 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1147 {
1148 u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
1149 return ((HC_VERSION(temp) == 0x95) &&
1150 (xhci->quirks & XHCI_LINK_TRB_QUIRK));
1151 }
1152
1153 /* xHCI debugging */
1154 void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num);
1155 void xhci_print_registers(struct xhci_hcd *xhci);
1156 void xhci_dbg_regs(struct xhci_hcd *xhci);
1157 void xhci_print_run_regs(struct xhci_hcd *xhci);
1158 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1159 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1160 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1161 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1162 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1163 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1164 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1165 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1166
1167 /* xHCI memory managment */
1168 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1169 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1170 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1171 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1172 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1173 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1174 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1175 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1176 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1177 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1178 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1179 struct xhci_virt_device *vdev, unsigned int ep_index);
1180 void xhci_slot_copy(struct xhci_hcd *xhci, struct xhci_virt_device *vdev);
1181 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1182 struct usb_device *udev, struct usb_host_endpoint *ep,
1183 gfp_t mem_flags);
1184 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1185
1186 #ifdef CONFIG_PCI
1187 /* xHCI PCI glue */
1188 int xhci_register_pci(void);
1189 void xhci_unregister_pci(void);
1190 #endif
1191
1192 /* xHCI host controller glue */
1193 int xhci_halt(struct xhci_hcd *xhci);
1194 int xhci_reset(struct xhci_hcd *xhci);
1195 int xhci_init(struct usb_hcd *hcd);
1196 int xhci_run(struct usb_hcd *hcd);
1197 void xhci_stop(struct usb_hcd *hcd);
1198 void xhci_shutdown(struct usb_hcd *hcd);
1199 int xhci_get_frame(struct usb_hcd *hcd);
1200 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1201 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1202 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1203 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1204 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1205 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1206 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1207 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1208 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1209 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1210 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1211
1212 /* xHCI ring, segment, TRB, and TD functions */
1213 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1214 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1215 void *xhci_setup_one_noop(struct xhci_hcd *xhci);
1216 void xhci_handle_event(struct xhci_hcd *xhci);
1217 void xhci_set_hc_event_deq(struct xhci_hcd *xhci);
1218 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1219 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1220 u32 slot_id);
1221 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1222 unsigned int ep_index);
1223 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1224 int slot_id, unsigned int ep_index);
1225 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1226 int slot_id, unsigned int ep_index);
1227 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1228 int slot_id, unsigned int ep_index);
1229 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1230 u32 slot_id);
1231 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1232 u32 slot_id);
1233 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1234 unsigned int ep_index);
1235 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1236 unsigned int slot_id, unsigned int ep_index,
1237 struct xhci_td *cur_td, struct xhci_dequeue_state *state);
1238 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1239 struct xhci_ring *ep_ring, unsigned int slot_id,
1240 unsigned int ep_index, struct xhci_dequeue_state *deq_state);
1241 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1242 struct usb_device *udev,
1243 unsigned int ep_index, struct xhci_ring *ep_ring);
1244 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1245 unsigned int slot_id, unsigned int ep_index,
1246 struct xhci_dequeue_state *deq_state);
1247
1248 /* xHCI roothub code */
1249 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1250 char *buf, u16 wLength);
1251 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1252
1253 /* xHCI contexts */
1254 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1255 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1256 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1257
1258 #endif /* __LINUX_XHCI_HCD_H */
1259
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