1 /*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 /*
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
29 *
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
41 *
42 * Cycle bit rules:
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
47 *
48 * Producer rules:
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
52 * cycle state).
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
56 *
57 * Consumer rules:
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
65 */
66
67 #include <linux/scatterlist.h>
68 #include "xhci.h"
69
70 /*
71 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
72 * address of the TRB.
73 */
74 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
75 union xhci_trb *trb)
76 {
77 unsigned long segment_offset;
78
79 if (!seg || !trb || trb < seg->trbs)
80 return 0;
81 /* offset in TRBs */
82 segment_offset = trb - seg->trbs;
83 if (segment_offset > TRBS_PER_SEGMENT)
84 return 0;
85 return seg->dma + (segment_offset * sizeof(*trb));
86 }
87
88 /* Does this link TRB point to the first segment in a ring,
89 * or was the previous TRB the last TRB on the last segment in the ERST?
90 */
91 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
92 struct xhci_segment *seg, union xhci_trb *trb)
93 {
94 if (ring == xhci->event_ring)
95 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
96 (seg->next == xhci->event_ring->first_seg);
97 else
98 return trb->link.control & LINK_TOGGLE;
99 }
100
101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
102 * segment? I.e. would the updated event TRB pointer step off the end of the
103 * event seg?
104 */
105 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
106 struct xhci_segment *seg, union xhci_trb *trb)
107 {
108 if (ring == xhci->event_ring)
109 return trb == &seg->trbs[TRBS_PER_SEGMENT];
110 else
111 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
112 }
113
114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
115 * TRB is in a new segment. This does not skip over link TRBs, and it does not
116 * effect the ring dequeue or enqueue pointers.
117 */
118 static void next_trb(struct xhci_hcd *xhci,
119 struct xhci_ring *ring,
120 struct xhci_segment **seg,
121 union xhci_trb **trb)
122 {
123 if (last_trb(xhci, ring, *seg, *trb)) {
124 *seg = (*seg)->next;
125 *trb = ((*seg)->trbs);
126 } else {
127 *trb = (*trb)++;
128 }
129 }
130
131 /*
132 * See Cycle bit rules. SW is the consumer for the event ring only.
133 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
134 */
135 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
136 {
137 union xhci_trb *next = ++(ring->dequeue);
138 unsigned long long addr;
139
140 ring->deq_updates++;
141 /* Update the dequeue pointer further if that was a link TRB or we're at
142 * the end of an event ring segment (which doesn't have link TRBS)
143 */
144 while (last_trb(xhci, ring, ring->deq_seg, next)) {
145 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
146 ring->cycle_state = (ring->cycle_state ? 0 : 1);
147 if (!in_interrupt())
148 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
149 ring,
150 (unsigned int) ring->cycle_state);
151 }
152 ring->deq_seg = ring->deq_seg->next;
153 ring->dequeue = ring->deq_seg->trbs;
154 next = ring->dequeue;
155 }
156 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
157 if (ring == xhci->event_ring)
158 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
159 else if (ring == xhci->cmd_ring)
160 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
161 else
162 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
163 }
164
165 /*
166 * See Cycle bit rules. SW is the consumer for the event ring only.
167 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
168 *
169 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
170 * chain bit is set), then set the chain bit in all the following link TRBs.
171 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
172 * have their chain bit cleared (so that each Link TRB is a separate TD).
173 *
174 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
175 * set, but other sections talk about dealing with the chain bit set. This was
176 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
177 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
178 */
179 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
180 {
181 u32 chain;
182 union xhci_trb *next;
183 unsigned long long addr;
184
185 chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
186 next = ++(ring->enqueue);
187
188 ring->enq_updates++;
189 /* Update the dequeue pointer further if that was a link TRB or we're at
190 * the end of an event ring segment (which doesn't have link TRBS)
191 */
192 while (last_trb(xhci, ring, ring->enq_seg, next)) {
193 if (!consumer) {
194 if (ring != xhci->event_ring) {
195 /* If we're not dealing with 0.95 hardware,
196 * carry over the chain bit of the previous TRB
197 * (which may mean the chain bit is cleared).
198 */
199 if (!xhci_link_trb_quirk(xhci)) {
200 next->link.control &= ~TRB_CHAIN;
201 next->link.control |= chain;
202 }
203 /* Give this link TRB to the hardware */
204 wmb();
205 if (next->link.control & TRB_CYCLE)
206 next->link.control &= (u32) ~TRB_CYCLE;
207 else
208 next->link.control |= (u32) TRB_CYCLE;
209 }
210 /* Toggle the cycle bit after the last ring segment. */
211 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
212 ring->cycle_state = (ring->cycle_state ? 0 : 1);
213 if (!in_interrupt())
214 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
215 ring,
216 (unsigned int) ring->cycle_state);
217 }
218 }
219 ring->enq_seg = ring->enq_seg->next;
220 ring->enqueue = ring->enq_seg->trbs;
221 next = ring->enqueue;
222 }
223 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
224 if (ring == xhci->event_ring)
225 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
226 else if (ring == xhci->cmd_ring)
227 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
228 else
229 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
230 }
231
232 /*
233 * Check to see if there's room to enqueue num_trbs on the ring. See rules
234 * above.
235 * FIXME: this would be simpler and faster if we just kept track of the number
236 * of free TRBs in a ring.
237 */
238 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
239 unsigned int num_trbs)
240 {
241 int i;
242 union xhci_trb *enq = ring->enqueue;
243 struct xhci_segment *enq_seg = ring->enq_seg;
244
245 /* Check if ring is empty */
246 if (enq == ring->dequeue)
247 return 1;
248 /* Make sure there's an extra empty TRB available */
249 for (i = 0; i <= num_trbs; ++i) {
250 if (enq == ring->dequeue)
251 return 0;
252 enq++;
253 while (last_trb(xhci, ring, enq_seg, enq)) {
254 enq_seg = enq_seg->next;
255 enq = enq_seg->trbs;
256 }
257 }
258 return 1;
259 }
260
261 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
262 {
263 u64 temp;
264 dma_addr_t deq;
265
266 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
267 xhci->event_ring->dequeue);
268 if (deq == 0 && !in_interrupt())
269 xhci_warn(xhci, "WARN something wrong with SW event ring "
270 "dequeue ptr.\n");
271 /* Update HC event ring dequeue pointer */
272 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
273 temp &= ERST_PTR_MASK;
274 /* Don't clear the EHB bit (which is RW1C) because
275 * there might be more events to service.
276 */
277 temp &= ~ERST_EHB;
278 xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
279 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
280 &xhci->ir_set->erst_dequeue);
281 }
282
283 /* Ring the host controller doorbell after placing a command on the ring */
284 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
285 {
286 u32 temp;
287
288 xhci_dbg(xhci, "// Ding dong!\n");
289 temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
290 xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
291 /* Flush PCI posted writes */
292 xhci_readl(xhci, &xhci->dba->doorbell[0]);
293 }
294
295 static void ring_ep_doorbell(struct xhci_hcd *xhci,
296 unsigned int slot_id,
297 unsigned int ep_index)
298 {
299 struct xhci_ring *ep_ring;
300 u32 field;
301 __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
302
303 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
304 /* Don't ring the doorbell for this endpoint if there are pending
305 * cancellations because the we don't want to interrupt processing.
306 */
307 if (!ep_ring->cancels_pending && !(ep_ring->state & SET_DEQ_PENDING)
308 && !(ep_ring->state & EP_HALTED)) {
309 field = xhci_readl(xhci, db_addr) & DB_MASK;
310 xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr);
311 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
312 * isn't time-critical and we shouldn't make the CPU wait for
313 * the flush.
314 */
315 xhci_readl(xhci, db_addr);
316 }
317 }
318
319 /*
320 * Find the segment that trb is in. Start searching in start_seg.
321 * If we must move past a segment that has a link TRB with a toggle cycle state
322 * bit set, then we will toggle the value pointed at by cycle_state.
323 */
324 static struct xhci_segment *find_trb_seg(
325 struct xhci_segment *start_seg,
326 union xhci_trb *trb, int *cycle_state)
327 {
328 struct xhci_segment *cur_seg = start_seg;
329 struct xhci_generic_trb *generic_trb;
330
331 while (cur_seg->trbs > trb ||
332 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
333 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
334 if (TRB_TYPE(generic_trb->field[3]) == TRB_LINK &&
335 (generic_trb->field[3] & LINK_TOGGLE))
336 *cycle_state = ~(*cycle_state) & 0x1;
337 cur_seg = cur_seg->next;
338 if (cur_seg == start_seg)
339 /* Looped over the entire list. Oops! */
340 return 0;
341 }
342 return cur_seg;
343 }
344
345 /*
346 * Move the xHC's endpoint ring dequeue pointer past cur_td.
347 * Record the new state of the xHC's endpoint ring dequeue segment,
348 * dequeue pointer, and new consumer cycle state in state.
349 * Update our internal representation of the ring's dequeue pointer.
350 *
351 * We do this in three jumps:
352 * - First we update our new ring state to be the same as when the xHC stopped.
353 * - Then we traverse the ring to find the segment that contains
354 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
355 * any link TRBs with the toggle cycle bit set.
356 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
357 * if we've moved it past a link TRB with the toggle cycle bit set.
358 */
359 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
360 unsigned int slot_id, unsigned int ep_index,
361 struct xhci_td *cur_td, struct xhci_dequeue_state *state)
362 {
363 struct xhci_virt_device *dev = xhci->devs[slot_id];
364 struct xhci_ring *ep_ring = dev->ep_rings[ep_index];
365 struct xhci_generic_trb *trb;
366 struct xhci_ep_ctx *ep_ctx;
367 dma_addr_t addr;
368
369 state->new_cycle_state = 0;
370 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
371 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
372 ep_ring->stopped_trb,
373 &state->new_cycle_state);
374 if (!state->new_deq_seg)
375 BUG();
376 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
377 xhci_dbg(xhci, "Finding endpoint context\n");
378 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
379 state->new_cycle_state = 0x1 & ep_ctx->deq;
380
381 state->new_deq_ptr = cur_td->last_trb;
382 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
383 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
384 state->new_deq_ptr,
385 &state->new_cycle_state);
386 if (!state->new_deq_seg)
387 BUG();
388
389 trb = &state->new_deq_ptr->generic;
390 if (TRB_TYPE(trb->field[3]) == TRB_LINK &&
391 (trb->field[3] & LINK_TOGGLE))
392 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
393 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
394
395 /* Don't update the ring cycle state for the producer (us). */
396 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
397 state->new_deq_seg);
398 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
399 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
400 (unsigned long long) addr);
401 xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
402 ep_ring->dequeue = state->new_deq_ptr;
403 ep_ring->deq_seg = state->new_deq_seg;
404 }
405
406 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
407 struct xhci_td *cur_td)
408 {
409 struct xhci_segment *cur_seg;
410 union xhci_trb *cur_trb;
411
412 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
413 true;
414 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
415 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
416 TRB_TYPE(TRB_LINK)) {
417 /* Unchain any chained Link TRBs, but
418 * leave the pointers intact.
419 */
420 cur_trb->generic.field[3] &= ~TRB_CHAIN;
421 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
422 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
423 "in seg %p (0x%llx dma)\n",
424 cur_trb,
425 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
426 cur_seg,
427 (unsigned long long)cur_seg->dma);
428 } else {
429 cur_trb->generic.field[0] = 0;
430 cur_trb->generic.field[1] = 0;
431 cur_trb->generic.field[2] = 0;
432 /* Preserve only the cycle bit of this TRB */
433 cur_trb->generic.field[3] &= TRB_CYCLE;
434 cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
435 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
436 "in seg %p (0x%llx dma)\n",
437 cur_trb,
438 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
439 cur_seg,
440 (unsigned long long)cur_seg->dma);
441 }
442 if (cur_trb == cur_td->last_trb)
443 break;
444 }
445 }
446
447 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
448 unsigned int ep_index, struct xhci_segment *deq_seg,
449 union xhci_trb *deq_ptr, u32 cycle_state);
450
451 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
452 struct xhci_ring *ep_ring, unsigned int slot_id,
453 unsigned int ep_index, struct xhci_dequeue_state *deq_state)
454 {
455 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
456 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
457 deq_state->new_deq_seg,
458 (unsigned long long)deq_state->new_deq_seg->dma,
459 deq_state->new_deq_ptr,
460 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
461 deq_state->new_cycle_state);
462 queue_set_tr_deq(xhci, slot_id, ep_index,
463 deq_state->new_deq_seg,
464 deq_state->new_deq_ptr,
465 (u32) deq_state->new_cycle_state);
466 /* Stop the TD queueing code from ringing the doorbell until
467 * this command completes. The HC won't set the dequeue pointer
468 * if the ring is running, and ringing the doorbell starts the
469 * ring running.
470 */
471 ep_ring->state |= SET_DEQ_PENDING;
472 }
473
474 /*
475 * When we get a command completion for a Stop Endpoint Command, we need to
476 * unlink any cancelled TDs from the ring. There are two ways to do that:
477 *
478 * 1. If the HW was in the middle of processing the TD that needs to be
479 * cancelled, then we must move the ring's dequeue pointer past the last TRB
480 * in the TD with a Set Dequeue Pointer Command.
481 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
482 * bit cleared) so that the HW will skip over them.
483 */
484 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
485 union xhci_trb *trb)
486 {
487 unsigned int slot_id;
488 unsigned int ep_index;
489 struct xhci_ring *ep_ring;
490 struct list_head *entry;
491 struct xhci_td *cur_td = 0;
492 struct xhci_td *last_unlinked_td;
493
494 struct xhci_dequeue_state deq_state;
495 #ifdef CONFIG_USB_HCD_STAT
496 ktime_t stop_time = ktime_get();
497 #endif
498
499 memset(&deq_state, 0, sizeof(deq_state));
500 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
501 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
502 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
503
504 if (list_empty(&ep_ring->cancelled_td_list))
505 return;
506
507 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
508 * We have the xHCI lock, so nothing can modify this list until we drop
509 * it. We're also in the event handler, so we can't get re-interrupted
510 * if another Stop Endpoint command completes
511 */
512 list_for_each(entry, &ep_ring->cancelled_td_list) {
513 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
514 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
515 cur_td->first_trb,
516 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
517 /*
518 * If we stopped on the TD we need to cancel, then we have to
519 * move the xHC endpoint ring dequeue pointer past this TD.
520 */
521 if (cur_td == ep_ring->stopped_td)
522 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, cur_td,
523 &deq_state);
524 else
525 td_to_noop(xhci, ep_ring, cur_td);
526 /*
527 * The event handler won't see a completion for this TD anymore,
528 * so remove it from the endpoint ring's TD list. Keep it in
529 * the cancelled TD list for URB completion later.
530 */
531 list_del(&cur_td->td_list);
532 ep_ring->cancels_pending--;
533 }
534 last_unlinked_td = cur_td;
535
536 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
537 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
538 xhci_queue_new_dequeue_state(xhci, ep_ring,
539 slot_id, ep_index, &deq_state);
540 xhci_ring_cmd_db(xhci);
541 } else {
542 /* Otherwise just ring the doorbell to restart the ring */
543 ring_ep_doorbell(xhci, slot_id, ep_index);
544 }
545
546 /*
547 * Drop the lock and complete the URBs in the cancelled TD list.
548 * New TDs to be cancelled might be added to the end of the list before
549 * we can complete all the URBs for the TDs we already unlinked.
550 * So stop when we've completed the URB for the last TD we unlinked.
551 */
552 do {
553 cur_td = list_entry(ep_ring->cancelled_td_list.next,
554 struct xhci_td, cancelled_td_list);
555 list_del(&cur_td->cancelled_td_list);
556
557 /* Clean up the cancelled URB */
558 #ifdef CONFIG_USB_HCD_STAT
559 hcd_stat_update(xhci->tp_stat, cur_td->urb->actual_length,
560 ktime_sub(stop_time, cur_td->start_time));
561 #endif
562 cur_td->urb->hcpriv = NULL;
563 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), cur_td->urb);
564
565 xhci_dbg(xhci, "Giveback cancelled URB %p\n", cur_td->urb);
566 spin_unlock(&xhci->lock);
567 /* Doesn't matter what we pass for status, since the core will
568 * just overwrite it (because the URB has been unlinked).
569 */
570 usb_hcd_giveback_urb(xhci_to_hcd(xhci), cur_td->urb, 0);
571 kfree(cur_td);
572
573 spin_lock(&xhci->lock);
574 } while (cur_td != last_unlinked_td);
575
576 /* Return to the event handler with xhci->lock re-acquired */
577 }
578
579 /*
580 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
581 * we need to clear the set deq pending flag in the endpoint ring state, so that
582 * the TD queueing code can ring the doorbell again. We also need to ring the
583 * endpoint doorbell to restart the ring, but only if there aren't more
584 * cancellations pending.
585 */
586 static void handle_set_deq_completion(struct xhci_hcd *xhci,
587 struct xhci_event_cmd *event,
588 union xhci_trb *trb)
589 {
590 unsigned int slot_id;
591 unsigned int ep_index;
592 struct xhci_ring *ep_ring;
593 struct xhci_virt_device *dev;
594 struct xhci_ep_ctx *ep_ctx;
595 struct xhci_slot_ctx *slot_ctx;
596
597 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
598 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
599 dev = xhci->devs[slot_id];
600 ep_ring = dev->ep_rings[ep_index];
601 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
602 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
603
604 if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
605 unsigned int ep_state;
606 unsigned int slot_state;
607
608 switch (GET_COMP_CODE(event->status)) {
609 case COMP_TRB_ERR:
610 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
611 "of stream ID configuration\n");
612 break;
613 case COMP_CTX_STATE:
614 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
615 "to incorrect slot or ep state.\n");
616 ep_state = ep_ctx->ep_info;
617 ep_state &= EP_STATE_MASK;
618 slot_state = slot_ctx->dev_state;
619 slot_state = GET_SLOT_STATE(slot_state);
620 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
621 slot_state, ep_state);
622 break;
623 case COMP_EBADSLT:
624 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
625 "slot %u was not enabled.\n", slot_id);
626 break;
627 default:
628 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
629 "completion code of %u.\n",
630 GET_COMP_CODE(event->status));
631 break;
632 }
633 /* OK what do we do now? The endpoint state is hosed, and we
634 * should never get to this point if the synchronization between
635 * queueing, and endpoint state are correct. This might happen
636 * if the device gets disconnected after we've finished
637 * cancelling URBs, which might not be an error...
638 */
639 } else {
640 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
641 ep_ctx->deq);
642 }
643
644 ep_ring->state &= ~SET_DEQ_PENDING;
645 ring_ep_doorbell(xhci, slot_id, ep_index);
646 }
647
648 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
649 struct xhci_event_cmd *event,
650 union xhci_trb *trb)
651 {
652 int slot_id;
653 unsigned int ep_index;
654 struct xhci_ring *ep_ring;
655
656 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
657 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
658 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
659 /* This command will only fail if the endpoint wasn't halted,
660 * but we don't care.
661 */
662 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
663 (unsigned int) GET_COMP_CODE(event->status));
664
665 /* HW with the reset endpoint quirk needs to have a configure endpoint
666 * command complete before the endpoint can be used. Queue that here
667 * because the HW can't handle two commands being queued in a row.
668 */
669 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
670 xhci_dbg(xhci, "Queueing configure endpoint command\n");
671 xhci_queue_configure_endpoint(xhci,
672 xhci->devs[slot_id]->in_ctx->dma, slot_id);
673 xhci_ring_cmd_db(xhci);
674 } else {
675 /* Clear our internal halted state and restart the ring */
676 ep_ring->state &= ~EP_HALTED;
677 ring_ep_doorbell(xhci, slot_id, ep_index);
678 }
679 }
680
681 static void handle_cmd_completion(struct xhci_hcd *xhci,
682 struct xhci_event_cmd *event)
683 {
684 int slot_id = TRB_TO_SLOT_ID(event->flags);
685 u64 cmd_dma;
686 dma_addr_t cmd_dequeue_dma;
687 struct xhci_input_control_ctx *ctrl_ctx;
688 unsigned int ep_index;
689 struct xhci_ring *ep_ring;
690 unsigned int ep_state;
691
692 cmd_dma = event->cmd_trb;
693 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
694 xhci->cmd_ring->dequeue);
695 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
696 if (cmd_dequeue_dma == 0) {
697 xhci->error_bitmask |= 1 << 4;
698 return;
699 }
700 /* Does the DMA address match our internal dequeue pointer address? */
701 if (cmd_dma != (u64) cmd_dequeue_dma) {
702 xhci->error_bitmask |= 1 << 5;
703 return;
704 }
705 switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
706 case TRB_TYPE(TRB_ENABLE_SLOT):
707 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
708 xhci->slot_id = slot_id;
709 else
710 xhci->slot_id = 0;
711 complete(&xhci->addr_dev);
712 break;
713 case TRB_TYPE(TRB_DISABLE_SLOT):
714 if (xhci->devs[slot_id])
715 xhci_free_virt_device(xhci, slot_id);
716 break;
717 case TRB_TYPE(TRB_CONFIG_EP):
718 /*
719 * Configure endpoint commands can come from the USB core
720 * configuration or alt setting changes, or because the HW
721 * needed an extra configure endpoint command after a reset
722 * endpoint command. In the latter case, the xHCI driver is
723 * not waiting on the configure endpoint command.
724 */
725 ctrl_ctx = xhci_get_input_control_ctx(xhci,
726 xhci->devs[slot_id]->in_ctx);
727 /* Input ctx add_flags are the endpoint index plus one */
728 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
729 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
730 if (!ep_ring) {
731 /* This must have been an initial configure endpoint */
732 xhci->devs[slot_id]->cmd_status =
733 GET_COMP_CODE(event->status);
734 complete(&xhci->devs[slot_id]->cmd_completion);
735 break;
736 }
737 ep_state = ep_ring->state;
738 xhci_dbg(xhci, "Completed config ep cmd - last ep index = %d, "
739 "state = %d\n", ep_index, ep_state);
740 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
741 ep_state & EP_HALTED) {
742 /* Clear our internal halted state and restart ring */
743 xhci->devs[slot_id]->ep_rings[ep_index]->state &=
744 ~EP_HALTED;
745 ring_ep_doorbell(xhci, slot_id, ep_index);
746 } else {
747 xhci->devs[slot_id]->cmd_status =
748 GET_COMP_CODE(event->status);
749 complete(&xhci->devs[slot_id]->cmd_completion);
750 }
751 break;
752 case TRB_TYPE(TRB_EVAL_CONTEXT):
753 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
754 complete(&xhci->devs[slot_id]->cmd_completion);
755 break;
756 case TRB_TYPE(TRB_ADDR_DEV):
757 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
758 complete(&xhci->addr_dev);
759 break;
760 case TRB_TYPE(TRB_STOP_RING):
761 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
762 break;
763 case TRB_TYPE(TRB_SET_DEQ):
764 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
765 break;
766 case TRB_TYPE(TRB_CMD_NOOP):
767 ++xhci->noops_handled;
768 break;
769 case TRB_TYPE(TRB_RESET_EP):
770 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
771 break;
772 default:
773 /* Skip over unknown commands on the event ring */
774 xhci->error_bitmask |= 1 << 6;
775 break;
776 }
777 inc_deq(xhci, xhci->cmd_ring, false);
778 }
779
780 static void handle_port_status(struct xhci_hcd *xhci,
781 union xhci_trb *event)
782 {
783 u32 port_id;
784
785 /* Port status change events always have a successful completion code */
786 if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
787 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
788 xhci->error_bitmask |= 1 << 8;
789 }
790 /* FIXME: core doesn't care about all port link state changes yet */
791 port_id = GET_PORT_ID(event->generic.field[0]);
792 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
793
794 /* Update event ring dequeue pointer before dropping the lock */
795 inc_deq(xhci, xhci->event_ring, true);
796 xhci_set_hc_event_deq(xhci);
797
798 spin_unlock(&xhci->lock);
799 /* Pass this up to the core */
800 usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
801 spin_lock(&xhci->lock);
802 }
803
804 /*
805 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
806 * at end_trb, which may be in another segment. If the suspect DMA address is a
807 * TRB in this TD, this function returns that TRB's segment. Otherwise it
808 * returns 0.
809 */
810 static struct xhci_segment *trb_in_td(
811 struct xhci_segment *start_seg,
812 union xhci_trb *start_trb,
813 union xhci_trb *end_trb,
814 dma_addr_t suspect_dma)
815 {
816 dma_addr_t start_dma;
817 dma_addr_t end_seg_dma;
818 dma_addr_t end_trb_dma;
819 struct xhci_segment *cur_seg;
820
821 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
822 cur_seg = start_seg;
823
824 do {
825 if (start_dma == 0)
826 return 0;
827 /* We may get an event for a Link TRB in the middle of a TD */
828 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
829 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
830 /* If the end TRB isn't in this segment, this is set to 0 */
831 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
832
833 if (end_trb_dma > 0) {
834 /* The end TRB is in this segment, so suspect should be here */
835 if (start_dma <= end_trb_dma) {
836 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
837 return cur_seg;
838 } else {
839 /* Case for one segment with
840 * a TD wrapped around to the top
841 */
842 if ((suspect_dma >= start_dma &&
843 suspect_dma <= end_seg_dma) ||
844 (suspect_dma >= cur_seg->dma &&
845 suspect_dma <= end_trb_dma))
846 return cur_seg;
847 }
848 return 0;
849 } else {
850 /* Might still be somewhere in this segment */
851 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
852 return cur_seg;
853 }
854 cur_seg = cur_seg->next;
855 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
856 } while (cur_seg != start_seg);
857
858 return 0;
859 }
860
861 /*
862 * If this function returns an error condition, it means it got a Transfer
863 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
864 * At this point, the host controller is probably hosed and should be reset.
865 */
866 static int handle_tx_event(struct xhci_hcd *xhci,
867 struct xhci_transfer_event *event)
868 {
869 struct xhci_virt_device *xdev;
870 struct xhci_ring *ep_ring;
871 unsigned int slot_id;
872 int ep_index;
873 struct xhci_td *td = 0;
874 dma_addr_t event_dma;
875 struct xhci_segment *event_seg;
876 union xhci_trb *event_trb;
877 struct urb *urb = 0;
878 int status = -EINPROGRESS;
879 struct xhci_ep_ctx *ep_ctx;
880 u32 trb_comp_code;
881
882 xhci_dbg(xhci, "In %s\n", __func__);
883 slot_id = TRB_TO_SLOT_ID(event->flags);
884 xdev = xhci->devs[slot_id];
885 if (!xdev) {
886 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
887 return -ENODEV;
888 }
889
890 /* Endpoint ID is 1 based, our index is zero based */
891 ep_index = TRB_TO_EP_ID(event->flags) - 1;
892 xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
893 ep_ring = xdev->ep_rings[ep_index];
894 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
895 if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
896 xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n");
897 return -ENODEV;
898 }
899
900 event_dma = event->buffer;
901 /* This TRB should be in the TD at the head of this ring's TD list */
902 xhci_dbg(xhci, "%s - checking for list empty\n", __func__);
903 if (list_empty(&ep_ring->td_list)) {
904 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
905 TRB_TO_SLOT_ID(event->flags), ep_index);
906 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
907 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
908 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
909 urb = NULL;
910 goto cleanup;
911 }
912 xhci_dbg(xhci, "%s - getting list entry\n", __func__);
913 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
914
915 /* Is this a TRB in the currently executing TD? */
916 xhci_dbg(xhci, "%s - looking for TD\n", __func__);
917 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
918 td->last_trb, event_dma);
919 xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg);
920 if (!event_seg) {
921 /* HC is busted, give up! */
922 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
923 return -ESHUTDOWN;
924 }
925 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)];
926 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
927 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
928 xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n",
929 lower_32_bits(event->buffer));
930 xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n",
931 upper_32_bits(event->buffer));
932 xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n",
933 (unsigned int) event->transfer_len);
934 xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n",
935 (unsigned int) event->flags);
936
937 /* Look for common error cases */
938 trb_comp_code = GET_COMP_CODE(event->transfer_len);
939 switch (trb_comp_code) {
940 /* Skip codes that require special handling depending on
941 * transfer type
942 */
943 case COMP_SUCCESS:
944 case COMP_SHORT_TX:
945 break;
946 case COMP_STOP:
947 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
948 break;
949 case COMP_STOP_INVAL:
950 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
951 break;
952 case COMP_STALL:
953 xhci_warn(xhci, "WARN: Stalled endpoint\n");
954 ep_ring->state |= EP_HALTED;
955 status = -EPIPE;
956 break;
957 case COMP_TRB_ERR:
958 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
959 status = -EILSEQ;
960 break;
961 case COMP_TX_ERR:
962 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
963 status = -EPROTO;
964 break;
965 case COMP_BABBLE:
966 xhci_warn(xhci, "WARN: babble error on endpoint\n");
967 status = -EOVERFLOW;
968 break;
969 case COMP_DB_ERR:
970 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
971 status = -ENOSR;
972 break;
973 default:
974 xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n");
975 urb = NULL;
976 goto cleanup;
977 }
978 /* Now update the urb's actual_length and give back to the core */
979 /* Was this a control transfer? */
980 if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
981 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
982 switch (trb_comp_code) {
983 case COMP_SUCCESS:
984 if (event_trb == ep_ring->dequeue) {
985 xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
986 status = -ESHUTDOWN;
987 } else if (event_trb != td->last_trb) {
988 xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n");
989 status = -ESHUTDOWN;
990 } else {
991 xhci_dbg(xhci, "Successful control transfer!\n");
992 status = 0;
993 }
994 break;
995 case COMP_SHORT_TX:
996 xhci_warn(xhci, "WARN: short transfer on control ep\n");
997 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
998 status = -EREMOTEIO;
999 else
1000 status = 0;
1001 break;
1002 case COMP_BABBLE:
1003 /* The 0.96 spec says a babbling control endpoint
1004 * is not halted. The 0.96 spec says it is. Some HW
1005 * claims to be 0.95 compliant, but it halts the control
1006 * endpoint anyway. Check if a babble halted the
1007 * endpoint.
1008 */
1009 if (ep_ctx->ep_info != EP_STATE_HALTED)
1010 break;
1011 /* else fall through */
1012 case COMP_STALL:
1013 /* Did we transfer part of the data (middle) phase? */
1014 if (event_trb != ep_ring->dequeue &&
1015 event_trb != td->last_trb)
1016 td->urb->actual_length =
1017 td->urb->transfer_buffer_length
1018 - TRB_LEN(event->transfer_len);
1019 else
1020 td->urb->actual_length = 0;
1021
1022 ep_ring->stopped_td = td;
1023 ep_ring->stopped_trb = event_trb;
1024 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1025 xhci_cleanup_stalled_ring(xhci,
1026 td->urb->dev,
1027 ep_index, ep_ring);
1028 xhci_ring_cmd_db(xhci);
1029 goto td_cleanup;
1030 default:
1031 /* Others already handled above */
1032 break;
1033 }
1034 /*
1035 * Did we transfer any data, despite the errors that might have
1036 * happened? I.e. did we get past the setup stage?
1037 */
1038 if (event_trb != ep_ring->dequeue) {
1039 /* The event was for the status stage */
1040 if (event_trb == td->last_trb) {
1041 if (td->urb->actual_length != 0) {
1042 /* Don't overwrite a previously set error code */
1043 if ((status == -EINPROGRESS ||
1044 status == 0) &&
1045 (td->urb->transfer_flags
1046 & URB_SHORT_NOT_OK))
1047 /* Did we already see a short data stage? */
1048 status = -EREMOTEIO;
1049 } else {
1050 td->urb->actual_length =
1051 td->urb->transfer_buffer_length;
1052 }
1053 } else {
1054 /* Maybe the event was for the data stage? */
1055 if (trb_comp_code != COMP_STOP_INVAL) {
1056 /* We didn't stop on a link TRB in the middle */
1057 td->urb->actual_length =
1058 td->urb->transfer_buffer_length -
1059 TRB_LEN(event->transfer_len);
1060 xhci_dbg(xhci, "Waiting for status stage event\n");
1061 urb = NULL;
1062 goto cleanup;
1063 }
1064 }
1065 }
1066 } else {
1067 switch (trb_comp_code) {
1068 case COMP_SUCCESS:
1069 /* Double check that the HW transferred everything. */
1070 if (event_trb != td->last_trb) {
1071 xhci_warn(xhci, "WARN Successful completion "
1072 "on short TX\n");
1073 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1074 status = -EREMOTEIO;
1075 else
1076 status = 0;
1077 } else {
1078 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1079 xhci_dbg(xhci, "Successful bulk "
1080 "transfer!\n");
1081 else
1082 xhci_dbg(xhci, "Successful interrupt "
1083 "transfer!\n");
1084 status = 0;
1085 }
1086 break;
1087 case COMP_SHORT_TX:
1088 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1089 status = -EREMOTEIO;
1090 else
1091 status = 0;
1092 break;
1093 default:
1094 /* Others already handled above */
1095 break;
1096 }
1097 dev_dbg(&td->urb->dev->dev,
1098 "ep %#x - asked for %d bytes, "
1099 "%d bytes untransferred\n",
1100 td->urb->ep->desc.bEndpointAddress,
1101 td->urb->transfer_buffer_length,
1102 TRB_LEN(event->transfer_len));
1103 /* Fast path - was this the last TRB in the TD for this URB? */
1104 if (event_trb == td->last_trb) {
1105 if (TRB_LEN(event->transfer_len) != 0) {
1106 td->urb->actual_length =
1107 td->urb->transfer_buffer_length -
1108 TRB_LEN(event->transfer_len);
1109 if (td->urb->transfer_buffer_length <
1110 td->urb->actual_length) {
1111 xhci_warn(xhci, "HC gave bad length "
1112 "of %d bytes left\n",
1113 TRB_LEN(event->transfer_len));
1114 td->urb->actual_length = 0;
1115 if (td->urb->transfer_flags &
1116 URB_SHORT_NOT_OK)
1117 status = -EREMOTEIO;
1118 else
1119 status = 0;
1120 }
1121 /* Don't overwrite a previously set error code */
1122 if (status == -EINPROGRESS) {
1123 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1124 status = -EREMOTEIO;
1125 else
1126 status = 0;
1127 }
1128 } else {
1129 td->urb->actual_length = td->urb->transfer_buffer_length;
1130 /* Ignore a short packet completion if the
1131 * untransferred length was zero.
1132 */
1133 if (status == -EREMOTEIO)
1134 status = 0;
1135 }
1136 } else {
1137 /* Slow path - walk the list, starting from the dequeue
1138 * pointer, to get the actual length transferred.
1139 */
1140 union xhci_trb *cur_trb;
1141 struct xhci_segment *cur_seg;
1142
1143 td->urb->actual_length = 0;
1144 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1145 cur_trb != event_trb;
1146 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1147 if (TRB_TYPE(cur_trb->generic.field[3]) != TRB_TR_NOOP &&
1148 TRB_TYPE(cur_trb->generic.field[3]) != TRB_LINK)
1149 td->urb->actual_length +=
1150 TRB_LEN(cur_trb->generic.field[2]);
1151 }
1152 /* If the ring didn't stop on a Link or No-op TRB, add
1153 * in the actual bytes transferred from the Normal TRB
1154 */
1155 if (trb_comp_code != COMP_STOP_INVAL)
1156 td->urb->actual_length +=
1157 TRB_LEN(cur_trb->generic.field[2]) -
1158 TRB_LEN(event->transfer_len);
1159 }
1160 }
1161 if (trb_comp_code == COMP_STOP_INVAL ||
1162 trb_comp_code == COMP_STOP) {
1163 /* The Endpoint Stop Command completion will take care of any
1164 * stopped TDs. A stopped TD may be restarted, so don't update
1165 * the ring dequeue pointer or take this TD off any lists yet.
1166 */
1167 ep_ring->stopped_td = td;
1168 ep_ring->stopped_trb = event_trb;
1169 } else {
1170 if (trb_comp_code == COMP_STALL ||
1171 trb_comp_code == COMP_BABBLE) {
1172 /* The transfer is completed from the driver's
1173 * perspective, but we need to issue a set dequeue
1174 * command for this stalled endpoint to move the dequeue
1175 * pointer past the TD. We can't do that here because
1176 * the halt condition must be cleared first.
1177 */
1178 ep_ring->stopped_td = td;
1179 ep_ring->stopped_trb = event_trb;
1180 } else {
1181 /* Update ring dequeue pointer */
1182 while (ep_ring->dequeue != td->last_trb)
1183 inc_deq(xhci, ep_ring, false);
1184 inc_deq(xhci, ep_ring, false);
1185 }
1186
1187 td_cleanup:
1188 /* Clean up the endpoint's TD list */
1189 urb = td->urb;
1190 /* Do one last check of the actual transfer length.
1191 * If the host controller said we transferred more data than
1192 * the buffer length, urb->actual_length will be a very big
1193 * number (since it's unsigned). Play it safe and say we didn't
1194 * transfer anything.
1195 */
1196 if (urb->actual_length > urb->transfer_buffer_length) {
1197 xhci_warn(xhci, "URB transfer length is wrong, "
1198 "xHC issue? req. len = %u, "
1199 "act. len = %u\n",
1200 urb->transfer_buffer_length,
1201 urb->actual_length);
1202 urb->actual_length = 0;
1203 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1204 status = -EREMOTEIO;
1205 else
1206 status = 0;
1207 }
1208 list_del(&td->td_list);
1209 /* Was this TD slated to be cancelled but completed anyway? */
1210 if (!list_empty(&td->cancelled_td_list)) {
1211 list_del(&td->cancelled_td_list);
1212 ep_ring->cancels_pending--;
1213 }
1214 /* Leave the TD around for the reset endpoint function to use
1215 * (but only if it's not a control endpoint, since we already
1216 * queued the Set TR dequeue pointer command for stalled
1217 * control endpoints).
1218 */
1219 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1220 (trb_comp_code != COMP_STALL &&
1221 trb_comp_code != COMP_BABBLE)) {
1222 kfree(td);
1223 }
1224 urb->hcpriv = NULL;
1225 }
1226 cleanup:
1227 inc_deq(xhci, xhci->event_ring, true);
1228 xhci_set_hc_event_deq(xhci);
1229
1230 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1231 if (urb) {
1232 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1233 xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n",
1234 urb, urb->actual_length, status);
1235 spin_unlock(&xhci->lock);
1236 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1237 spin_lock(&xhci->lock);
1238 }
1239 return 0;
1240 }
1241
1242 /*
1243 * This function handles all OS-owned events on the event ring. It may drop
1244 * xhci->lock between event processing (e.g. to pass up port status changes).
1245 */
1246 void xhci_handle_event(struct xhci_hcd *xhci)
1247 {
1248 union xhci_trb *event;
1249 int update_ptrs = 1;
1250 int ret;
1251
1252 xhci_dbg(xhci, "In %s\n", __func__);
1253 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1254 xhci->error_bitmask |= 1 << 1;
1255 return;
1256 }
1257
1258 event = xhci->event_ring->dequeue;
1259 /* Does the HC or OS own the TRB? */
1260 if ((event->event_cmd.flags & TRB_CYCLE) !=
1261 xhci->event_ring->cycle_state) {
1262 xhci->error_bitmask |= 1 << 2;
1263 return;
1264 }
1265 xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1266
1267 /* FIXME: Handle more event types. */
1268 switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1269 case TRB_TYPE(TRB_COMPLETION):
1270 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1271 handle_cmd_completion(xhci, &event->event_cmd);
1272 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1273 break;
1274 case TRB_TYPE(TRB_PORT_STATUS):
1275 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1276 handle_port_status(xhci, event);
1277 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1278 update_ptrs = 0;
1279 break;
1280 case TRB_TYPE(TRB_TRANSFER):
1281 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1282 ret = handle_tx_event(xhci, &event->trans_event);
1283 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1284 if (ret < 0)
1285 xhci->error_bitmask |= 1 << 9;
1286 else
1287 update_ptrs = 0;
1288 break;
1289 default:
1290 xhci->error_bitmask |= 1 << 3;
1291 }
1292
1293 if (update_ptrs) {
1294 /* Update SW and HC event ring dequeue pointer */
1295 inc_deq(xhci, xhci->event_ring, true);
1296 xhci_set_hc_event_deq(xhci);
1297 }
1298 /* Are there more items on the event ring? */
1299 xhci_handle_event(xhci);
1300 }
1301
1302 /**** Endpoint Ring Operations ****/
1303
1304 /*
1305 * Generic function for queueing a TRB on a ring.
1306 * The caller must have checked to make sure there's room on the ring.
1307 */
1308 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1309 bool consumer,
1310 u32 field1, u32 field2, u32 field3, u32 field4)
1311 {
1312 struct xhci_generic_trb *trb;
1313
1314 trb = &ring->enqueue->generic;
1315 trb->field[0] = field1;
1316 trb->field[1] = field2;
1317 trb->field[2] = field3;
1318 trb->field[3] = field4;
1319 inc_enq(xhci, ring, consumer);
1320 }
1321
1322 /*
1323 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1324 * FIXME allocate segments if the ring is full.
1325 */
1326 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1327 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1328 {
1329 /* Make sure the endpoint has been added to xHC schedule */
1330 xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1331 switch (ep_state) {
1332 case EP_STATE_DISABLED:
1333 /*
1334 * USB core changed config/interfaces without notifying us,
1335 * or hardware is reporting the wrong state.
1336 */
1337 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1338 return -ENOENT;
1339 case EP_STATE_ERROR:
1340 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
1341 /* FIXME event handling code for error needs to clear it */
1342 /* XXX not sure if this should be -ENOENT or not */
1343 return -EINVAL;
1344 case EP_STATE_HALTED:
1345 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
1346 case EP_STATE_STOPPED:
1347 case EP_STATE_RUNNING:
1348 break;
1349 default:
1350 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1351 /*
1352 * FIXME issue Configure Endpoint command to try to get the HC
1353 * back into a known state.
1354 */
1355 return -EINVAL;
1356 }
1357 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1358 /* FIXME allocate more room */
1359 xhci_err(xhci, "ERROR no room on ep ring\n");
1360 return -ENOMEM;
1361 }
1362 return 0;
1363 }
1364
1365 static int prepare_transfer(struct xhci_hcd *xhci,
1366 struct xhci_virt_device *xdev,
1367 unsigned int ep_index,
1368 unsigned int num_trbs,
1369 struct urb *urb,
1370 struct xhci_td **td,
1371 gfp_t mem_flags)
1372 {
1373 int ret;
1374 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1375 ret = prepare_ring(xhci, xdev->ep_rings[ep_index],
1376 ep_ctx->ep_info & EP_STATE_MASK,
1377 num_trbs, mem_flags);
1378 if (ret)
1379 return ret;
1380 *td = kzalloc(sizeof(struct xhci_td), mem_flags);
1381 if (!*td)
1382 return -ENOMEM;
1383 INIT_LIST_HEAD(&(*td)->td_list);
1384 INIT_LIST_HEAD(&(*td)->cancelled_td_list);
1385
1386 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
1387 if (unlikely(ret)) {
1388 kfree(*td);
1389 return ret;
1390 }
1391
1392 (*td)->urb = urb;
1393 urb->hcpriv = (void *) (*td);
1394 /* Add this TD to the tail of the endpoint ring's TD list */
1395 list_add_tail(&(*td)->td_list, &xdev->ep_rings[ep_index]->td_list);
1396 (*td)->start_seg = xdev->ep_rings[ep_index]->enq_seg;
1397 (*td)->first_trb = xdev->ep_rings[ep_index]->enqueue;
1398
1399 return 0;
1400 }
1401
1402 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
1403 {
1404 int num_sgs, num_trbs, running_total, temp, i;
1405 struct scatterlist *sg;
1406
1407 sg = NULL;
1408 num_sgs = urb->num_sgs;
1409 temp = urb->transfer_buffer_length;
1410
1411 xhci_dbg(xhci, "count sg list trbs: \n");
1412 num_trbs = 0;
1413 for_each_sg(urb->sg->sg, sg, num_sgs, i) {
1414 unsigned int previous_total_trbs = num_trbs;
1415 unsigned int len = sg_dma_len(sg);
1416
1417 /* Scatter gather list entries may cross 64KB boundaries */
1418 running_total = TRB_MAX_BUFF_SIZE -
1419 (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1420 if (running_total != 0)
1421 num_trbs++;
1422
1423 /* How many more 64KB chunks to transfer, how many more TRBs? */
1424 while (running_total < sg_dma_len(sg)) {
1425 num_trbs++;
1426 running_total += TRB_MAX_BUFF_SIZE;
1427 }
1428 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1429 i, (unsigned long long)sg_dma_address(sg),
1430 len, len, num_trbs - previous_total_trbs);
1431
1432 len = min_t(int, len, temp);
1433 temp -= len;
1434 if (temp == 0)
1435 break;
1436 }
1437 xhci_dbg(xhci, "\n");
1438 if (!in_interrupt())
1439 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1440 urb->ep->desc.bEndpointAddress,
1441 urb->transfer_buffer_length,
1442 num_trbs);
1443 return num_trbs;
1444 }
1445
1446 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
1447 {
1448 if (num_trbs != 0)
1449 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
1450 "TRBs, %d left\n", __func__,
1451 urb->ep->desc.bEndpointAddress, num_trbs);
1452 if (running_total != urb->transfer_buffer_length)
1453 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
1454 "queued %#x (%d), asked for %#x (%d)\n",
1455 __func__,
1456 urb->ep->desc.bEndpointAddress,
1457 running_total, running_total,
1458 urb->transfer_buffer_length,
1459 urb->transfer_buffer_length);
1460 }
1461
1462 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
1463 unsigned int ep_index, int start_cycle,
1464 struct xhci_generic_trb *start_trb, struct xhci_td *td)
1465 {
1466 /*
1467 * Pass all the TRBs to the hardware at once and make sure this write
1468 * isn't reordered.
1469 */
1470 wmb();
1471 start_trb->field[3] |= start_cycle;
1472 ring_ep_doorbell(xhci, slot_id, ep_index);
1473 }
1474
1475 /*
1476 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
1477 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
1478 * (comprised of sg list entries) can take several service intervals to
1479 * transmit.
1480 */
1481 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1482 struct urb *urb, int slot_id, unsigned int ep_index)
1483 {
1484 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
1485 xhci->devs[slot_id]->out_ctx, ep_index);
1486 int xhci_interval;
1487 int ep_interval;
1488
1489 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
1490 ep_interval = urb->interval;
1491 /* Convert to microframes */
1492 if (urb->dev->speed == USB_SPEED_LOW ||
1493 urb->dev->speed == USB_SPEED_FULL)
1494 ep_interval *= 8;
1495 /* FIXME change this to a warning and a suggestion to use the new API
1496 * to set the polling interval (once the API is added).
1497 */
1498 if (xhci_interval != ep_interval) {
1499 if (!printk_ratelimit())
1500 dev_dbg(&urb->dev->dev, "Driver uses different interval"
1501 " (%d microframe%s) than xHCI "
1502 "(%d microframe%s)\n",
1503 ep_interval,
1504 ep_interval == 1 ? "" : "s",
1505 xhci_interval,
1506 xhci_interval == 1 ? "" : "s");
1507 urb->interval = xhci_interval;
1508 /* Convert back to frames for LS/FS devices */
1509 if (urb->dev->speed == USB_SPEED_LOW ||
1510 urb->dev->speed == USB_SPEED_FULL)
1511 urb->interval /= 8;
1512 }
1513 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
1514 }
1515
1516 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1517 struct urb *urb, int slot_id, unsigned int ep_index)
1518 {
1519 struct xhci_ring *ep_ring;
1520 unsigned int num_trbs;
1521 struct xhci_td *td;
1522 struct scatterlist *sg;
1523 int num_sgs;
1524 int trb_buff_len, this_sg_len, running_total;
1525 bool first_trb;
1526 u64 addr;
1527
1528 struct xhci_generic_trb *start_trb;
1529 int start_cycle;
1530
1531 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1532 num_trbs = count_sg_trbs_needed(xhci, urb);
1533 num_sgs = urb->num_sgs;
1534
1535 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
1536 ep_index, num_trbs, urb, &td, mem_flags);
1537 if (trb_buff_len < 0)
1538 return trb_buff_len;
1539 /*
1540 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1541 * until we've finished creating all the other TRBs. The ring's cycle
1542 * state may change as we enqueue the other TRBs, so save it too.
1543 */
1544 start_trb = &ep_ring->enqueue->generic;
1545 start_cycle = ep_ring->cycle_state;
1546
1547 running_total = 0;
1548 /*
1549 * How much data is in the first TRB?
1550 *
1551 * There are three forces at work for TRB buffer pointers and lengths:
1552 * 1. We don't want to walk off the end of this sg-list entry buffer.
1553 * 2. The transfer length that the driver requested may be smaller than
1554 * the amount of memory allocated for this scatter-gather list.
1555 * 3. TRBs buffers can't cross 64KB boundaries.
1556 */
1557 sg = urb->sg->sg;
1558 addr = (u64) sg_dma_address(sg);
1559 this_sg_len = sg_dma_len(sg);
1560 trb_buff_len = TRB_MAX_BUFF_SIZE -
1561 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1562 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1563 if (trb_buff_len > urb->transfer_buffer_length)
1564 trb_buff_len = urb->transfer_buffer_length;
1565 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
1566 trb_buff_len);
1567
1568 first_trb = true;
1569 /* Queue the first TRB, even if it's zero-length */
1570 do {
1571 u32 field = 0;
1572 u32 length_field = 0;
1573
1574 /* Don't change the cycle bit of the first TRB until later */
1575 if (first_trb)
1576 first_trb = false;
1577 else
1578 field |= ep_ring->cycle_state;
1579
1580 /* Chain all the TRBs together; clear the chain bit in the last
1581 * TRB to indicate it's the last TRB in the chain.
1582 */
1583 if (num_trbs > 1) {
1584 field |= TRB_CHAIN;
1585 } else {
1586 /* FIXME - add check for ZERO_PACKET flag before this */
1587 td->last_trb = ep_ring->enqueue;
1588 field |= TRB_IOC;
1589 }
1590 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
1591 "64KB boundary at %#x, end dma = %#x\n",
1592 (unsigned int) addr, trb_buff_len, trb_buff_len,
1593 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1594 (unsigned int) addr + trb_buff_len);
1595 if (TRB_MAX_BUFF_SIZE -
1596 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
1597 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1598 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
1599 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1600 (unsigned int) addr + trb_buff_len);
1601 }
1602 length_field = TRB_LEN(trb_buff_len) |
1603 TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1604 TRB_INTR_TARGET(0);
1605 queue_trb(xhci, ep_ring, false,
1606 lower_32_bits(addr),
1607 upper_32_bits(addr),
1608 length_field,
1609 /* We always want to know if the TRB was short,
1610 * or we won't get an event when it completes.
1611 * (Unless we use event data TRBs, which are a
1612 * waste of space and HC resources.)
1613 */
1614 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1615 --num_trbs;
1616 running_total += trb_buff_len;
1617
1618 /* Calculate length for next transfer --
1619 * Are we done queueing all the TRBs for this sg entry?
1620 */
1621 this_sg_len -= trb_buff_len;
1622 if (this_sg_len == 0) {
1623 --num_sgs;
1624 if (num_sgs == 0)
1625 break;
1626 sg = sg_next(sg);
1627 addr = (u64) sg_dma_address(sg);
1628 this_sg_len = sg_dma_len(sg);
1629 } else {
1630 addr += trb_buff_len;
1631 }
1632
1633 trb_buff_len = TRB_MAX_BUFF_SIZE -
1634 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1635 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1636 if (running_total + trb_buff_len > urb->transfer_buffer_length)
1637 trb_buff_len =
1638 urb->transfer_buffer_length - running_total;
1639 } while (running_total < urb->transfer_buffer_length);
1640
1641 check_trb_math(urb, num_trbs, running_total);
1642 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1643 return 0;
1644 }
1645
1646 /* This is very similar to what ehci-q.c qtd_fill() does */
1647 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1648 struct urb *urb, int slot_id, unsigned int ep_index)
1649 {
1650 struct xhci_ring *ep_ring;
1651 struct xhci_td *td;
1652 int num_trbs;
1653 struct xhci_generic_trb *start_trb;
1654 bool first_trb;
1655 int start_cycle;
1656 u32 field, length_field;
1657
1658 int running_total, trb_buff_len, ret;
1659 u64 addr;
1660
1661 if (urb->sg)
1662 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
1663
1664 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1665
1666 num_trbs = 0;
1667 /* How much data is (potentially) left before the 64KB boundary? */
1668 running_total = TRB_MAX_BUFF_SIZE -
1669 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1670
1671 /* If there's some data on this 64KB chunk, or we have to send a
1672 * zero-length transfer, we need at least one TRB
1673 */
1674 if (running_total != 0 || urb->transfer_buffer_length == 0)
1675 num_trbs++;
1676 /* How many more 64KB chunks to transfer, how many more TRBs? */
1677 while (running_total < urb->transfer_buffer_length) {
1678 num_trbs++;
1679 running_total += TRB_MAX_BUFF_SIZE;
1680 }
1681 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1682
1683 if (!in_interrupt())
1684 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1685 urb->ep->desc.bEndpointAddress,
1686 urb->transfer_buffer_length,
1687 urb->transfer_buffer_length,
1688 (unsigned long long)urb->transfer_dma,
1689 num_trbs);
1690
1691 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
1692 num_trbs, urb, &td, mem_flags);
1693 if (ret < 0)
1694 return ret;
1695
1696 /*
1697 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1698 * until we've finished creating all the other TRBs. The ring's cycle
1699 * state may change as we enqueue the other TRBs, so save it too.
1700 */
1701 start_trb = &ep_ring->enqueue->generic;
1702 start_cycle = ep_ring->cycle_state;
1703
1704 running_total = 0;
1705 /* How much data is in the first TRB? */
1706 addr = (u64) urb->transfer_dma;
1707 trb_buff_len = TRB_MAX_BUFF_SIZE -
1708 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1709 if (urb->transfer_buffer_length < trb_buff_len)
1710 trb_buff_len = urb->transfer_buffer_length;
1711
1712 first_trb = true;
1713
1714 /* Queue the first TRB, even if it's zero-length */
1715 do {
1716 field = 0;
1717
1718 /* Don't change the cycle bit of the first TRB until later */
1719 if (first_trb)
1720 first_trb = false;
1721 else
1722 field |= ep_ring->cycle_state;
1723
1724 /* Chain all the TRBs together; clear the chain bit in the last
1725 * TRB to indicate it's the last TRB in the chain.
1726 */
1727 if (num_trbs > 1) {
1728 field |= TRB_CHAIN;
1729 } else {
1730 /* FIXME - add check for ZERO_PACKET flag before this */
1731 td->last_trb = ep_ring->enqueue;
1732 field |= TRB_IOC;
1733 }
1734 length_field = TRB_LEN(trb_buff_len) |
1735 TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1736 TRB_INTR_TARGET(0);
1737 queue_trb(xhci, ep_ring, false,
1738 lower_32_bits(addr),
1739 upper_32_bits(addr),
1740 length_field,
1741 /* We always want to know if the TRB was short,
1742 * or we won't get an event when it completes.
1743 * (Unless we use event data TRBs, which are a
1744 * waste of space and HC resources.)
1745 */
1746 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1747 --num_trbs;
1748 running_total += trb_buff_len;
1749
1750 /* Calculate length for next transfer */
1751 addr += trb_buff_len;
1752 trb_buff_len = urb->transfer_buffer_length - running_total;
1753 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
1754 trb_buff_len = TRB_MAX_BUFF_SIZE;
1755 } while (running_total < urb->transfer_buffer_length);
1756
1757 check_trb_math(urb, num_trbs, running_total);
1758 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1759 return 0;
1760 }
1761
1762 /* Caller must have locked xhci->lock */
1763 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1764 struct urb *urb, int slot_id, unsigned int ep_index)
1765 {
1766 struct xhci_ring *ep_ring;
1767 int num_trbs;
1768 int ret;
1769 struct usb_ctrlrequest *setup;
1770 struct xhci_generic_trb *start_trb;
1771 int start_cycle;
1772 u32 field, length_field;
1773 struct xhci_td *td;
1774
1775 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1776
1777 /*
1778 * Need to copy setup packet into setup TRB, so we can't use the setup
1779 * DMA address.
1780 */
1781 if (!urb->setup_packet)
1782 return -EINVAL;
1783
1784 if (!in_interrupt())
1785 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
1786 slot_id, ep_index);
1787 /* 1 TRB for setup, 1 for status */
1788 num_trbs = 2;
1789 /*
1790 * Don't need to check if we need additional event data and normal TRBs,
1791 * since data in control transfers will never get bigger than 16MB
1792 * XXX: can we get a buffer that crosses 64KB boundaries?
1793 */
1794 if (urb->transfer_buffer_length > 0)
1795 num_trbs++;
1796 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs,
1797 urb, &td, mem_flags);
1798 if (ret < 0)
1799 return ret;
1800
1801 /*
1802 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1803 * until we've finished creating all the other TRBs. The ring's cycle
1804 * state may change as we enqueue the other TRBs, so save it too.
1805 */
1806 start_trb = &ep_ring->enqueue->generic;
1807 start_cycle = ep_ring->cycle_state;
1808
1809 /* Queue setup TRB - see section 6.4.1.2.1 */
1810 /* FIXME better way to translate setup_packet into two u32 fields? */
1811 setup = (struct usb_ctrlrequest *) urb->setup_packet;
1812 queue_trb(xhci, ep_ring, false,
1813 /* FIXME endianness is probably going to bite my ass here. */
1814 setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
1815 setup->wIndex | setup->wLength << 16,
1816 TRB_LEN(8) | TRB_INTR_TARGET(0),
1817 /* Immediate data in pointer */
1818 TRB_IDT | TRB_TYPE(TRB_SETUP));
1819
1820 /* If there's data, queue data TRBs */
1821 field = 0;
1822 length_field = TRB_LEN(urb->transfer_buffer_length) |
1823 TD_REMAINDER(urb->transfer_buffer_length) |
1824 TRB_INTR_TARGET(0);
1825 if (urb->transfer_buffer_length > 0) {
1826 if (setup->bRequestType & USB_DIR_IN)
1827 field |= TRB_DIR_IN;
1828 queue_trb(xhci, ep_ring, false,
1829 lower_32_bits(urb->transfer_dma),
1830 upper_32_bits(urb->transfer_dma),
1831 length_field,
1832 /* Event on short tx */
1833 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
1834 }
1835
1836 /* Save the DMA address of the last TRB in the TD */
1837 td->last_trb = ep_ring->enqueue;
1838
1839 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1840 /* If the device sent data, the status stage is an OUT transfer */
1841 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
1842 field = 0;
1843 else
1844 field = TRB_DIR_IN;
1845 queue_trb(xhci, ep_ring, false,
1846 0,
1847 0,
1848 TRB_INTR_TARGET(0),
1849 /* Event on completion */
1850 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
1851
1852 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1853 return 0;
1854 }
1855
1856 /**** Command Ring Operations ****/
1857
1858 /* Generic function for queueing a command TRB on the command ring */
1859 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, u32 field3, u32 field4)
1860 {
1861 if (!room_on_ring(xhci, xhci->cmd_ring, 1)) {
1862 if (!in_interrupt())
1863 xhci_err(xhci, "ERR: No room for command on command ring\n");
1864 return -ENOMEM;
1865 }
1866 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
1867 field4 | xhci->cmd_ring->cycle_state);
1868 return 0;
1869 }
1870
1871 /* Queue a no-op command on the command ring */
1872 static int queue_cmd_noop(struct xhci_hcd *xhci)
1873 {
1874 return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP));
1875 }
1876
1877 /*
1878 * Place a no-op command on the command ring to test the command and
1879 * event ring.
1880 */
1881 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
1882 {
1883 if (queue_cmd_noop(xhci) < 0)
1884 return NULL;
1885 xhci->noops_submitted++;
1886 return xhci_ring_cmd_db;
1887 }
1888
1889 /* Queue a slot enable or disable request on the command ring */
1890 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
1891 {
1892 return queue_command(xhci, 0, 0, 0,
1893 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id));
1894 }
1895
1896 /* Queue an address device command TRB */
1897 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1898 u32 slot_id)
1899 {
1900 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1901 upper_32_bits(in_ctx_ptr), 0,
1902 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id));
1903 }
1904
1905 /* Queue a configure endpoint command TRB */
1906 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1907 u32 slot_id)
1908 {
1909 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1910 upper_32_bits(in_ctx_ptr), 0,
1911 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id));
1912 }
1913
1914 /* Queue an evaluate context command TRB */
1915 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1916 u32 slot_id)
1917 {
1918 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1919 upper_32_bits(in_ctx_ptr), 0,
1920 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id));
1921 }
1922
1923 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1924 unsigned int ep_index)
1925 {
1926 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1927 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1928 u32 type = TRB_TYPE(TRB_STOP_RING);
1929
1930 return queue_command(xhci, 0, 0, 0,
1931 trb_slot_id | trb_ep_index | type);
1932 }
1933
1934 /* Set Transfer Ring Dequeue Pointer command.
1935 * This should not be used for endpoints that have streams enabled.
1936 */
1937 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
1938 unsigned int ep_index, struct xhci_segment *deq_seg,
1939 union xhci_trb *deq_ptr, u32 cycle_state)
1940 {
1941 dma_addr_t addr;
1942 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1943 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1944 u32 type = TRB_TYPE(TRB_SET_DEQ);
1945
1946 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
1947 if (addr == 0) {
1948 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
1949 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
1950 deq_seg, deq_ptr);
1951 return 0;
1952 }
1953 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
1954 upper_32_bits(addr), 0,
1955 trb_slot_id | trb_ep_index | type);
1956 }
1957
1958 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1959 unsigned int ep_index)
1960 {
1961 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1962 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1963 u32 type = TRB_TYPE(TRB_RESET_EP);
1964
1965 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type);
1966 }
1967
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