1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ohci fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
11 *
12 *
13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14 * interfaces (though some non-x86 Intel chips use it). It supports
15 * smarter hardware than UHCI. A download link for the spec available
16 * through the http://www.usb.org website.
17 *
18 * This file is licenced under the GPL.
19 */
20
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dmapool.h>
37 #include <linux/reboot.h>
38 #include <linux/workqueue.h>
39 #include <linux/debugfs.h>
40
41 #include <asm/io.h>
42 #include <asm/irq.h>
43 #include <asm/system.h>
44 #include <asm/unaligned.h>
45 #include <asm/byteorder.h>
46
47 #include "../core/hcd.h"
48
49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
51
52 /*-------------------------------------------------------------------------*/
53
54 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
55
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58 #define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
61
62 #ifdef __hppa__
63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
64 #define IR_DISABLE
65 #endif
66
67 #ifdef CONFIG_ARCH_OMAP
68 /* OMAP doesn't support IR (no SMM; not needed) */
69 #define IR_DISABLE
70 #endif
71
72 /*-------------------------------------------------------------------------*/
73
74 static const char hcd_name [] = "ohci_hcd";
75
76 #define STATECHANGE_DELAY msecs_to_jiffies(300)
77
78 #include "ohci.h"
79
80 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
81 static int ohci_init (struct ohci_hcd *ohci);
82 static void ohci_stop (struct usb_hcd *hcd);
83
84 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
85 static int ohci_restart (struct ohci_hcd *ohci);
86 #endif
87
88 #ifdef CONFIG_PCI
89 static void quirk_amd_pll(int state);
90 static void amd_iso_dev_put(void);
91 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
92 #else
93 static inline void quirk_amd_pll(int state)
94 {
95 return;
96 }
97 static inline void amd_iso_dev_put(void)
98 {
99 return;
100 }
101 static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
102 {
103 return;
104 }
105 #endif
106
107
108 #include "ohci-hub.c"
109 #include "ohci-dbg.c"
110 #include "ohci-mem.c"
111 #include "ohci-q.c"
112
113
114 /*
115 * On architectures with edge-triggered interrupts we must never return
116 * IRQ_NONE.
117 */
118 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
119 #define IRQ_NOTMINE IRQ_HANDLED
120 #else
121 #define IRQ_NOTMINE IRQ_NONE
122 #endif
123
124
125 /* Some boards misreport power switching/overcurrent */
126 static int distrust_firmware = 1;
127 module_param (distrust_firmware, bool, 0);
128 MODULE_PARM_DESC (distrust_firmware,
129 "true to distrust firmware power/overcurrent setup");
130
131 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
132 static int no_handshake = 0;
133 module_param (no_handshake, bool, 0);
134 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
135
136 /*-------------------------------------------------------------------------*/
137
138 /*
139 * queue up an urb for anything except the root hub
140 */
141 static int ohci_urb_enqueue (
142 struct usb_hcd *hcd,
143 struct urb *urb,
144 gfp_t mem_flags
145 ) {
146 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
147 struct ed *ed;
148 urb_priv_t *urb_priv;
149 unsigned int pipe = urb->pipe;
150 int i, size = 0;
151 unsigned long flags;
152 int retval = 0;
153
154 #ifdef OHCI_VERBOSE_DEBUG
155 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
156 #endif
157
158 /* every endpoint has a ed, locate and maybe (re)initialize it */
159 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
160 return -ENOMEM;
161
162 /* for the private part of the URB we need the number of TDs (size) */
163 switch (ed->type) {
164 case PIPE_CONTROL:
165 /* td_submit_urb() doesn't yet handle these */
166 if (urb->transfer_buffer_length > 4096)
167 return -EMSGSIZE;
168
169 /* 1 TD for setup, 1 for ACK, plus ... */
170 size = 2;
171 /* FALLTHROUGH */
172 // case PIPE_INTERRUPT:
173 // case PIPE_BULK:
174 default:
175 /* one TD for every 4096 Bytes (can be upto 8K) */
176 size += urb->transfer_buffer_length / 4096;
177 /* ... and for any remaining bytes ... */
178 if ((urb->transfer_buffer_length % 4096) != 0)
179 size++;
180 /* ... and maybe a zero length packet to wrap it up */
181 if (size == 0)
182 size++;
183 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
184 && (urb->transfer_buffer_length
185 % usb_maxpacket (urb->dev, pipe,
186 usb_pipeout (pipe))) == 0)
187 size++;
188 break;
189 case PIPE_ISOCHRONOUS: /* number of packets from URB */
190 size = urb->number_of_packets;
191 break;
192 }
193
194 /* allocate the private part of the URB */
195 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
196 mem_flags);
197 if (!urb_priv)
198 return -ENOMEM;
199 INIT_LIST_HEAD (&urb_priv->pending);
200 urb_priv->length = size;
201 urb_priv->ed = ed;
202
203 /* allocate the TDs (deferring hash chain updates) */
204 for (i = 0; i < size; i++) {
205 urb_priv->td [i] = td_alloc (ohci, mem_flags);
206 if (!urb_priv->td [i]) {
207 urb_priv->length = i;
208 urb_free_priv (ohci, urb_priv);
209 return -ENOMEM;
210 }
211 }
212
213 spin_lock_irqsave (&ohci->lock, flags);
214
215 /* don't submit to a dead HC */
216 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
217 retval = -ENODEV;
218 goto fail;
219 }
220 if (!HC_IS_RUNNING(hcd->state)) {
221 retval = -ENODEV;
222 goto fail;
223 }
224 retval = usb_hcd_link_urb_to_ep(hcd, urb);
225 if (retval)
226 goto fail;
227
228 /* schedule the ed if needed */
229 if (ed->state == ED_IDLE) {
230 retval = ed_schedule (ohci, ed);
231 if (retval < 0) {
232 usb_hcd_unlink_urb_from_ep(hcd, urb);
233 goto fail;
234 }
235 if (ed->type == PIPE_ISOCHRONOUS) {
236 u16 frame = ohci_frame_no(ohci);
237
238 /* delay a few frames before the first TD */
239 frame += max_t (u16, 8, ed->interval);
240 frame &= ~(ed->interval - 1);
241 frame |= ed->branch;
242 urb->start_frame = frame;
243
244 /* yes, only URB_ISO_ASAP is supported, and
245 * urb->start_frame is never used as input.
246 */
247 }
248 } else if (ed->type == PIPE_ISOCHRONOUS)
249 urb->start_frame = ed->last_iso + ed->interval;
250
251 /* fill the TDs and link them to the ed; and
252 * enable that part of the schedule, if needed
253 * and update count of queued periodic urbs
254 */
255 urb->hcpriv = urb_priv;
256 td_submit_urb (ohci, urb);
257
258 fail:
259 if (retval)
260 urb_free_priv (ohci, urb_priv);
261 spin_unlock_irqrestore (&ohci->lock, flags);
262 return retval;
263 }
264
265 /*
266 * decouple the URB from the HC queues (TDs, urb_priv).
267 * reporting is always done
268 * asynchronously, and we might be dealing with an urb that's
269 * partially transferred, or an ED with other urbs being unlinked.
270 */
271 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
272 {
273 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
274 unsigned long flags;
275 int rc;
276
277 #ifdef OHCI_VERBOSE_DEBUG
278 urb_print(urb, "UNLINK", 1, status);
279 #endif
280
281 spin_lock_irqsave (&ohci->lock, flags);
282 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
283 if (rc) {
284 ; /* Do nothing */
285 } else if (HC_IS_RUNNING(hcd->state)) {
286 urb_priv_t *urb_priv;
287
288 /* Unless an IRQ completed the unlink while it was being
289 * handed to us, flag it for unlink and giveback, and force
290 * some upcoming INTR_SF to call finish_unlinks()
291 */
292 urb_priv = urb->hcpriv;
293 if (urb_priv) {
294 if (urb_priv->ed->state == ED_OPER)
295 start_ed_unlink (ohci, urb_priv->ed);
296 }
297 } else {
298 /*
299 * with HC dead, we won't respect hc queue pointers
300 * any more ... just clean up every urb's memory.
301 */
302 if (urb->hcpriv)
303 finish_urb(ohci, urb, status);
304 }
305 spin_unlock_irqrestore (&ohci->lock, flags);
306 return rc;
307 }
308
309 /*-------------------------------------------------------------------------*/
310
311 /* frees config/altsetting state for endpoints,
312 * including ED memory, dummy TD, and bulk/intr data toggle
313 */
314
315 static void
316 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
317 {
318 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
319 unsigned long flags;
320 struct ed *ed = ep->hcpriv;
321 unsigned limit = 1000;
322
323 /* ASSERT: any requests/urbs are being unlinked */
324 /* ASSERT: nobody can be submitting urbs for this any more */
325
326 if (!ed)
327 return;
328
329 rescan:
330 spin_lock_irqsave (&ohci->lock, flags);
331
332 if (!HC_IS_RUNNING (hcd->state)) {
333 sanitize:
334 ed->state = ED_IDLE;
335 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
336 ohci->eds_scheduled--;
337 finish_unlinks (ohci, 0);
338 }
339
340 switch (ed->state) {
341 case ED_UNLINK: /* wait for hw to finish? */
342 /* major IRQ delivery trouble loses INTR_SF too... */
343 if (limit-- == 0) {
344 ohci_warn(ohci, "ED unlink timeout\n");
345 if (quirk_zfmicro(ohci)) {
346 ohci_warn(ohci, "Attempting ZF TD recovery\n");
347 ohci->ed_to_check = ed;
348 ohci->zf_delay = 2;
349 }
350 goto sanitize;
351 }
352 spin_unlock_irqrestore (&ohci->lock, flags);
353 schedule_timeout_uninterruptible(1);
354 goto rescan;
355 case ED_IDLE: /* fully unlinked */
356 if (list_empty (&ed->td_list)) {
357 td_free (ohci, ed->dummy);
358 ed_free (ohci, ed);
359 break;
360 }
361 /* else FALL THROUGH */
362 default:
363 /* caller was supposed to have unlinked any requests;
364 * that's not our job. can't recover; must leak ed.
365 */
366 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
367 ed, ep->desc.bEndpointAddress, ed->state,
368 list_empty (&ed->td_list) ? "" : " (has tds)");
369 td_free (ohci, ed->dummy);
370 break;
371 }
372 ep->hcpriv = NULL;
373 spin_unlock_irqrestore (&ohci->lock, flags);
374 return;
375 }
376
377 static int ohci_get_frame (struct usb_hcd *hcd)
378 {
379 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
380
381 return ohci_frame_no(ohci);
382 }
383
384 static void ohci_usb_reset (struct ohci_hcd *ohci)
385 {
386 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
387 ohci->hc_control &= OHCI_CTRL_RWC;
388 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
389 }
390
391 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
392 * other cases where the next software may expect clean state from the
393 * "firmware". this is bus-neutral, unlike shutdown() methods.
394 */
395 static void
396 ohci_shutdown (struct usb_hcd *hcd)
397 {
398 struct ohci_hcd *ohci;
399
400 ohci = hcd_to_ohci (hcd);
401 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
402 ohci_usb_reset (ohci);
403 /* flush the writes */
404 (void) ohci_readl (ohci, &ohci->regs->control);
405 }
406
407 static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
408 {
409 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
410 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
411 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
412 && !list_empty(&ed->td_list);
413 }
414
415 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
416 * an interrupt TD but neglects to add it to the donelist. On systems with
417 * this chipset, we need to periodically check the state of the queues to look
418 * for such "lost" TDs.
419 */
420 static void unlink_watchdog_func(unsigned long _ohci)
421 {
422 unsigned long flags;
423 unsigned max;
424 unsigned seen_count = 0;
425 unsigned i;
426 struct ed **seen = NULL;
427 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
428
429 spin_lock_irqsave(&ohci->lock, flags);
430 max = ohci->eds_scheduled;
431 if (!max)
432 goto done;
433
434 if (ohci->ed_to_check)
435 goto out;
436
437 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
438 if (!seen)
439 goto out;
440
441 for (i = 0; i < NUM_INTS; i++) {
442 struct ed *ed = ohci->periodic[i];
443
444 while (ed) {
445 unsigned temp;
446
447 /* scan this branch of the periodic schedule tree */
448 for (temp = 0; temp < seen_count; temp++) {
449 if (seen[temp] == ed) {
450 /* we've checked it and what's after */
451 ed = NULL;
452 break;
453 }
454 }
455 if (!ed)
456 break;
457 seen[seen_count++] = ed;
458 if (!check_ed(ohci, ed)) {
459 ed = ed->ed_next;
460 continue;
461 }
462
463 /* HC's TD list is empty, but HCD sees at least one
464 * TD that's not been sent through the donelist.
465 */
466 ohci->ed_to_check = ed;
467 ohci->zf_delay = 2;
468
469 /* The HC may wait until the next frame to report the
470 * TD as done through the donelist and INTR_WDH. (We
471 * just *assume* it's not a multi-TD interrupt URB;
472 * those could defer the IRQ more than one frame, using
473 * DI...) Check again after the next INTR_SF.
474 */
475 ohci_writel(ohci, OHCI_INTR_SF,
476 &ohci->regs->intrstatus);
477 ohci_writel(ohci, OHCI_INTR_SF,
478 &ohci->regs->intrenable);
479
480 /* flush those writes */
481 (void) ohci_readl(ohci, &ohci->regs->control);
482
483 goto out;
484 }
485 }
486 out:
487 kfree(seen);
488 if (ohci->eds_scheduled)
489 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
490 done:
491 spin_unlock_irqrestore(&ohci->lock, flags);
492 }
493
494 /*-------------------------------------------------------------------------*
495 * HC functions
496 *-------------------------------------------------------------------------*/
497
498 /* init memory, and kick BIOS/SMM off */
499
500 static int ohci_init (struct ohci_hcd *ohci)
501 {
502 int ret;
503 struct usb_hcd *hcd = ohci_to_hcd(ohci);
504
505 if (distrust_firmware)
506 ohci->flags |= OHCI_QUIRK_HUB_POWER;
507
508 disable (ohci);
509 ohci->regs = hcd->regs;
510
511 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
512 * was never needed for most non-PCI systems ... remove the code?
513 */
514
515 #ifndef IR_DISABLE
516 /* SMM owns the HC? not for long! */
517 if (!no_handshake && ohci_readl (ohci,
518 &ohci->regs->control) & OHCI_CTRL_IR) {
519 u32 temp;
520
521 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
522
523 /* this timeout is arbitrary. we make it long, so systems
524 * depending on usb keyboards may be usable even if the
525 * BIOS/SMM code seems pretty broken.
526 */
527 temp = 500; /* arbitrary: five seconds */
528
529 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
530 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
531 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
532 msleep (10);
533 if (--temp == 0) {
534 ohci_err (ohci, "USB HC takeover failed!"
535 " (BIOS/SMM bug)\n");
536 return -EBUSY;
537 }
538 }
539 ohci_usb_reset (ohci);
540 }
541 #endif
542
543 /* Disable HC interrupts */
544 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
545
546 /* flush the writes, and save key bits like RWC */
547 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
548 ohci->hc_control |= OHCI_CTRL_RWC;
549
550 /* Read the number of ports unless overridden */
551 if (ohci->num_ports == 0)
552 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
553
554 if (ohci->hcca)
555 return 0;
556
557 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
558 sizeof *ohci->hcca, &ohci->hcca_dma, 0);
559 if (!ohci->hcca)
560 return -ENOMEM;
561
562 if ((ret = ohci_mem_init (ohci)) < 0)
563 ohci_stop (hcd);
564 else {
565 create_debug_files (ohci);
566 }
567
568 return ret;
569 }
570
571 /*-------------------------------------------------------------------------*/
572
573 /* Start an OHCI controller, set the BUS operational
574 * resets USB and controller
575 * enable interrupts
576 */
577 static int ohci_run (struct ohci_hcd *ohci)
578 {
579 u32 mask, val;
580 int first = ohci->fminterval == 0;
581 struct usb_hcd *hcd = ohci_to_hcd(ohci);
582
583 disable (ohci);
584
585 /* boot firmware should have set this up (5.1.1.3.1) */
586 if (first) {
587
588 val = ohci_readl (ohci, &ohci->regs->fminterval);
589 ohci->fminterval = val & 0x3fff;
590 if (ohci->fminterval != FI)
591 ohci_dbg (ohci, "fminterval delta %d\n",
592 ohci->fminterval - FI);
593 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
594 /* also: power/overcurrent flags in roothub.a */
595 }
596
597 /* Reset USB nearly "by the book". RemoteWakeupConnected has
598 * to be checked in case boot firmware (BIOS/SMM/...) has set up
599 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
600 * If the bus glue detected wakeup capability then it should
601 * already be enabled; if so we'll just enable it again.
602 */
603 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
604 device_set_wakeup_capable(hcd->self.controller, 1);
605
606 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
607 case OHCI_USB_OPER:
608 val = 0;
609 break;
610 case OHCI_USB_SUSPEND:
611 case OHCI_USB_RESUME:
612 ohci->hc_control &= OHCI_CTRL_RWC;
613 ohci->hc_control |= OHCI_USB_RESUME;
614 val = 10 /* msec wait */;
615 break;
616 // case OHCI_USB_RESET:
617 default:
618 ohci->hc_control &= OHCI_CTRL_RWC;
619 ohci->hc_control |= OHCI_USB_RESET;
620 val = 50 /* msec wait */;
621 break;
622 }
623 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
624 // flush the writes
625 (void) ohci_readl (ohci, &ohci->regs->control);
626 msleep(val);
627
628 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
629
630 /* 2msec timelimit here means no irqs/preempt */
631 spin_lock_irq (&ohci->lock);
632
633 retry:
634 /* HC Reset requires max 10 us delay */
635 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
636 val = 30; /* ... allow extra time */
637 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
638 if (--val == 0) {
639 spin_unlock_irq (&ohci->lock);
640 ohci_err (ohci, "USB HC reset timed out!\n");
641 return -1;
642 }
643 udelay (1);
644 }
645
646 /* now we're in the SUSPEND state ... must go OPERATIONAL
647 * within 2msec else HC enters RESUME
648 *
649 * ... but some hardware won't init fmInterval "by the book"
650 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
651 * this if we write fmInterval after we're OPERATIONAL.
652 * Unclear about ALi, ServerWorks, and others ... this could
653 * easily be a longstanding bug in chip init on Linux.
654 */
655 if (ohci->flags & OHCI_QUIRK_INITRESET) {
656 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
657 // flush those writes
658 (void) ohci_readl (ohci, &ohci->regs->control);
659 }
660
661 /* Tell the controller where the control and bulk lists are
662 * The lists are empty now. */
663 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
664 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
665
666 /* a reset clears this */
667 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
668
669 periodic_reinit (ohci);
670
671 /* some OHCI implementations are finicky about how they init.
672 * bogus values here mean not even enumeration could work.
673 */
674 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
675 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
676 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
677 ohci->flags |= OHCI_QUIRK_INITRESET;
678 ohci_dbg (ohci, "enabling initreset quirk\n");
679 goto retry;
680 }
681 spin_unlock_irq (&ohci->lock);
682 ohci_err (ohci, "init err (%08x %04x)\n",
683 ohci_readl (ohci, &ohci->regs->fminterval),
684 ohci_readl (ohci, &ohci->regs->periodicstart));
685 return -EOVERFLOW;
686 }
687
688 /* use rhsc irqs after khubd is fully initialized */
689 hcd->poll_rh = 1;
690 hcd->uses_new_polling = 1;
691
692 /* start controller operations */
693 ohci->hc_control &= OHCI_CTRL_RWC;
694 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
695 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
696 hcd->state = HC_STATE_RUNNING;
697
698 /* wake on ConnectStatusChange, matching external hubs */
699 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
700
701 /* Choose the interrupts we care about now, others later on demand */
702 mask = OHCI_INTR_INIT;
703 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
704 ohci_writel (ohci, mask, &ohci->regs->intrenable);
705
706 /* handle root hub init quirks ... */
707 val = roothub_a (ohci);
708 val &= ~(RH_A_PSM | RH_A_OCPM);
709 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
710 /* NSC 87560 and maybe others */
711 val |= RH_A_NOCP;
712 val &= ~(RH_A_POTPGT | RH_A_NPS);
713 ohci_writel (ohci, val, &ohci->regs->roothub.a);
714 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
715 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
716 /* hub power always on; required for AMD-756 and some
717 * Mac platforms. ganged overcurrent reporting, if any.
718 */
719 val |= RH_A_NPS;
720 ohci_writel (ohci, val, &ohci->regs->roothub.a);
721 }
722 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
723 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
724 &ohci->regs->roothub.b);
725 // flush those writes
726 (void) ohci_readl (ohci, &ohci->regs->control);
727
728 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
729 spin_unlock_irq (&ohci->lock);
730
731 // POTPGT delay is bits 24-31, in 2 ms units.
732 mdelay ((val >> 23) & 0x1fe);
733 hcd->state = HC_STATE_RUNNING;
734
735 if (quirk_zfmicro(ohci)) {
736 /* Create timer to watch for bad queue state on ZF Micro */
737 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
738 (unsigned long) ohci);
739
740 ohci->eds_scheduled = 0;
741 ohci->ed_to_check = NULL;
742 }
743
744 ohci_dump (ohci, 1);
745
746 return 0;
747 }
748
749 /*-------------------------------------------------------------------------*/
750
751 /* an interrupt happens */
752
753 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
754 {
755 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
756 struct ohci_regs __iomem *regs = ohci->regs;
757 int ints;
758
759 /* Read interrupt status (and flush pending writes). We ignore the
760 * optimization of checking the LSB of hcca->done_head; it doesn't
761 * work on all systems (edge triggering for OHCI can be a factor).
762 */
763 ints = ohci_readl(ohci, ®s->intrstatus);
764
765 /* Check for an all 1's result which is a typical consequence
766 * of dead, unclocked, or unplugged (CardBus...) devices
767 */
768 if (ints == ~(u32)0) {
769 disable (ohci);
770 ohci_dbg (ohci, "device removed!\n");
771 return IRQ_HANDLED;
772 }
773
774 /* We only care about interrupts that are enabled */
775 ints &= ohci_readl(ohci, ®s->intrenable);
776
777 /* interrupt for some other device? */
778 if (ints == 0)
779 return IRQ_NOTMINE;
780
781 if (ints & OHCI_INTR_UE) {
782 // e.g. due to PCI Master/Target Abort
783 if (quirk_nec(ohci)) {
784 /* Workaround for a silicon bug in some NEC chips used
785 * in Apple's PowerBooks. Adapted from Darwin code.
786 */
787 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
788
789 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
790
791 schedule_work (&ohci->nec_work);
792 } else {
793 disable (ohci);
794 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
795 }
796
797 ohci_dump (ohci, 1);
798 ohci_usb_reset (ohci);
799 }
800
801 if (ints & OHCI_INTR_RHSC) {
802 ohci_vdbg(ohci, "rhsc\n");
803 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
804 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
805 ®s->intrstatus);
806
807 /* NOTE: Vendors didn't always make the same implementation
808 * choices for RHSC. Many followed the spec; RHSC triggers
809 * on an edge, like setting and maybe clearing a port status
810 * change bit. With others it's level-triggered, active
811 * until khubd clears all the port status change bits. We'll
812 * always disable it here and rely on polling until khubd
813 * re-enables it.
814 */
815 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
816 usb_hcd_poll_rh_status(hcd);
817 }
818
819 /* For connect and disconnect events, we expect the controller
820 * to turn on RHSC along with RD. But for remote wakeup events
821 * this might not happen.
822 */
823 else if (ints & OHCI_INTR_RD) {
824 ohci_vdbg(ohci, "resume detect\n");
825 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
826 hcd->poll_rh = 1;
827 if (ohci->autostop) {
828 spin_lock (&ohci->lock);
829 ohci_rh_resume (ohci);
830 spin_unlock (&ohci->lock);
831 } else
832 usb_hcd_resume_root_hub(hcd);
833 }
834
835 if (ints & OHCI_INTR_WDH) {
836 spin_lock (&ohci->lock);
837 dl_done_list (ohci);
838 spin_unlock (&ohci->lock);
839 }
840
841 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
842 spin_lock(&ohci->lock);
843 if (ohci->ed_to_check) {
844 struct ed *ed = ohci->ed_to_check;
845
846 if (check_ed(ohci, ed)) {
847 /* HC thinks the TD list is empty; HCD knows
848 * at least one TD is outstanding
849 */
850 if (--ohci->zf_delay == 0) {
851 struct td *td = list_entry(
852 ed->td_list.next,
853 struct td, td_list);
854 ohci_warn(ohci,
855 "Reclaiming orphan TD %p\n",
856 td);
857 takeback_td(ohci, td);
858 ohci->ed_to_check = NULL;
859 }
860 } else
861 ohci->ed_to_check = NULL;
862 }
863 spin_unlock(&ohci->lock);
864 }
865
866 /* could track INTR_SO to reduce available PCI/... bandwidth */
867
868 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
869 * when there's still unlinking to be done (next frame).
870 */
871 spin_lock (&ohci->lock);
872 if (ohci->ed_rm_list)
873 finish_unlinks (ohci, ohci_frame_no(ohci));
874 if ((ints & OHCI_INTR_SF) != 0
875 && !ohci->ed_rm_list
876 && !ohci->ed_to_check
877 && HC_IS_RUNNING(hcd->state))
878 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
879 spin_unlock (&ohci->lock);
880
881 if (HC_IS_RUNNING(hcd->state)) {
882 ohci_writel (ohci, ints, ®s->intrstatus);
883 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
884 // flush those writes
885 (void) ohci_readl (ohci, &ohci->regs->control);
886 }
887
888 return IRQ_HANDLED;
889 }
890
891 /*-------------------------------------------------------------------------*/
892
893 static void ohci_stop (struct usb_hcd *hcd)
894 {
895 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
896
897 ohci_dump (ohci, 1);
898
899 flush_scheduled_work();
900
901 ohci_usb_reset (ohci);
902 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
903 free_irq(hcd->irq, hcd);
904 hcd->irq = -1;
905
906 if (quirk_zfmicro(ohci))
907 del_timer(&ohci->unlink_watchdog);
908 if (quirk_amdiso(ohci))
909 amd_iso_dev_put();
910
911 remove_debug_files (ohci);
912 ohci_mem_cleanup (ohci);
913 if (ohci->hcca) {
914 dma_free_coherent (hcd->self.controller,
915 sizeof *ohci->hcca,
916 ohci->hcca, ohci->hcca_dma);
917 ohci->hcca = NULL;
918 ohci->hcca_dma = 0;
919 }
920 }
921
922 /*-------------------------------------------------------------------------*/
923
924 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
925
926 /* must not be called from interrupt context */
927 static int ohci_restart (struct ohci_hcd *ohci)
928 {
929 int temp;
930 int i;
931 struct urb_priv *priv;
932
933 spin_lock_irq(&ohci->lock);
934 disable (ohci);
935
936 /* Recycle any "live" eds/tds (and urbs). */
937 if (!list_empty (&ohci->pending))
938 ohci_dbg(ohci, "abort schedule...\n");
939 list_for_each_entry (priv, &ohci->pending, pending) {
940 struct urb *urb = priv->td[0]->urb;
941 struct ed *ed = priv->ed;
942
943 switch (ed->state) {
944 case ED_OPER:
945 ed->state = ED_UNLINK;
946 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
947 ed_deschedule (ohci, ed);
948
949 ed->ed_next = ohci->ed_rm_list;
950 ed->ed_prev = NULL;
951 ohci->ed_rm_list = ed;
952 /* FALLTHROUGH */
953 case ED_UNLINK:
954 break;
955 default:
956 ohci_dbg(ohci, "bogus ed %p state %d\n",
957 ed, ed->state);
958 }
959
960 if (!urb->unlinked)
961 urb->unlinked = -ESHUTDOWN;
962 }
963 finish_unlinks (ohci, 0);
964 spin_unlock_irq(&ohci->lock);
965
966 /* paranoia, in case that didn't work: */
967
968 /* empty the interrupt branches */
969 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
970 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
971
972 /* no EDs to remove */
973 ohci->ed_rm_list = NULL;
974
975 /* empty control and bulk lists */
976 ohci->ed_controltail = NULL;
977 ohci->ed_bulktail = NULL;
978
979 if ((temp = ohci_run (ohci)) < 0) {
980 ohci_err (ohci, "can't restart, %d\n", temp);
981 return temp;
982 }
983 ohci_dbg(ohci, "restart complete\n");
984 return 0;
985 }
986
987 #endif
988
989 /*-------------------------------------------------------------------------*/
990
991 MODULE_AUTHOR (DRIVER_AUTHOR);
992 MODULE_DESCRIPTION(DRIVER_DESC);
993 MODULE_LICENSE ("GPL");
994
995 #ifdef CONFIG_PCI
996 #include "ohci-pci.c"
997 #define PCI_DRIVER ohci_pci_driver
998 #endif
999
1000 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1001 #include "ohci-sa1111.c"
1002 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1003 #endif
1004
1005 #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX)
1006 #include "ohci-s3c2410.c"
1007 #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1008 #endif
1009
1010 #ifdef CONFIG_ARCH_OMAP
1011 #include "ohci-omap.c"
1012 #define PLATFORM_DRIVER ohci_hcd_omap_driver
1013 #endif
1014
1015 #ifdef CONFIG_ARCH_LH7A404
1016 #include "ohci-lh7a404.c"
1017 #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver
1018 #endif
1019
1020 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1021 #include "ohci-pxa27x.c"
1022 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1023 #endif
1024
1025 #ifdef CONFIG_ARCH_EP93XX
1026 #include "ohci-ep93xx.c"
1027 #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1028 #endif
1029
1030 #ifdef CONFIG_SOC_AU1X00
1031 #include "ohci-au1xxx.c"
1032 #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver
1033 #endif
1034
1035 #ifdef CONFIG_PNX8550
1036 #include "ohci-pnx8550.c"
1037 #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver
1038 #endif
1039
1040 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
1041 #include "ohci-ppc-soc.c"
1042 #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver
1043 #endif
1044
1045 #ifdef CONFIG_ARCH_AT91
1046 #include "ohci-at91.c"
1047 #define PLATFORM_DRIVER ohci_hcd_at91_driver
1048 #endif
1049
1050 #ifdef CONFIG_ARCH_PNX4008
1051 #include "ohci-pnx4008.c"
1052 #define PLATFORM_DRIVER usb_hcd_pnx4008_driver
1053 #endif
1054
1055 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
1056 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
1057 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1058 defined(CONFIG_CPU_SUBTYPE_SH7786)
1059 #include "ohci-sh.c"
1060 #define PLATFORM_DRIVER ohci_hcd_sh_driver
1061 #endif
1062
1063
1064 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1065 #include "ohci-ppc-of.c"
1066 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1067 #endif
1068
1069 #ifdef CONFIG_PPC_PS3
1070 #include "ohci-ps3.c"
1071 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1072 #endif
1073
1074 #ifdef CONFIG_USB_OHCI_HCD_SSB
1075 #include "ohci-ssb.c"
1076 #define SSB_OHCI_DRIVER ssb_ohci_driver
1077 #endif
1078
1079 #ifdef CONFIG_MFD_SM501
1080 #include "ohci-sm501.c"
1081 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1082 #endif
1083
1084 #ifdef CONFIG_MFD_TC6393XB
1085 #include "ohci-tmio.c"
1086 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1087 #endif
1088
1089 #if !defined(PCI_DRIVER) && \
1090 !defined(PLATFORM_DRIVER) && \
1091 !defined(OF_PLATFORM_DRIVER) && \
1092 !defined(SA1111_DRIVER) && \
1093 !defined(PS3_SYSTEM_BUS_DRIVER) && \
1094 !defined(SM501_OHCI_DRIVER) && \
1095 !defined(TMIO_OHCI_DRIVER) && \
1096 !defined(SSB_OHCI_DRIVER)
1097 #error "missing bus glue for ohci-hcd"
1098 #endif
1099
1100 static int __init ohci_hcd_mod_init(void)
1101 {
1102 int retval = 0;
1103
1104 if (usb_disabled())
1105 return -ENODEV;
1106
1107 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1108 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1109 sizeof (struct ed), sizeof (struct td));
1110 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1111
1112 #ifdef DEBUG
1113 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1114 if (!ohci_debug_root) {
1115 retval = -ENOENT;
1116 goto error_debug;
1117 }
1118 #endif
1119
1120 #ifdef PS3_SYSTEM_BUS_DRIVER
1121 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1122 if (retval < 0)
1123 goto error_ps3;
1124 #endif
1125
1126 #ifdef PLATFORM_DRIVER
1127 retval = platform_driver_register(&PLATFORM_DRIVER);
1128 if (retval < 0)
1129 goto error_platform;
1130 #endif
1131
1132 #ifdef OF_PLATFORM_DRIVER
1133 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
1134 if (retval < 0)
1135 goto error_of_platform;
1136 #endif
1137
1138 #ifdef SA1111_DRIVER
1139 retval = sa1111_driver_register(&SA1111_DRIVER);
1140 if (retval < 0)
1141 goto error_sa1111;
1142 #endif
1143
1144 #ifdef PCI_DRIVER
1145 retval = pci_register_driver(&PCI_DRIVER);
1146 if (retval < 0)
1147 goto error_pci;
1148 #endif
1149
1150 #ifdef SSB_OHCI_DRIVER
1151 retval = ssb_driver_register(&SSB_OHCI_DRIVER);
1152 if (retval)
1153 goto error_ssb;
1154 #endif
1155
1156 #ifdef SM501_OHCI_DRIVER
1157 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1158 if (retval < 0)
1159 goto error_sm501;
1160 #endif
1161
1162 #ifdef TMIO_OHCI_DRIVER
1163 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1164 if (retval < 0)
1165 goto error_tmio;
1166 #endif
1167
1168 return retval;
1169
1170 /* Error path */
1171 #ifdef TMIO_OHCI_DRIVER
1172 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1173 error_tmio:
1174 #endif
1175 #ifdef SM501_OHCI_DRIVER
1176 platform_driver_unregister(&SM501_OHCI_DRIVER);
1177 error_sm501:
1178 #endif
1179 #ifdef SSB_OHCI_DRIVER
1180 ssb_driver_unregister(&SSB_OHCI_DRIVER);
1181 error_ssb:
1182 #endif
1183 #ifdef PCI_DRIVER
1184 pci_unregister_driver(&PCI_DRIVER);
1185 error_pci:
1186 #endif
1187 #ifdef SA1111_DRIVER
1188 sa1111_driver_unregister(&SA1111_DRIVER);
1189 error_sa1111:
1190 #endif
1191 #ifdef OF_PLATFORM_DRIVER
1192 of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1193 error_of_platform:
1194 #endif
1195 #ifdef PLATFORM_DRIVER
1196 platform_driver_unregister(&PLATFORM_DRIVER);
1197 error_platform:
1198 #endif
1199 #ifdef PS3_SYSTEM_BUS_DRIVER
1200 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1201 error_ps3:
1202 #endif
1203 #ifdef DEBUG
1204 debugfs_remove(ohci_debug_root);
1205 ohci_debug_root = NULL;
1206 error_debug:
1207 #endif
1208
1209 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1210 return retval;
1211 }
1212 module_init(ohci_hcd_mod_init);
1213
1214 static void __exit ohci_hcd_mod_exit(void)
1215 {
1216 #ifdef TMIO_OHCI_DRIVER
1217 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1218 #endif
1219 #ifdef SM501_OHCI_DRIVER
1220 platform_driver_unregister(&SM501_OHCI_DRIVER);
1221 #endif
1222 #ifdef SSB_OHCI_DRIVER
1223 ssb_driver_unregister(&SSB_OHCI_DRIVER);
1224 #endif
1225 #ifdef PCI_DRIVER
1226 pci_unregister_driver(&PCI_DRIVER);
1227 #endif
1228 #ifdef SA1111_DRIVER
1229 sa1111_driver_unregister(&SA1111_DRIVER);
1230 #endif
1231 #ifdef OF_PLATFORM_DRIVER
1232 of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1233 #endif
1234 #ifdef PLATFORM_DRIVER
1235 platform_driver_unregister(&PLATFORM_DRIVER);
1236 #endif
1237 #ifdef PS3_SYSTEM_BUS_DRIVER
1238 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1239 #endif
1240 #ifdef DEBUG
1241 debugfs_remove(ohci_debug_root);
1242 #endif
1243 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1244 }
1245 module_exit(ohci_hcd_mod_exit);
1246
1247
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