1 #ifndef _ISP1760_HCD_H_
2 #define _ISP1760_HCD_H_
3
4 /* exports for if */
5 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
6 int irq, unsigned long irqflags,
7 struct device *dev, const char *busname,
8 unsigned int devflags);
9 int init_kmem_once(void);
10 void deinit_kmem_cache(void);
11
12 /* EHCI capability registers */
13 #define HC_CAPLENGTH 0x00
14 #define HC_HCSPARAMS 0x04
15 #define HC_HCCPARAMS 0x08
16
17 /* EHCI operational registers */
18 #define HC_USBCMD 0x20
19 #define HC_USBSTS 0x24
20 #define HC_FRINDEX 0x2c
21 #define HC_CONFIGFLAG 0x60
22 #define HC_PORTSC1 0x64
23 #define HC_ISO_PTD_DONEMAP_REG 0x130
24 #define HC_ISO_PTD_SKIPMAP_REG 0x134
25 #define HC_ISO_PTD_LASTPTD_REG 0x138
26 #define HC_INT_PTD_DONEMAP_REG 0x140
27 #define HC_INT_PTD_SKIPMAP_REG 0x144
28 #define HC_INT_PTD_LASTPTD_REG 0x148
29 #define HC_ATL_PTD_DONEMAP_REG 0x150
30 #define HC_ATL_PTD_SKIPMAP_REG 0x154
31 #define HC_ATL_PTD_LASTPTD_REG 0x158
32
33 /* Configuration Register */
34 #define HC_HW_MODE_CTRL 0x300
35 #define ALL_ATX_RESET (1 << 31)
36 #define HW_ANA_DIGI_OC (1 << 15)
37 #define HW_DATA_BUS_32BIT (1 << 8)
38 #define HW_DACK_POL_HIGH (1 << 6)
39 #define HW_DREQ_POL_HIGH (1 << 5)
40 #define HW_INTR_HIGH_ACT (1 << 2)
41 #define HW_INTR_EDGE_TRIG (1 << 1)
42 #define HW_GLOBAL_INTR_EN (1 << 0)
43
44 #define HC_CHIP_ID_REG 0x304
45 #define HC_SCRATCH_REG 0x308
46
47 #define HC_RESET_REG 0x30c
48 #define SW_RESET_RESET_HC (1 << 1)
49 #define SW_RESET_RESET_ALL (1 << 0)
50
51 #define HC_BUFFER_STATUS_REG 0x334
52 #define ATL_BUFFER 0x1
53 #define INT_BUFFER 0x2
54 #define ISO_BUFFER 0x4
55 #define BUFFER_MAP 0x7
56
57 #define HC_MEMORY_REG 0x33c
58 #define ISP_BANK(x) ((x) << 16)
59
60 #define HC_PORT1_CTRL 0x374
61 #define PORT1_POWER (3 << 3)
62 #define PORT1_INIT1 (1 << 7)
63 #define PORT1_INIT2 (1 << 23)
64 #define HW_OTG_CTRL_SET 0x374
65 #define HW_OTG_CTRL_CLR 0x376
66
67 /* Interrupt Register */
68 #define HC_INTERRUPT_REG 0x310
69
70 #define HC_INTERRUPT_ENABLE 0x314
71 #define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT | HC_EOT_INT)
72
73 #define HC_ISO_INT (1 << 9)
74 #define HC_ATL_INT (1 << 8)
75 #define HC_INTL_INT (1 << 7)
76 #define HC_EOT_INT (1 << 3)
77 #define HC_SOT_INT (1 << 1)
78
79 #define HC_ISO_IRQ_MASK_OR_REG 0x318
80 #define HC_INT_IRQ_MASK_OR_REG 0x31C
81 #define HC_ATL_IRQ_MASK_OR_REG 0x320
82 #define HC_ISO_IRQ_MASK_AND_REG 0x324
83 #define HC_INT_IRQ_MASK_AND_REG 0x328
84 #define HC_ATL_IRQ_MASK_AND_REG 0x32C
85
86 /* Register sets */
87 #define HC_BEGIN_OF_ATL 0x0c00
88 #define HC_BEGIN_OF_INT 0x0800
89 #define HC_BEGIN_OF_ISO 0x0400
90 #define HC_BEGIN_OF_PAYLOAD 0x1000
91
92 /* urb state*/
93 #define DELETE_URB (0x0008)
94 #define NO_TRANSFER_ACTIVE (0xffffffff)
95
96 #define ATL_REGS_OFFSET (0xc00)
97 #define INT_REGS_OFFSET (0x800)
98
99 /* Philips Transfer Descriptor (PTD) */
100 struct ptd {
101 __le32 dw0;
102 __le32 dw1;
103 __le32 dw2;
104 __le32 dw3;
105 __le32 dw4;
106 __le32 dw5;
107 __le32 dw6;
108 __le32 dw7;
109 };
110
111 struct inter_packet_info {
112 void *data_buffer;
113 u32 payload;
114 #define PTD_FIRE_NEXT (1 << 0)
115 #define PTD_URB_FINISHED (1 << 1)
116 struct urb *urb;
117 struct isp1760_qh *qh;
118 struct isp1760_qtd *qtd;
119 };
120
121
122 typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
123 struct isp1760_qtd *qtd);
124
125 #define isp1760_dbg(priv, fmt, args...) \
126 dev_dbg(priv_to_hcd(priv)->self.controller, fmt, ##args)
127
128 #define isp1760_info(priv, fmt, args...) \
129 dev_info(priv_to_hcd(priv)->self.controller, fmt, ##args)
130
131 #define isp1760_err(priv, fmt, args...) \
132 dev_err(priv_to_hcd(priv)->self.controller, fmt, ##args)
133
134 /*
135 * Device flags that can vary from board to board. All of these
136 * indicate the most "atypical" case, so that a devflags of 0 is
137 * a sane default configuration.
138 */
139 #define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */
140 #define ISP1760_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */
141 #define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */
142 #define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */
143 #define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */
144 #define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */
145
146 /* chip memory management */
147 struct memory_chunk {
148 unsigned int start;
149 unsigned int size;
150 unsigned int free;
151 };
152
153 /*
154 * 60kb divided in:
155 * - 32 blocks @ 256 bytes
156 * - 20 blocks @ 1024 bytes
157 * - 4 blocks @ 8192 bytes
158 */
159
160 #define BLOCK_1_NUM 32
161 #define BLOCK_2_NUM 20
162 #define BLOCK_3_NUM 4
163
164 #define BLOCK_1_SIZE 256
165 #define BLOCK_2_SIZE 1024
166 #define BLOCK_3_SIZE 8192
167 #define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM)
168 #define PAYLOAD_SIZE 0xf000
169
170 /* I saw if some reloads if the pointer was negative */
171 #define ISP1760_NULL_POINTER (0x400)
172
173 /* ATL */
174 /* DW0 */
175 #define PTD_VALID 1
176 #define PTD_LENGTH(x) (((u32) x) << 3)
177 #define PTD_MAXPACKET(x) (((u32) x) << 18)
178 #define PTD_MULTI(x) (((u32) x) << 29)
179 #define PTD_ENDPOINT(x) (((u32) x) << 31)
180 /* DW1 */
181 #define PTD_DEVICE_ADDR(x) (((u32) x) << 3)
182 #define PTD_PID_TOKEN(x) (((u32) x) << 10)
183 #define PTD_TRANS_BULK ((u32) 2 << 12)
184 #define PTD_TRANS_INT ((u32) 3 << 12)
185 #define PTD_TRANS_SPLIT ((u32) 1 << 14)
186 #define PTD_SE_USB_LOSPEED ((u32) 2 << 16)
187 #define PTD_PORT_NUM(x) (((u32) x) << 18)
188 #define PTD_HUB_NUM(x) (((u32) x) << 25)
189 #define PTD_PING(x) (((u32) x) << 26)
190 /* DW2 */
191 #define PTD_RL_CNT(x) (((u32) x) << 25)
192 #define PTD_DATA_START_ADDR(x) (((u32) x) << 8)
193 #define BASE_ADDR 0x1000
194 /* DW3 */
195 #define PTD_CERR(x) (((u32) x) << 23)
196 #define PTD_NAC_CNT(x) (((u32) x) << 19)
197 #define PTD_ACTIVE ((u32) 1 << 31)
198 #define PTD_DATA_TOGGLE(x) (((u32) x) << 25)
199
200 #define DW3_HALT_BIT (1 << 30)
201 #define DW3_ERROR_BIT (1 << 28)
202 #define DW3_QTD_ACTIVE (1 << 31)
203
204 #define INT_UNDERRUN (1 << 2)
205 #define INT_BABBLE (1 << 1)
206 #define INT_EXACT (1 << 0)
207
208 #define DW1_GET_PID(x) (((x) >> 10) & 0x3)
209 #define PTD_XFERRED_LENGTH(x) ((x) & 0x7fff)
210 #define PTD_XFERRED_LENGTH_LO(x) ((x) & 0x7ff)
211
212 #define SETUP_PID (2)
213 #define IN_PID (1)
214 #define OUT_PID (0)
215 #define GET_QTD_TOKEN_TYPE(x) ((x) & 0x3)
216
217 #define DATA_TOGGLE (1 << 31)
218 #define GET_DATA_TOGGLE(x) ((x) >> 31)
219
220 /* Errata 1 */
221 #define RL_COUNTER (0)
222 #define NAK_COUNTER (0)
223 #define ERR_COUNTER (2)
224
225 #define HC_ATL_PL_SIZE (8192)
226
227 #endif
228
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