1 /*
2 * Copyright (c) 2001-2002 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
21
22 /* definitions used for the EHCI driver */
23
24 /*
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
28 *
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
31 */
32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33 typedef __u32 __bitwise __hc32;
34 typedef __u16 __bitwise __hc16;
35 #else
36 #define __hc32 __le32
37 #define __hc16 __le16
38 #endif
39
40 /* statistics can be kept for for tuning/monitoring */
41 struct ehci_stats {
42 /* irq usage */
43 unsigned long normal;
44 unsigned long error;
45 unsigned long reclaim;
46 unsigned long lost_iaa;
47
48 /* termination of urbs from core */
49 unsigned long complete;
50 unsigned long unlink;
51 };
52
53 /* ehci_hcd->lock guards shared data against other CPUs:
54 * ehci_hcd: async, reclaim, periodic (and shadow), ...
55 * usb_host_endpoint: hcpriv
56 * ehci_qh: qh_next, qtd_list
57 * ehci_qtd: qtd_list
58 *
59 * Also, hold this lock when talking to HC registers or
60 * when updating hw_* fields in shared qh/qtd/... structures.
61 */
62
63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
64
65 struct ehci_hcd { /* one per controller */
66 /* glue to PCI and HCD framework */
67 struct ehci_caps __iomem *caps;
68 struct ehci_regs __iomem *regs;
69 struct ehci_dbg_port __iomem *debug;
70
71 __u32 hcs_params; /* cached register copy */
72 spinlock_t lock;
73
74 /* async schedule support */
75 struct ehci_qh *async;
76 struct ehci_qh *reclaim;
77 unsigned scanning : 1;
78
79 /* periodic schedule support */
80 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
81 unsigned periodic_size;
82 __hc32 *periodic; /* hw periodic table */
83 dma_addr_t periodic_dma;
84 unsigned i_thresh; /* uframes HC might cache */
85
86 union ehci_shadow *pshadow; /* mirror hw periodic table */
87 int next_uframe; /* scan periodic, start here */
88 unsigned periodic_sched; /* periodic activity count */
89
90 /* list of itds completed while clock_frame was still active */
91 struct list_head cached_itd_list;
92 unsigned clock_frame;
93
94 /* per root hub port */
95 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
96
97 /* bit vectors (one bit per port) */
98 unsigned long bus_suspended; /* which ports were
99 already suspended at the start of a bus suspend */
100 unsigned long companion_ports; /* which ports are
101 dedicated to the companion controller */
102 unsigned long owned_ports; /* which ports are
103 owned by the companion during a bus suspend */
104 unsigned long port_c_suspend; /* which ports have
105 the change-suspend feature turned on */
106 unsigned long suspended_ports; /* which ports are
107 suspended */
108
109 /* per-HC memory pools (could be per-bus, but ...) */
110 struct dma_pool *qh_pool; /* qh per active urb */
111 struct dma_pool *qtd_pool; /* one or more per qh */
112 struct dma_pool *itd_pool; /* itd per iso urb */
113 struct dma_pool *sitd_pool; /* sitd per split iso urb */
114
115 struct timer_list iaa_watchdog;
116 struct timer_list watchdog;
117 unsigned long actions;
118 unsigned stamp;
119 unsigned random_frame;
120 unsigned long next_statechange;
121 ktime_t last_periodic_enable;
122 u32 command;
123
124 /* SILICON QUIRKS */
125 unsigned no_selective_suspend:1;
126 unsigned has_fsl_port_bug:1; /* FreeScale */
127 unsigned big_endian_mmio:1;
128 unsigned big_endian_desc:1;
129 unsigned has_amcc_usb23:1;
130 unsigned broken_periodic:1;
131
132 /* required for usb32 quirk */
133 #define OHCI_CTRL_HCFS (3 << 6)
134 #define OHCI_USB_OPER (2 << 6)
135 #define OHCI_USB_SUSPEND (3 << 6)
136
137 #define OHCI_HCCTRL_OFFSET 0x4
138 #define OHCI_HCCTRL_LEN 0x4
139 __hc32 *ohci_hcctrl_reg;
140
141 u8 sbrn; /* packed release number */
142
143 /* irq statistics */
144 #ifdef EHCI_STATS
145 struct ehci_stats stats;
146 # define COUNT(x) do { (x)++; } while (0)
147 #else
148 # define COUNT(x) do {} while (0)
149 #endif
150
151 /* debug files */
152 #ifdef DEBUG
153 struct dentry *debug_dir;
154 struct dentry *debug_async;
155 struct dentry *debug_periodic;
156 struct dentry *debug_registers;
157 #endif
158 };
159
160 /* convert between an HCD pointer and the corresponding EHCI_HCD */
161 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
162 {
163 return (struct ehci_hcd *) (hcd->hcd_priv);
164 }
165 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
166 {
167 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
168 }
169
170
171 static inline void
172 iaa_watchdog_start(struct ehci_hcd *ehci)
173 {
174 WARN_ON(timer_pending(&ehci->iaa_watchdog));
175 mod_timer(&ehci->iaa_watchdog,
176 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
177 }
178
179 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
180 {
181 del_timer(&ehci->iaa_watchdog);
182 }
183
184 enum ehci_timer_action {
185 TIMER_IO_WATCHDOG,
186 TIMER_ASYNC_SHRINK,
187 TIMER_ASYNC_OFF,
188 };
189
190 static inline void
191 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
192 {
193 clear_bit (action, &ehci->actions);
194 }
195
196 static void free_cached_itd_list(struct ehci_hcd *ehci);
197
198 /*-------------------------------------------------------------------------*/
199
200 #include <linux/usb/ehci_def.h>
201
202 /*-------------------------------------------------------------------------*/
203
204 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
205
206 /*
207 * EHCI Specification 0.95 Section 3.5
208 * QTD: describe data transfer components (buffer, direction, ...)
209 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
210 *
211 * These are associated only with "QH" (Queue Head) structures,
212 * used with control, bulk, and interrupt transfers.
213 */
214 struct ehci_qtd {
215 /* first part defined by EHCI spec */
216 __hc32 hw_next; /* see EHCI 3.5.1 */
217 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
218 __hc32 hw_token; /* see EHCI 3.5.3 */
219 #define QTD_TOGGLE (1 << 31) /* data toggle */
220 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
221 #define QTD_IOC (1 << 15) /* interrupt on complete */
222 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
223 #define QTD_PID(tok) (((tok)>>8) & 0x3)
224 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
225 #define QTD_STS_HALT (1 << 6) /* halted on error */
226 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
227 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
228 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
229 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
230 #define QTD_STS_STS (1 << 1) /* split transaction state */
231 #define QTD_STS_PING (1 << 0) /* issue PING? */
232
233 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
234 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
235 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
236
237 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
238 __hc32 hw_buf_hi [5]; /* Appendix B */
239
240 /* the rest is HCD-private */
241 dma_addr_t qtd_dma; /* qtd address */
242 struct list_head qtd_list; /* sw qtd list */
243 struct urb *urb; /* qtd's urb */
244 size_t length; /* length of buffer */
245 } __attribute__ ((aligned (32)));
246
247 /* mask NakCnt+T in qh->hw_alt_next */
248 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
249
250 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
251
252 /*-------------------------------------------------------------------------*/
253
254 /* type tag from {qh,itd,sitd,fstn}->hw_next */
255 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
256
257 /*
258 * Now the following defines are not converted using the
259 * cpu_to_le32() macro anymore, since we have to support
260 * "dynamic" switching between be and le support, so that the driver
261 * can be used on one system with SoC EHCI controller using big-endian
262 * descriptors as well as a normal little-endian PCI EHCI controller.
263 */
264 /* values for that type tag */
265 #define Q_TYPE_ITD (0 << 1)
266 #define Q_TYPE_QH (1 << 1)
267 #define Q_TYPE_SITD (2 << 1)
268 #define Q_TYPE_FSTN (3 << 1)
269
270 /* next async queue entry, or pointer to interrupt/periodic QH */
271 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
272
273 /* for periodic/async schedules and qtd lists, mark end of list */
274 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
275
276 /*
277 * Entries in periodic shadow table are pointers to one of four kinds
278 * of data structure. That's dictated by the hardware; a type tag is
279 * encoded in the low bits of the hardware's periodic schedule. Use
280 * Q_NEXT_TYPE to get the tag.
281 *
282 * For entries in the async schedule, the type tag always says "qh".
283 */
284 union ehci_shadow {
285 struct ehci_qh *qh; /* Q_TYPE_QH */
286 struct ehci_itd *itd; /* Q_TYPE_ITD */
287 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
288 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
289 __hc32 *hw_next; /* (all types) */
290 void *ptr;
291 };
292
293 /*-------------------------------------------------------------------------*/
294
295 /*
296 * EHCI Specification 0.95 Section 3.6
297 * QH: describes control/bulk/interrupt endpoints
298 * See Fig 3-7 "Queue Head Structure Layout".
299 *
300 * These appear in both the async and (for interrupt) periodic schedules.
301 */
302
303 struct ehci_qh {
304 /* first part defined by EHCI spec */
305 __hc32 hw_next; /* see EHCI 3.6.1 */
306 __hc32 hw_info1; /* see EHCI 3.6.2 */
307 #define QH_HEAD 0x00008000
308 __hc32 hw_info2; /* see EHCI 3.6.2 */
309 #define QH_SMASK 0x000000ff
310 #define QH_CMASK 0x0000ff00
311 #define QH_HUBADDR 0x007f0000
312 #define QH_HUBPORT 0x3f800000
313 #define QH_MULT 0xc0000000
314 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
315
316 /* qtd overlay (hardware parts of a struct ehci_qtd) */
317 __hc32 hw_qtd_next;
318 __hc32 hw_alt_next;
319 __hc32 hw_token;
320 __hc32 hw_buf [5];
321 __hc32 hw_buf_hi [5];
322
323 /* the rest is HCD-private */
324 dma_addr_t qh_dma; /* address of qh */
325 union ehci_shadow qh_next; /* ptr to qh; or periodic */
326 struct list_head qtd_list; /* sw qtd list */
327 struct ehci_qtd *dummy;
328 struct ehci_qh *reclaim; /* next to reclaim */
329
330 struct ehci_hcd *ehci;
331
332 /*
333 * Do NOT use atomic operations for QH refcounting. On some CPUs
334 * (PPC7448 for example), atomic operations cannot be performed on
335 * memory that is cache-inhibited (i.e. being used for DMA).
336 * Spinlocks are used to protect all QH fields.
337 */
338 u32 refcount;
339 unsigned stamp;
340
341 u8 qh_state;
342 #define QH_STATE_LINKED 1 /* HC sees this */
343 #define QH_STATE_UNLINK 2 /* HC may still see this */
344 #define QH_STATE_IDLE 3 /* HC doesn't see this */
345 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
346 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
347
348 u8 xacterrs; /* XactErr retry counter */
349 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
350
351 /* periodic schedule info */
352 u8 usecs; /* intr bandwidth */
353 u8 gap_uf; /* uframes split/csplit gap */
354 u8 c_usecs; /* ... split completion bw */
355 u16 tt_usecs; /* tt downstream bandwidth */
356 unsigned short period; /* polling interval */
357 unsigned short start; /* where polling starts */
358 #define NO_FRAME ((unsigned short)~0) /* pick new start */
359
360 struct usb_device *dev; /* access to TT */
361 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
362 } __attribute__ ((aligned (32)));
363
364 /*-------------------------------------------------------------------------*/
365
366 /* description of one iso transaction (up to 3 KB data if highspeed) */
367 struct ehci_iso_packet {
368 /* These will be copied to iTD when scheduling */
369 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
370 __hc32 transaction; /* itd->hw_transaction[i] |= */
371 u8 cross; /* buf crosses pages */
372 /* for full speed OUT splits */
373 u32 buf1;
374 };
375
376 /* temporary schedule data for packets from iso urbs (both speeds)
377 * each packet is one logical usb transaction to the device (not TT),
378 * beginning at stream->next_uframe
379 */
380 struct ehci_iso_sched {
381 struct list_head td_list;
382 unsigned span;
383 struct ehci_iso_packet packet [0];
384 };
385
386 /*
387 * ehci_iso_stream - groups all (s)itds for this endpoint.
388 * acts like a qh would, if EHCI had them for ISO.
389 */
390 struct ehci_iso_stream {
391 /* first two fields match QH, but info1 == 0 */
392 __hc32 hw_next;
393 __hc32 hw_info1;
394
395 u32 refcount;
396 u8 bEndpointAddress;
397 u8 highspeed;
398 u16 depth; /* depth in uframes */
399 struct list_head td_list; /* queued itds/sitds */
400 struct list_head free_list; /* list of unused itds/sitds */
401 struct usb_device *udev;
402 struct usb_host_endpoint *ep;
403
404 /* output of (re)scheduling */
405 unsigned long start; /* jiffies */
406 unsigned long rescheduled;
407 int next_uframe;
408 __hc32 splits;
409
410 /* the rest is derived from the endpoint descriptor,
411 * trusting urb->interval == f(epdesc->bInterval) and
412 * including the extra info for hw_bufp[0..2]
413 */
414 u8 usecs, c_usecs;
415 u16 interval;
416 u16 tt_usecs;
417 u16 maxp;
418 u16 raw_mask;
419 unsigned bandwidth;
420
421 /* This is used to initialize iTD's hw_bufp fields */
422 __hc32 buf0;
423 __hc32 buf1;
424 __hc32 buf2;
425
426 /* this is used to initialize sITD's tt info */
427 __hc32 address;
428 };
429
430 /*-------------------------------------------------------------------------*/
431
432 /*
433 * EHCI Specification 0.95 Section 3.3
434 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
435 *
436 * Schedule records for high speed iso xfers
437 */
438 struct ehci_itd {
439 /* first part defined by EHCI spec */
440 __hc32 hw_next; /* see EHCI 3.3.1 */
441 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
442 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
443 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
444 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
445 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
446 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
447 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
448
449 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
450
451 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
452 __hc32 hw_bufp_hi [7]; /* Appendix B */
453
454 /* the rest is HCD-private */
455 dma_addr_t itd_dma; /* for this itd */
456 union ehci_shadow itd_next; /* ptr to periodic q entry */
457
458 struct urb *urb;
459 struct ehci_iso_stream *stream; /* endpoint's queue */
460 struct list_head itd_list; /* list of stream's itds */
461
462 /* any/all hw_transactions here may be used by that urb */
463 unsigned frame; /* where scheduled */
464 unsigned pg;
465 unsigned index[8]; /* in urb->iso_frame_desc */
466 } __attribute__ ((aligned (32)));
467
468 /*-------------------------------------------------------------------------*/
469
470 /*
471 * EHCI Specification 0.95 Section 3.4
472 * siTD, aka split-transaction isochronous Transfer Descriptor
473 * ... describe full speed iso xfers through TT in hubs
474 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
475 */
476 struct ehci_sitd {
477 /* first part defined by EHCI spec */
478 __hc32 hw_next;
479 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
480 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
481 __hc32 hw_uframe; /* EHCI table 3-10 */
482 __hc32 hw_results; /* EHCI table 3-11 */
483 #define SITD_IOC (1 << 31) /* interrupt on completion */
484 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
485 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
486 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
487 #define SITD_STS_ERR (1 << 6) /* error from TT */
488 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
489 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
490 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
491 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
492 #define SITD_STS_STS (1 << 1) /* split transaction state */
493
494 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
495
496 __hc32 hw_buf [2]; /* EHCI table 3-12 */
497 __hc32 hw_backpointer; /* EHCI table 3-13 */
498 __hc32 hw_buf_hi [2]; /* Appendix B */
499
500 /* the rest is HCD-private */
501 dma_addr_t sitd_dma;
502 union ehci_shadow sitd_next; /* ptr to periodic q entry */
503
504 struct urb *urb;
505 struct ehci_iso_stream *stream; /* endpoint's queue */
506 struct list_head sitd_list; /* list of stream's sitds */
507 unsigned frame;
508 unsigned index;
509 } __attribute__ ((aligned (32)));
510
511 /*-------------------------------------------------------------------------*/
512
513 /*
514 * EHCI Specification 0.96 Section 3.7
515 * Periodic Frame Span Traversal Node (FSTN)
516 *
517 * Manages split interrupt transactions (using TT) that span frame boundaries
518 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
519 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
520 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
521 */
522 struct ehci_fstn {
523 __hc32 hw_next; /* any periodic q entry */
524 __hc32 hw_prev; /* qh or EHCI_LIST_END */
525
526 /* the rest is HCD-private */
527 dma_addr_t fstn_dma;
528 union ehci_shadow fstn_next; /* ptr to periodic q entry */
529 } __attribute__ ((aligned (32)));
530
531 /*-------------------------------------------------------------------------*/
532
533 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
534
535 /*
536 * Some EHCI controllers have a Transaction Translator built into the
537 * root hub. This is a non-standard feature. Each controller will need
538 * to add code to the following inline functions, and call them as
539 * needed (mostly in root hub code).
540 */
541
542 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
543
544 /* Returns the speed of a device attached to a port on the root hub. */
545 static inline unsigned int
546 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
547 {
548 if (ehci_is_TDI(ehci)) {
549 switch ((portsc>>26)&3) {
550 case 0:
551 return 0;
552 case 1:
553 return (1<<USB_PORT_FEAT_LOWSPEED);
554 case 2:
555 default:
556 return (1<<USB_PORT_FEAT_HIGHSPEED);
557 }
558 }
559 return (1<<USB_PORT_FEAT_HIGHSPEED);
560 }
561
562 #else
563
564 #define ehci_is_TDI(e) (0)
565
566 #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED)
567 #endif
568
569 /*-------------------------------------------------------------------------*/
570
571 #ifdef CONFIG_PPC_83xx
572 /* Some Freescale processors have an erratum in which the TT
573 * port number in the queue head was 0..N-1 instead of 1..N.
574 */
575 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
576 #else
577 #define ehci_has_fsl_portno_bug(e) (0)
578 #endif
579
580 /*
581 * While most USB host controllers implement their registers in
582 * little-endian format, a minority (celleb companion chip) implement
583 * them in big endian format.
584 *
585 * This attempts to support either format at compile time without a
586 * runtime penalty, or both formats with the additional overhead
587 * of checking a flag bit.
588 */
589
590 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
591 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
592 #else
593 #define ehci_big_endian_mmio(e) 0
594 #endif
595
596 /*
597 * Big-endian read/write functions are arch-specific.
598 * Other arches can be added if/when they're needed.
599 */
600 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
601 #define readl_be(addr) __raw_readl((__force unsigned *)addr)
602 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
603 #endif
604
605 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
606 __u32 __iomem * regs)
607 {
608 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
609 return ehci_big_endian_mmio(ehci) ?
610 readl_be(regs) :
611 readl(regs);
612 #else
613 return readl(regs);
614 #endif
615 }
616
617 static inline void ehci_writel(const struct ehci_hcd *ehci,
618 const unsigned int val, __u32 __iomem *regs)
619 {
620 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
621 ehci_big_endian_mmio(ehci) ?
622 writel_be(val, regs) :
623 writel(val, regs);
624 #else
625 writel(val, regs);
626 #endif
627 }
628
629 /*
630 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
631 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
632 * Other common bits are dependant on has_amcc_usb23 quirk flag.
633 */
634 #ifdef CONFIG_44x
635 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
636 {
637 u32 hc_control;
638
639 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
640 if (operational)
641 hc_control |= OHCI_USB_OPER;
642 else
643 hc_control |= OHCI_USB_SUSPEND;
644
645 writel_be(hc_control, ehci->ohci_hcctrl_reg);
646 (void) readl_be(ehci->ohci_hcctrl_reg);
647 }
648 #else
649 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
650 { }
651 #endif
652
653 /*-------------------------------------------------------------------------*/
654
655 /*
656 * The AMCC 440EPx not only implements its EHCI registers in big-endian
657 * format, but also its DMA data structures (descriptors).
658 *
659 * EHCI controllers accessed through PCI work normally (little-endian
660 * everywhere), so we won't bother supporting a BE-only mode for now.
661 */
662 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
663 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
664
665 /* cpu to ehci */
666 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
667 {
668 return ehci_big_endian_desc(ehci)
669 ? (__force __hc32)cpu_to_be32(x)
670 : (__force __hc32)cpu_to_le32(x);
671 }
672
673 /* ehci to cpu */
674 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
675 {
676 return ehci_big_endian_desc(ehci)
677 ? be32_to_cpu((__force __be32)x)
678 : le32_to_cpu((__force __le32)x);
679 }
680
681 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
682 {
683 return ehci_big_endian_desc(ehci)
684 ? be32_to_cpup((__force __be32 *)x)
685 : le32_to_cpup((__force __le32 *)x);
686 }
687
688 #else
689
690 /* cpu to ehci */
691 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
692 {
693 return cpu_to_le32(x);
694 }
695
696 /* ehci to cpu */
697 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
698 {
699 return le32_to_cpu(x);
700 }
701
702 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
703 {
704 return le32_to_cpup(x);
705 }
706
707 #endif
708
709 /*-------------------------------------------------------------------------*/
710
711 #ifndef DEBUG
712 #define STUB_DEBUG_FILES
713 #endif /* DEBUG */
714
715 /*-------------------------------------------------------------------------*/
716
717 #endif /* __LINUX_EHCI_HCD_H */
718
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