1 /*
2 * Copyright (c) 2000-2004 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 #include <linux/config.h>
20
21 #ifdef CONFIG_USB_DEBUG
22 #define DEBUG
23 #else
24 #undef DEBUG
25 #endif
26
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/dmapool.h>
30 #include <linux/kernel.h>
31 #include <linux/delay.h>
32 #include <linux/ioport.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <linux/smp_lock.h>
36 #include <linux/errno.h>
37 #include <linux/init.h>
38 #include <linux/timer.h>
39 #include <linux/list.h>
40 #include <linux/interrupt.h>
41 #include <linux/reboot.h>
42 #include <linux/usb.h>
43 #include <linux/moduleparam.h>
44 #include <linux/dma-mapping.h>
45
46 #include "../core/hcd.h"
47
48 #include <asm/byteorder.h>
49 #include <asm/io.h>
50 #include <asm/irq.h>
51 #include <asm/system.h>
52 #include <asm/unaligned.h>
53
54
55 /*-------------------------------------------------------------------------*/
56
57 /*
58 * EHCI hc_driver implementation ... experimental, incomplete.
59 * Based on the final 1.0 register interface specification.
60 *
61 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
62 * First was PCMCIA, like ISA; then CardBus, which is PCI.
63 * Next comes "CardBay", using USB 2.0 signals.
64 *
65 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
66 * Special thanks to Intel and VIA for providing host controllers to
67 * test this driver on, and Cypress (including In-System Design) for
68 * providing early devices for those host controllers to talk to!
69 *
70 * HISTORY:
71 *
72 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
73 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
74 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
75 * <sojkam@centrum.cz>, updates by DB).
76 *
77 * 2002-11-29 Correct handling for hw async_next register.
78 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
79 * only scheduling is different, no arbitrary limitations.
80 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
81 * clean up HC run state handshaking.
82 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
83 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
84 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
85 * 2002-05-07 Some error path cleanups to report better errors; wmb();
86 * use non-CVS version id; better iso bandwidth claim.
87 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
88 * errors in submit path. Bugfixes to interrupt scheduling/processing.
89 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
90 * more checking to generic hcd framework (db). Make it work with
91 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
92 * 2002-01-14 Minor cleanup; version synch.
93 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
94 * 2002-01-04 Control/Bulk queuing behaves.
95 *
96 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
97 * 2001-June Works with usb-storage and NEC EHCI on 2.4
98 */
99
100 #define DRIVER_VERSION "10 Dec 2004"
101 #define DRIVER_AUTHOR "David Brownell"
102 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
103
104 static const char hcd_name [] = "ehci_hcd";
105
106
107 #undef EHCI_VERBOSE_DEBUG
108 #undef EHCI_URB_TRACE
109
110 #ifdef DEBUG
111 #define EHCI_STATS
112 #endif
113
114 /* magic numbers that can affect system performance */
115 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
116 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
117 #define EHCI_TUNE_RL_TT 0
118 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
119 #define EHCI_TUNE_MULT_TT 1
120 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
121
122 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
123 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
124 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
125 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
126
127 /* Initial IRQ latency: faster than hw default */
128 static int log2_irq_thresh = 0; // 0 to 6
129 module_param (log2_irq_thresh, int, S_IRUGO);
130 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
131
132 /* initial park setting: slower than hw default */
133 static unsigned park = 0;
134 module_param (park, uint, S_IRUGO);
135 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
136
137 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
138
139 /*-------------------------------------------------------------------------*/
140
141 #include "ehci.h"
142 #include "ehci-dbg.c"
143
144 /*-------------------------------------------------------------------------*/
145
146 /*
147 * handshake - spin reading hc until handshake completes or fails
148 * @ptr: address of hc register to be read
149 * @mask: bits to look at in result of read
150 * @done: value of those bits when handshake succeeds
151 * @usec: timeout in microseconds
152 *
153 * Returns negative errno, or zero on success
154 *
155 * Success happens when the "mask" bits have the specified value (hardware
156 * handshake done). There are two failure modes: "usec" have passed (major
157 * hardware flakeout), or the register reads as all-ones (hardware removed).
158 *
159 * That last failure should_only happen in cases like physical cardbus eject
160 * before driver shutdown. But it also seems to be caused by bugs in cardbus
161 * bridge shutdown: shutting down the bridge before the devices using it.
162 */
163 static int handshake (void __iomem *ptr, u32 mask, u32 done, int usec)
164 {
165 u32 result;
166
167 do {
168 result = readl (ptr);
169 if (result == ~(u32)0) /* card removed */
170 return -ENODEV;
171 result &= mask;
172 if (result == done)
173 return 0;
174 udelay (1);
175 usec--;
176 } while (usec > 0);
177 return -ETIMEDOUT;
178 }
179
180 /* force HC to halt state from unknown (EHCI spec section 2.3) */
181 static int ehci_halt (struct ehci_hcd *ehci)
182 {
183 u32 temp = readl (&ehci->regs->status);
184
185 if ((temp & STS_HALT) != 0)
186 return 0;
187
188 temp = readl (&ehci->regs->command);
189 temp &= ~CMD_RUN;
190 writel (temp, &ehci->regs->command);
191 return handshake (&ehci->regs->status, STS_HALT, STS_HALT, 16 * 125);
192 }
193
194 /* reset a non-running (STS_HALT == 1) controller */
195 static int ehci_reset (struct ehci_hcd *ehci)
196 {
197 u32 command = readl (&ehci->regs->command);
198
199 command |= CMD_RESET;
200 dbg_cmd (ehci, "reset", command);
201 writel (command, &ehci->regs->command);
202 ehci_to_hcd(ehci)->state = USB_STATE_HALT;
203 ehci->next_statechange = jiffies;
204 return handshake (&ehci->regs->command, CMD_RESET, 0, 250 * 1000);
205 }
206
207 /* idle the controller (from running) */
208 static void ehci_quiesce (struct ehci_hcd *ehci)
209 {
210 u32 temp;
211
212 #ifdef DEBUG
213 if (!HCD_IS_RUNNING (ehci_to_hcd(ehci)->state))
214 BUG ();
215 #endif
216
217 /* wait for any schedule enables/disables to take effect */
218 temp = readl (&ehci->regs->command) << 10;
219 temp &= STS_ASS | STS_PSS;
220 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
221 temp, 16 * 125) != 0) {
222 ehci_to_hcd(ehci)->state = USB_STATE_HALT;
223 return;
224 }
225
226 /* then disable anything that's still active */
227 temp = readl (&ehci->regs->command);
228 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
229 writel (temp, &ehci->regs->command);
230
231 /* hardware can take 16 microframes to turn off ... */
232 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
233 0, 16 * 125) != 0) {
234 ehci_to_hcd(ehci)->state = USB_STATE_HALT;
235 return;
236 }
237 }
238
239 /*-------------------------------------------------------------------------*/
240
241 static void ehci_work(struct ehci_hcd *ehci, struct pt_regs *regs);
242
243 #include "ehci-hub.c"
244 #include "ehci-mem.c"
245 #include "ehci-q.c"
246 #include "ehci-sched.c"
247
248 /*-------------------------------------------------------------------------*/
249
250 static void ehci_watchdog (unsigned long param)
251 {
252 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
253 unsigned long flags;
254
255 spin_lock_irqsave (&ehci->lock, flags);
256
257 /* lost IAA irqs wedge things badly; seen with a vt8235 */
258 if (ehci->reclaim) {
259 u32 status = readl (&ehci->regs->status);
260
261 if (status & STS_IAA) {
262 ehci_vdbg (ehci, "lost IAA\n");
263 COUNT (ehci->stats.lost_iaa);
264 writel (STS_IAA, &ehci->regs->status);
265 ehci->reclaim_ready = 1;
266 }
267 }
268
269 /* stop async processing after it's idled a bit */
270 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
271 start_unlink_async (ehci, ehci->async);
272
273 /* ehci could run by timer, without IRQs ... */
274 ehci_work (ehci, NULL);
275
276 spin_unlock_irqrestore (&ehci->lock, flags);
277 }
278
279 #ifdef CONFIG_PCI
280
281 /* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
282 * off the controller (maybe it can boot from highspeed USB disks).
283 */
284 static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap)
285 {
286 if (cap & (1 << 16)) {
287 int msec = 5000;
288 struct pci_dev *pdev =
289 to_pci_dev(ehci_to_hcd(ehci)->self.controller);
290
291 /* request handoff to OS */
292 cap |= 1 << 24;
293 pci_write_config_dword(pdev, where, cap);
294
295 /* and wait a while for it to happen */
296 do {
297 msleep(10);
298 msec -= 10;
299 pci_read_config_dword(pdev, where, &cap);
300 } while ((cap & (1 << 16)) && msec);
301 if (cap & (1 << 16)) {
302 ehci_err (ehci, "BIOS handoff failed (%d, %04x)\n",
303 where, cap);
304 // some BIOS versions seem buggy...
305 // return 1;
306 ehci_warn (ehci, "continuing after BIOS bug...\n");
307 return 0;
308 }
309 ehci_dbg (ehci, "BIOS handoff succeeded\n");
310 }
311 return 0;
312 }
313
314 #endif
315
316 static int
317 ehci_reboot (struct notifier_block *self, unsigned long code, void *null)
318 {
319 struct ehci_hcd *ehci;
320
321 ehci = container_of (self, struct ehci_hcd, reboot_notifier);
322
323 /* make BIOS/etc use companion controller during reboot */
324 writel (0, &ehci->regs->configured_flag);
325 return 0;
326 }
327
328
329 /* called by khubd or root hub init threads */
330
331 static int ehci_hc_reset (struct usb_hcd *hcd)
332 {
333 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
334 u32 temp;
335 unsigned count = 256/4;
336
337 spin_lock_init (&ehci->lock);
338
339 ehci->caps = hcd->regs;
340 ehci->regs = hcd->regs + HC_LENGTH (readl (&ehci->caps->hc_capbase));
341 dbg_hcs_params (ehci, "reset");
342 dbg_hcc_params (ehci, "reset");
343
344 #ifdef CONFIG_PCI
345 /* EHCI 0.96 and later may have "extended capabilities" */
346 if (hcd->self.controller->bus == &pci_bus_type) {
347 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
348
349 /* AMD8111 EHCI doesn't work, according to AMD errata */
350 if ((pdev->vendor == PCI_VENDOR_ID_AMD)
351 && (pdev->device == 0x7463)) {
352 ehci_info (ehci, "ignoring AMD8111 (errata)\n");
353 return -EIO;
354 }
355
356 temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params));
357 } else
358 temp = 0;
359 while (temp && count--) {
360 u32 cap;
361
362 pci_read_config_dword (to_pci_dev(hcd->self.controller),
363 temp, &cap);
364 ehci_dbg (ehci, "capability %04x at %02x\n", cap, temp);
365 switch (cap & 0xff) {
366 case 1: /* BIOS/SMM/... handoff */
367 if (bios_handoff (ehci, temp, cap) != 0)
368 return -EOPNOTSUPP;
369 break;
370 case 0: /* illegal reserved capability */
371 ehci_warn (ehci, "illegal capability!\n");
372 cap = 0;
373 /* FALLTHROUGH */
374 default: /* unknown */
375 break;
376 }
377 temp = (cap >> 8) & 0xff;
378 }
379 if (!count) {
380 ehci_err (ehci, "bogus capabilities ... PCI problems!\n");
381 return -EIO;
382 }
383 #endif
384
385 /* cache this readonly data; minimize PCI reads */
386 ehci->hcs_params = readl (&ehci->caps->hcs_params);
387
388 /* at least the Genesys GL880S needs fixup here */
389 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
390 temp &= 0x0f;
391 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
392 ehci_dbg (ehci, "bogus port configuration: "
393 "cc=%d x pcc=%d < ports=%d\n",
394 HCS_N_CC(ehci->hcs_params),
395 HCS_N_PCC(ehci->hcs_params),
396 HCS_N_PORTS(ehci->hcs_params));
397
398 #ifdef CONFIG_PCI
399 if (hcd->self.controller->bus == &pci_bus_type) {
400 struct pci_dev *pdev;
401
402 pdev = to_pci_dev(hcd->self.controller);
403 switch (pdev->vendor) {
404 case 0x17a0: /* GENESYS */
405 /* GL880S: should be PORTS=2 */
406 temp |= (ehci->hcs_params & ~0xf);
407 ehci->hcs_params = temp;
408 break;
409 case PCI_VENDOR_ID_NVIDIA:
410 /* NF4: should be PCC=10 */
411 break;
412 }
413 }
414 #endif
415 }
416
417 /* force HC to halt state */
418 return ehci_halt (ehci);
419 }
420
421 static int ehci_start (struct usb_hcd *hcd)
422 {
423 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
424 u32 temp;
425 struct usb_device *udev;
426 struct usb_bus *bus;
427 int retval;
428 u32 hcc_params;
429 u8 sbrn = 0;
430 int first;
431
432 /* skip some things on restart paths */
433 first = (ehci->watchdog.data == 0);
434 if (first) {
435 init_timer (&ehci->watchdog);
436 ehci->watchdog.function = ehci_watchdog;
437 ehci->watchdog.data = (unsigned long) ehci;
438 }
439
440 /*
441 * hw default: 1K periodic list heads, one per frame.
442 * periodic_size can shrink by USBCMD update if hcc_params allows.
443 */
444 ehci->periodic_size = DEFAULT_I_TDPS;
445 if (first && (retval = ehci_mem_init (ehci, GFP_KERNEL)) < 0)
446 return retval;
447
448 /* controllers may cache some of the periodic schedule ... */
449 hcc_params = readl (&ehci->caps->hcc_params);
450 if (HCC_ISOC_CACHE (hcc_params)) // full frame cache
451 ehci->i_thresh = 8;
452 else // N microframes cached
453 ehci->i_thresh = 2 + HCC_ISOC_THRES (hcc_params);
454
455 ehci->reclaim = NULL;
456 ehci->reclaim_ready = 0;
457 ehci->next_uframe = -1;
458
459 /* controller state: unknown --> reset */
460
461 /* EHCI spec section 4.1 */
462 if ((retval = ehci_reset (ehci)) != 0) {
463 ehci_mem_cleanup (ehci);
464 return retval;
465 }
466 writel (ehci->periodic_dma, &ehci->regs->frame_list);
467
468 #ifdef CONFIG_PCI
469 if (hcd->self.controller->bus == &pci_bus_type) {
470 struct pci_dev *pdev;
471 u16 port_wake;
472
473 pdev = to_pci_dev(hcd->self.controller);
474
475 /* Serial Bus Release Number is at PCI 0x60 offset */
476 pci_read_config_byte(pdev, 0x60, &sbrn);
477
478 /* port wake capability, reported by boot firmware */
479 pci_read_config_word(pdev, 0x62, &port_wake);
480 hcd->can_wakeup = (port_wake & 1) != 0;
481
482 /* help hc dma work well with cachelines */
483 pci_set_mwi (pdev);
484
485 /* chip-specific init */
486 switch (pdev->vendor) {
487 case PCI_VENDOR_ID_ARC:
488 if (pdev->device == PCI_DEVICE_ID_ARC_EHCI)
489 ehci->is_arc_rh_tt = 1;
490 break;
491 }
492
493 }
494 #endif
495
496 /*
497 * dedicate a qh for the async ring head, since we couldn't unlink
498 * a 'real' qh without stopping the async schedule [4.8]. use it
499 * as the 'reclamation list head' too.
500 * its dummy is used in hw_alt_next of many tds, to prevent the qh
501 * from automatically advancing to the next td after short reads.
502 */
503 if (first) {
504 ehci->async->qh_next.qh = NULL;
505 ehci->async->hw_next = QH_NEXT (ehci->async->qh_dma);
506 ehci->async->hw_info1 = cpu_to_le32 (QH_HEAD);
507 ehci->async->hw_token = cpu_to_le32 (QTD_STS_HALT);
508 ehci->async->hw_qtd_next = EHCI_LIST_END;
509 ehci->async->qh_state = QH_STATE_LINKED;
510 ehci->async->hw_alt_next = QTD_NEXT (ehci->async->dummy->qtd_dma);
511 }
512 writel ((u32)ehci->async->qh_dma, &ehci->regs->async_next);
513
514 /*
515 * hcc_params controls whether ehci->regs->segment must (!!!)
516 * be used; it constrains QH/ITD/SITD and QTD locations.
517 * pci_pool consistent memory always uses segment zero.
518 * streaming mappings for I/O buffers, like pci_map_single(),
519 * can return segments above 4GB, if the device allows.
520 *
521 * NOTE: the dma mask is visible through dma_supported(), so
522 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
523 * Scsi_Host.highmem_io, and so forth. It's readonly to all
524 * host side drivers though.
525 */
526 if (HCC_64BIT_ADDR (hcc_params)) {
527 writel (0, &ehci->regs->segment);
528 #if 0
529 // this is deeply broken on almost all architectures
530 if (!pci_set_dma_mask (to_pci_dev(hcd->self.controller), 0xffffffffffffffffULL))
531 ehci_info (ehci, "enabled 64bit PCI DMA\n");
532 #endif
533 }
534
535 /* clear interrupt enables, set irq latency */
536 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
537 log2_irq_thresh = 0;
538 temp = 1 << (16 + log2_irq_thresh);
539 if (HCC_CANPARK(hcc_params)) {
540 /* HW default park == 3, on hardware that supports it (like
541 * NVidia and ALI silicon), maximizes throughput on the async
542 * schedule by avoiding QH fetches between transfers.
543 *
544 * With fast usb storage devices and NForce2, "park" seems to
545 * make problems: throughput reduction (!), data errors...
546 */
547 if (park) {
548 park = min (park, (unsigned) 3);
549 temp |= CMD_PARK;
550 temp |= park << 8;
551 }
552 ehci_info (ehci, "park %d\n", park);
553 }
554 if (HCC_PGM_FRAMELISTLEN (hcc_params)) {
555 /* periodic schedule size can be smaller than default */
556 temp &= ~(3 << 2);
557 temp |= (EHCI_TUNE_FLS << 2);
558 switch (EHCI_TUNE_FLS) {
559 case 0: ehci->periodic_size = 1024; break;
560 case 1: ehci->periodic_size = 512; break;
561 case 2: ehci->periodic_size = 256; break;
562 default: BUG ();
563 }
564 }
565 // Philips, Intel, and maybe others need CMD_RUN before the
566 // root hub will detect new devices (why?); NEC doesn't
567 temp |= CMD_RUN;
568 writel (temp, &ehci->regs->command);
569 dbg_cmd (ehci, "init", temp);
570
571 /* set async sleep time = 10 us ... ? */
572
573 /* wire up the root hub */
574 bus = hcd_to_bus (hcd);
575 udev = first ? usb_alloc_dev (NULL, bus, 0) : bus->root_hub;
576 if (!udev) {
577 done2:
578 ehci_mem_cleanup (ehci);
579 return -ENOMEM;
580 }
581 udev->speed = USB_SPEED_HIGH;
582 udev->state = first ? USB_STATE_ATTACHED : USB_STATE_CONFIGURED;
583
584 /*
585 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
586 * are explicitly handed to companion controller(s), so no TT is
587 * involved with the root hub. (Except where one is integrated,
588 * and there's no companion controller unless maybe for USB OTG.)
589 */
590 if (first) {
591 ehci->reboot_notifier.notifier_call = ehci_reboot;
592 register_reboot_notifier (&ehci->reboot_notifier);
593 }
594
595 hcd->state = USB_STATE_RUNNING;
596 writel (FLAG_CF, &ehci->regs->configured_flag);
597 readl (&ehci->regs->command); /* unblock posted write */
598
599 temp = HC_VERSION(readl (&ehci->caps->hc_capbase));
600 ehci_info (ehci,
601 "USB %x.%x %s, EHCI %x.%02x, driver %s\n",
602 ((sbrn & 0xf0)>>4), (sbrn & 0x0f),
603 first ? "initialized" : "restarted",
604 temp >> 8, temp & 0xff, DRIVER_VERSION);
605
606 /*
607 * From here on, khubd concurrently accesses the root
608 * hub; drivers will be talking to enumerated devices.
609 * (On restart paths, khubd already knows about the root
610 * hub and could find work as soon as we wrote FLAG_CF.)
611 *
612 * Before this point the HC was idle/ready. After, khubd
613 * and device drivers may start it running.
614 */
615 if (first && hcd_register_root (udev, hcd) != 0) {
616 if (hcd->state == USB_STATE_RUNNING)
617 ehci_quiesce (ehci);
618 ehci_reset (ehci);
619 usb_put_dev (udev);
620 retval = -ENODEV;
621 goto done2;
622 }
623
624 writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */
625
626 if (first)
627 create_debug_files (ehci);
628
629 return 0;
630 }
631
632 /* always called by thread; normally rmmod */
633
634 static void ehci_stop (struct usb_hcd *hcd)
635 {
636 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
637 u8 rh_ports, port;
638
639 ehci_dbg (ehci, "stop\n");
640
641 /* Turn off port power on all root hub ports. */
642 rh_ports = HCS_N_PORTS (ehci->hcs_params);
643 for (port = 1; port <= rh_ports; port++)
644 (void) ehci_hub_control(hcd,
645 ClearPortFeature, USB_PORT_FEAT_POWER,
646 port, NULL, 0);
647
648 /* no more interrupts ... */
649 del_timer_sync (&ehci->watchdog);
650
651 spin_lock_irq(&ehci->lock);
652 if (HCD_IS_RUNNING (hcd->state))
653 ehci_quiesce (ehci);
654
655 ehci_reset (ehci);
656 writel (0, &ehci->regs->intr_enable);
657 spin_unlock_irq(&ehci->lock);
658
659 /* let companion controllers work when we aren't */
660 writel (0, &ehci->regs->configured_flag);
661 unregister_reboot_notifier (&ehci->reboot_notifier);
662
663 remove_debug_files (ehci);
664
665 /* root hub is shut down separately (first, when possible) */
666 spin_lock_irq (&ehci->lock);
667 if (ehci->async)
668 ehci_work (ehci, NULL);
669 spin_unlock_irq (&ehci->lock);
670 ehci_mem_cleanup (ehci);
671
672 #ifdef EHCI_STATS
673 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
674 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
675 ehci->stats.lost_iaa);
676 ehci_dbg (ehci, "complete %ld unlink %ld\n",
677 ehci->stats.complete, ehci->stats.unlink);
678 #endif
679
680 dbg_status (ehci, "ehci_stop completed", readl (&ehci->regs->status));
681 }
682
683 static int ehci_get_frame (struct usb_hcd *hcd)
684 {
685 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
686 return (readl (&ehci->regs->frame_index) >> 3) % ehci->periodic_size;
687 }
688
689 /*-------------------------------------------------------------------------*/
690
691 #ifdef CONFIG_PM
692
693 /* suspend/resume, section 4.3 */
694
695 /* These routines rely on the bus (pci, platform, etc)
696 * to handle powerdown and wakeup, and currently also on
697 * transceivers that don't need any software attention to set up
698 * the right sort of wakeup.
699 */
700
701 static int ehci_suspend (struct usb_hcd *hcd, u32 state)
702 {
703 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
704
705 if (time_before (jiffies, ehci->next_statechange))
706 msleep (100);
707
708 #ifdef CONFIG_USB_SUSPEND
709 (void) usb_suspend_device (hcd->self.root_hub, state);
710 #else
711 usb_lock_device (hcd->self.root_hub);
712 (void) ehci_hub_suspend (hcd);
713 usb_unlock_device (hcd->self.root_hub);
714 #endif
715
716 // save (PCI) FLADJ in case of Vaux power loss
717 // ... we'd only use it to handle clock skew
718
719 return 0;
720 }
721
722 static int ehci_resume (struct usb_hcd *hcd)
723 {
724 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
725 unsigned port;
726 struct usb_device *root = hcd->self.root_hub;
727 int retval = -EINVAL;
728 int powerup = 0;
729
730 // maybe restore (PCI) FLADJ
731
732 if (time_before (jiffies, ehci->next_statechange))
733 msleep (100);
734
735 /* If any port is suspended, we know we can/must resume the HC. */
736 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) {
737 u32 status;
738 port--;
739 status = readl (&ehci->regs->port_status [port]);
740 if (status & PORT_SUSPEND) {
741 down (&hcd->self.root_hub->serialize);
742 retval = ehci_hub_resume (hcd);
743 up (&hcd->self.root_hub->serialize);
744 break;
745 }
746 if ((status & PORT_POWER) == 0)
747 powerup = 1;
748 if (!root->children [port])
749 continue;
750 dbg_port (ehci, __FUNCTION__, port + 1, status);
751 usb_set_device_state (root->children[port],
752 USB_STATE_NOTATTACHED);
753 }
754
755 /* Else reset, to cope with power loss or flush-to-storage
756 * style "resume" having activated BIOS during reboot.
757 */
758 if (port == 0) {
759 (void) ehci_halt (ehci);
760 (void) ehci_reset (ehci);
761 (void) ehci_hc_reset (hcd);
762
763 /* emptying the schedule aborts any urbs */
764 spin_lock_irq (&ehci->lock);
765 if (ehci->reclaim)
766 ehci->reclaim_ready = 1;
767 ehci_work (ehci, NULL);
768 spin_unlock_irq (&ehci->lock);
769
770 /* restart; khubd will disconnect devices */
771 retval = ehci_start (hcd);
772
773 /* here we "know" root ports should always stay powered;
774 * but some controllers may lost all power.
775 */
776 if (powerup) {
777 ehci_dbg (ehci, "...powerup ports...\n");
778 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
779 (void) ehci_hub_control(hcd,
780 SetPortFeature, USB_PORT_FEAT_POWER,
781 port--, NULL, 0);
782 msleep(20);
783 }
784 }
785
786 return retval;
787 }
788
789 #endif
790
791 /*-------------------------------------------------------------------------*/
792
793 /*
794 * ehci_work is called from some interrupts, timers, and so on.
795 * it calls driver completion functions, after dropping ehci->lock.
796 */
797 static void ehci_work (struct ehci_hcd *ehci, struct pt_regs *regs)
798 {
799 timer_action_done (ehci, TIMER_IO_WATCHDOG);
800 if (ehci->reclaim_ready)
801 end_unlink_async (ehci, regs);
802
803 /* another CPU may drop ehci->lock during a schedule scan while
804 * it reports urb completions. this flag guards against bogus
805 * attempts at re-entrant schedule scanning.
806 */
807 if (ehci->scanning)
808 return;
809 ehci->scanning = 1;
810 scan_async (ehci, regs);
811 if (ehci->next_uframe != -1)
812 scan_periodic (ehci, regs);
813 ehci->scanning = 0;
814
815 /* the IO watchdog guards against hardware or driver bugs that
816 * misplace IRQs, and should let us run completely without IRQs.
817 * such lossage has been observed on both VT6202 and VT8235.
818 */
819 if (HCD_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
820 (ehci->async->qh_next.ptr != NULL ||
821 ehci->periodic_sched != 0))
822 timer_action (ehci, TIMER_IO_WATCHDOG);
823 }
824
825 /*-------------------------------------------------------------------------*/
826
827 static irqreturn_t ehci_irq (struct usb_hcd *hcd, struct pt_regs *regs)
828 {
829 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
830 u32 status;
831 int bh;
832
833 spin_lock (&ehci->lock);
834
835 status = readl (&ehci->regs->status);
836
837 /* e.g. cardbus physical eject */
838 if (status == ~(u32) 0) {
839 ehci_dbg (ehci, "device removed\n");
840 goto dead;
841 }
842
843 status &= INTR_MASK;
844 if (!status) { /* irq sharing? */
845 spin_unlock(&ehci->lock);
846 return IRQ_NONE;
847 }
848
849 /* clear (just) interrupts */
850 writel (status, &ehci->regs->status);
851 readl (&ehci->regs->command); /* unblock posted write */
852 bh = 0;
853
854 #ifdef EHCI_VERBOSE_DEBUG
855 /* unrequested/ignored: Frame List Rollover */
856 dbg_status (ehci, "irq", status);
857 #endif
858
859 /* INT, ERR, and IAA interrupt rates can be throttled */
860
861 /* normal [4.15.1.2] or error [4.15.1.1] completion */
862 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
863 if (likely ((status & STS_ERR) == 0))
864 COUNT (ehci->stats.normal);
865 else
866 COUNT (ehci->stats.error);
867 bh = 1;
868 }
869
870 /* complete the unlinking of some qh [4.15.2.3] */
871 if (status & STS_IAA) {
872 COUNT (ehci->stats.reclaim);
873 ehci->reclaim_ready = 1;
874 bh = 1;
875 }
876
877 /* remote wakeup [4.3.1] */
878 if ((status & STS_PCD) && hcd->remote_wakeup) {
879 unsigned i = HCS_N_PORTS (ehci->hcs_params);
880
881 /* resume root hub? */
882 status = readl (&ehci->regs->command);
883 if (!(status & CMD_RUN))
884 writel (status | CMD_RUN, &ehci->regs->command);
885
886 while (i--) {
887 status = readl (&ehci->regs->port_status [i]);
888 if (status & PORT_OWNER)
889 continue;
890 if (!(status & PORT_RESUME)
891 || ehci->reset_done [i] != 0)
892 continue;
893
894 /* start 20 msec resume signaling from this port,
895 * and make khubd collect PORT_STAT_C_SUSPEND to
896 * stop that signaling.
897 */
898 ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
899 mod_timer (&hcd->rh_timer,
900 ehci->reset_done [i] + 1);
901 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
902 }
903 }
904
905 /* PCI errors [4.15.2.4] */
906 if (unlikely ((status & STS_FATAL) != 0)) {
907 /* bogus "fatal" IRQs appear on some chips... why? */
908 status = readl (&ehci->regs->status);
909 dbg_cmd (ehci, "fatal", readl (&ehci->regs->command));
910 dbg_status (ehci, "fatal", status);
911 if (status & STS_HALT) {
912 ehci_err (ehci, "fatal error\n");
913 dead:
914 ehci_reset (ehci);
915 writel (0, &ehci->regs->configured_flag);
916 /* generic layer kills/unlinks all urbs, then
917 * uses ehci_stop to clean up the rest
918 */
919 bh = 1;
920 }
921 }
922
923 if (bh)
924 ehci_work (ehci, regs);
925 spin_unlock (&ehci->lock);
926 return IRQ_HANDLED;
927 }
928
929 /*-------------------------------------------------------------------------*/
930
931 /*
932 * non-error returns are a promise to giveback() the urb later
933 * we drop ownership so next owner (or urb unlink) can get it
934 *
935 * urb + dev is in hcd.self.controller.urb_list
936 * we're queueing TDs onto software and hardware lists
937 *
938 * hcd-specific init for hcpriv hasn't been done yet
939 *
940 * NOTE: control, bulk, and interrupt share the same code to append TDs
941 * to a (possibly active) QH, and the same QH scanning code.
942 */
943 static int ehci_urb_enqueue (
944 struct usb_hcd *hcd,
945 struct usb_host_endpoint *ep,
946 struct urb *urb,
947 int mem_flags
948 ) {
949 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
950 struct list_head qtd_list;
951
952 INIT_LIST_HEAD (&qtd_list);
953
954 switch (usb_pipetype (urb->pipe)) {
955 // case PIPE_CONTROL:
956 // case PIPE_BULK:
957 default:
958 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
959 return -ENOMEM;
960 return submit_async (ehci, ep, urb, &qtd_list, mem_flags);
961
962 case PIPE_INTERRUPT:
963 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
964 return -ENOMEM;
965 return intr_submit (ehci, ep, urb, &qtd_list, mem_flags);
966
967 case PIPE_ISOCHRONOUS:
968 if (urb->dev->speed == USB_SPEED_HIGH)
969 return itd_submit (ehci, urb, mem_flags);
970 else
971 return sitd_submit (ehci, urb, mem_flags);
972 }
973 }
974
975 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
976 {
977 /* if we need to use IAA and it's busy, defer */
978 if (qh->qh_state == QH_STATE_LINKED
979 && ehci->reclaim
980 && HCD_IS_RUNNING (ehci_to_hcd(ehci)->state)) {
981 struct ehci_qh *last;
982
983 for (last = ehci->reclaim;
984 last->reclaim;
985 last = last->reclaim)
986 continue;
987 qh->qh_state = QH_STATE_UNLINK_WAIT;
988 last->reclaim = qh;
989
990 /* bypass IAA if the hc can't care */
991 } else if (!HCD_IS_RUNNING (ehci_to_hcd(ehci)->state) && ehci->reclaim)
992 end_unlink_async (ehci, NULL);
993
994 /* something else might have unlinked the qh by now */
995 if (qh->qh_state == QH_STATE_LINKED)
996 start_unlink_async (ehci, qh);
997 }
998
999 /* remove from hardware lists
1000 * completions normally happen asynchronously
1001 */
1002
1003 static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
1004 {
1005 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1006 struct ehci_qh *qh;
1007 unsigned long flags;
1008
1009 spin_lock_irqsave (&ehci->lock, flags);
1010 switch (usb_pipetype (urb->pipe)) {
1011 // case PIPE_CONTROL:
1012 // case PIPE_BULK:
1013 default:
1014 qh = (struct ehci_qh *) urb->hcpriv;
1015 if (!qh)
1016 break;
1017 unlink_async (ehci, qh);
1018 break;
1019
1020 case PIPE_INTERRUPT:
1021 qh = (struct ehci_qh *) urb->hcpriv;
1022 if (!qh)
1023 break;
1024 switch (qh->qh_state) {
1025 case QH_STATE_LINKED:
1026 intr_deschedule (ehci, qh);
1027 /* FALL THROUGH */
1028 case QH_STATE_IDLE:
1029 qh_completions (ehci, qh, NULL);
1030 break;
1031 default:
1032 ehci_dbg (ehci, "bogus qh %p state %d\n",
1033 qh, qh->qh_state);
1034 goto done;
1035 }
1036
1037 /* reschedule QH iff another request is queued */
1038 if (!list_empty (&qh->qtd_list)
1039 && HCD_IS_RUNNING (hcd->state)) {
1040 int status;
1041
1042 status = qh_schedule (ehci, qh);
1043 spin_unlock_irqrestore (&ehci->lock, flags);
1044
1045 if (status != 0) {
1046 // shouldn't happen often, but ...
1047 // FIXME kill those tds' urbs
1048 err ("can't reschedule qh %p, err %d",
1049 qh, status);
1050 }
1051 return status;
1052 }
1053 break;
1054
1055 case PIPE_ISOCHRONOUS:
1056 // itd or sitd ...
1057
1058 // wait till next completion, do it then.
1059 // completion irqs can wait up to 1024 msec,
1060 break;
1061 }
1062 done:
1063 spin_unlock_irqrestore (&ehci->lock, flags);
1064 return 0;
1065 }
1066
1067 /*-------------------------------------------------------------------------*/
1068
1069 // bulk qh holds the data toggle
1070
1071 static void
1072 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1073 {
1074 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1075 unsigned long flags;
1076 struct ehci_qh *qh, *tmp;
1077
1078 /* ASSERT: any requests/urbs are being unlinked */
1079 /* ASSERT: nobody can be submitting urbs for this any more */
1080
1081 rescan:
1082 spin_lock_irqsave (&ehci->lock, flags);
1083 qh = ep->hcpriv;
1084 if (!qh)
1085 goto done;
1086
1087 /* endpoints can be iso streams. for now, we don't
1088 * accelerate iso completions ... so spin a while.
1089 */
1090 if (qh->hw_info1 == 0) {
1091 ehci_vdbg (ehci, "iso delay\n");
1092 goto idle_timeout;
1093 }
1094
1095 if (!HCD_IS_RUNNING (hcd->state))
1096 qh->qh_state = QH_STATE_IDLE;
1097 switch (qh->qh_state) {
1098 case QH_STATE_LINKED:
1099 for (tmp = ehci->async->qh_next.qh;
1100 tmp && tmp != qh;
1101 tmp = tmp->qh_next.qh)
1102 continue;
1103 /* periodic qh self-unlinks on empty */
1104 if (!tmp)
1105 goto nogood;
1106 unlink_async (ehci, qh);
1107 /* FALL THROUGH */
1108 case QH_STATE_UNLINK: /* wait for hw to finish? */
1109 idle_timeout:
1110 spin_unlock_irqrestore (&ehci->lock, flags);
1111 set_current_state (TASK_UNINTERRUPTIBLE);
1112 schedule_timeout (1);
1113 goto rescan;
1114 case QH_STATE_IDLE: /* fully unlinked */
1115 if (list_empty (&qh->qtd_list)) {
1116 qh_put (qh);
1117 break;
1118 }
1119 /* else FALL THROUGH */
1120 default:
1121 nogood:
1122 /* caller was supposed to have unlinked any requests;
1123 * that's not our job. just leak this memory.
1124 */
1125 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1126 qh, ep->desc.bEndpointAddress, qh->qh_state,
1127 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1128 break;
1129 }
1130 ep->hcpriv = NULL;
1131 done:
1132 spin_unlock_irqrestore (&ehci->lock, flags);
1133 return;
1134 }
1135
1136 /*-------------------------------------------------------------------------*/
1137
1138 static const struct hc_driver ehci_driver = {
1139 .description = hcd_name,
1140 .product_desc = "EHCI Host Controller",
1141 .hcd_priv_size = sizeof(struct ehci_hcd),
1142
1143 /*
1144 * generic hardware linkage
1145 */
1146 .irq = ehci_irq,
1147 .flags = HCD_MEMORY | HCD_USB2,
1148
1149 /*
1150 * basic lifecycle operations
1151 */
1152 .reset = ehci_hc_reset,
1153 .start = ehci_start,
1154 #ifdef CONFIG_PM
1155 .suspend = ehci_suspend,
1156 .resume = ehci_resume,
1157 #endif
1158 .stop = ehci_stop,
1159
1160 /*
1161 * managing i/o requests and associated device resources
1162 */
1163 .urb_enqueue = ehci_urb_enqueue,
1164 .urb_dequeue = ehci_urb_dequeue,
1165 .endpoint_disable = ehci_endpoint_disable,
1166
1167 /*
1168 * scheduling support
1169 */
1170 .get_frame_number = ehci_get_frame,
1171
1172 /*
1173 * root hub support
1174 */
1175 .hub_status_data = ehci_hub_status_data,
1176 .hub_control = ehci_hub_control,
1177 .hub_suspend = ehci_hub_suspend,
1178 .hub_resume = ehci_hub_resume,
1179 };
1180
1181 /*-------------------------------------------------------------------------*/
1182
1183 /* EHCI 1.0 doesn't require PCI */
1184
1185 #ifdef CONFIG_PCI
1186
1187 /* PCI driver selection metadata; PCI hotplugging uses this */
1188 static const struct pci_device_id pci_ids [] = { {
1189 /* handle any USB 2.0 EHCI controller */
1190 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0),
1191 .driver_data = (unsigned long) &ehci_driver,
1192 },
1193 { /* end: all zeroes */ }
1194 };
1195 MODULE_DEVICE_TABLE (pci, pci_ids);
1196
1197 /* pci driver glue; this is a "new style" PCI driver module */
1198 static struct pci_driver ehci_pci_driver = {
1199 .name = (char *) hcd_name,
1200 .id_table = pci_ids,
1201
1202 .probe = usb_hcd_pci_probe,
1203 .remove = usb_hcd_pci_remove,
1204
1205 #ifdef CONFIG_PM
1206 .suspend = usb_hcd_pci_suspend,
1207 .resume = usb_hcd_pci_resume,
1208 #endif
1209 };
1210
1211 #endif /* PCI */
1212
1213
1214 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
1215
1216 MODULE_DESCRIPTION (DRIVER_INFO);
1217 MODULE_AUTHOR (DRIVER_AUTHOR);
1218 MODULE_LICENSE ("GPL");
1219
1220 static int __init init (void)
1221 {
1222 if (usb_disabled())
1223 return -ENODEV;
1224
1225 pr_debug ("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1226 hcd_name,
1227 sizeof (struct ehci_qh), sizeof (struct ehci_qtd),
1228 sizeof (struct ehci_itd), sizeof (struct ehci_sitd));
1229
1230 return pci_register_driver (&ehci_pci_driver);
1231 }
1232 module_init (init);
1233
1234 static void __exit cleanup (void)
1235 {
1236 pci_unregister_driver (&ehci_pci_driver);
1237 }
1238 module_exit (cleanup);
1239
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