1 /*
2 * drivers/usb/gadget/qe_udc.h
3 *
4 * Copyright (C) 2006-2008 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Xiaobo Xie <X.Xie@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Description:
10 * Freescale USB device/endpoint management registers
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or (at
15 * your option) any later version.
16 */
17
18 #ifndef __FSL_QE_UDC_H
19 #define __FSL_QE_UDC_H
20
21 /* SoC type */
22 #define PORT_CPM 0
23 #define PORT_QE 1
24
25 #define USB_MAX_ENDPOINTS 4
26 #define USB_MAX_PIPES USB_MAX_ENDPOINTS
27 #define USB_EP0_MAX_SIZE 64
28 #define USB_MAX_CTRL_PAYLOAD 0x4000
29 #define USB_BDRING_LEN 16
30 #define USB_BDRING_LEN_RX 256
31 #define USB_BDRING_LEN_TX 16
32 #define MIN_EMPTY_BDS 128
33 #define MAX_DATA_BDS 8
34 #define USB_CRC_SIZE 2
35 #define USB_DIR_BOTH 0x88
36 #define R_BUF_MAXSIZE 0x800
37 #define USB_EP_PARA_ALIGNMENT 32
38
39 /* USB Mode Register bit define */
40 #define USB_MODE_EN 0x01
41 #define USB_MODE_HOST 0x02
42 #define USB_MODE_TEST 0x04
43 #define USB_MODE_SFTE 0x08
44 #define USB_MODE_RESUME 0x40
45 #define USB_MODE_LSS 0x80
46
47 /* USB Slave Address Register Mask */
48 #define USB_SLVADDR_MASK 0x7F
49
50 /* USB Endpoint register define */
51 #define USB_EPNUM_MASK 0xF000
52 #define USB_EPNUM_SHIFT 12
53
54 #define USB_TRANS_MODE_SHIFT 8
55 #define USB_TRANS_CTR 0x0000
56 #define USB_TRANS_INT 0x0100
57 #define USB_TRANS_BULK 0x0200
58 #define USB_TRANS_ISO 0x0300
59
60 #define USB_EP_MF 0x0020
61 #define USB_EP_RTE 0x0010
62
63 #define USB_THS_SHIFT 2
64 #define USB_THS_MASK 0x000c
65 #define USB_THS_NORMAL 0x0
66 #define USB_THS_IGNORE_IN 0x0004
67 #define USB_THS_NACK 0x0008
68 #define USB_THS_STALL 0x000c
69
70 #define USB_RHS_SHIFT 0
71 #define USB_RHS_MASK 0x0003
72 #define USB_RHS_NORMAL 0x0
73 #define USB_RHS_IGNORE_OUT 0x0001
74 #define USB_RHS_NACK 0x0002
75 #define USB_RHS_STALL 0x0003
76
77 #define USB_RTHS_MASK 0x000f
78
79 /* USB Command Register define */
80 #define USB_CMD_STR_FIFO 0x80
81 #define USB_CMD_FLUSH_FIFO 0x40
82 #define USB_CMD_ISFT 0x20
83 #define USB_CMD_DSFT 0x10
84 #define USB_CMD_EP_MASK 0x03
85
86 /* USB Event and Mask Register define */
87 #define USB_E_MSF_MASK 0x0800
88 #define USB_E_SFT_MASK 0x0400
89 #define USB_E_RESET_MASK 0x0200
90 #define USB_E_IDLE_MASK 0x0100
91 #define USB_E_TXE4_MASK 0x0080
92 #define USB_E_TXE3_MASK 0x0040
93 #define USB_E_TXE2_MASK 0x0020
94 #define USB_E_TXE1_MASK 0x0010
95 #define USB_E_SOF_MASK 0x0008
96 #define USB_E_BSY_MASK 0x0004
97 #define USB_E_TXB_MASK 0x0002
98 #define USB_E_RXB_MASK 0x0001
99 #define USBER_ALL_CLEAR 0x0fff
100
101 #define USB_E_DEFAULT_DEVICE (USB_E_RESET_MASK | USB_E_TXE4_MASK | \
102 USB_E_TXE3_MASK | USB_E_TXE2_MASK | \
103 USB_E_TXE1_MASK | USB_E_BSY_MASK | \
104 USB_E_TXB_MASK | USB_E_RXB_MASK)
105
106 #define USB_E_TXE_MASK (USB_E_TXE4_MASK | USB_E_TXE3_MASK|\
107 USB_E_TXE2_MASK | USB_E_TXE1_MASK)
108 /* USB Status Register define */
109 #define USB_IDLE_STATUS_MASK 0x01
110
111 /* USB Start of Frame Timer */
112 #define USB_USSFT_MASK 0x3FFF
113
114 /* USB Frame Number Register */
115 #define USB_USFRN_MASK 0xFFFF
116
117 struct usb_device_para{
118 u16 epptr[4];
119 u32 rstate;
120 u32 rptr;
121 u16 frame_n;
122 u16 rbcnt;
123 u32 rtemp;
124 u32 rxusb_data;
125 u16 rxuptr;
126 u8 reso[2];
127 u32 softbl;
128 u8 sofucrctemp;
129 };
130
131 struct usb_ep_para{
132 u16 rbase;
133 u16 tbase;
134 u8 rbmr;
135 u8 tbmr;
136 u16 mrblr;
137 u16 rbptr;
138 u16 tbptr;
139 u32 tstate;
140 u32 tptr;
141 u16 tcrc;
142 u16 tbcnt;
143 u32 ttemp;
144 u16 txusbu_ptr;
145 u8 reserve[2];
146 };
147
148 #define USB_BUSMODE_GBL 0x20
149 #define USB_BUSMODE_BO_MASK 0x18
150 #define USB_BUSMODE_BO_SHIFT 0x3
151 #define USB_BUSMODE_BE 0x2
152 #define USB_BUSMODE_CETM 0x04
153 #define USB_BUSMODE_DTB 0x02
154
155 /* Endpoint basic handle */
156 #define ep_index(EP) ((EP)->desc->bEndpointAddress & 0xF)
157 #define ep_maxpacket(EP) ((EP)->ep.maxpacket)
158 #define ep_is_in(EP) ((ep_index(EP) == 0) ? (EP->udc->ep0_dir == \
159 USB_DIR_IN) : ((EP)->desc->bEndpointAddress \
160 & USB_DIR_IN) == USB_DIR_IN)
161
162 /* ep0 transfer state */
163 #define WAIT_FOR_SETUP 0
164 #define DATA_STATE_XMIT 1
165 #define DATA_STATE_NEED_ZLP 2
166 #define WAIT_FOR_OUT_STATUS 3
167 #define DATA_STATE_RECV 4
168
169 /* ep tramsfer mode */
170 #define USBP_TM_CTL 0
171 #define USBP_TM_ISO 1
172 #define USBP_TM_BULK 2
173 #define USBP_TM_INT 3
174
175 /*-----------------------------------------------------------------------------
176 USB RX And TX DATA Frame
177 -----------------------------------------------------------------------------*/
178 struct qe_frame{
179 u8 *data;
180 u32 len;
181 u32 status;
182 u32 info;
183
184 void *privdata;
185 struct list_head node;
186 };
187
188 /* Frame structure, info field. */
189 #define PID_DATA0 0x80000000 /* Data toggle zero */
190 #define PID_DATA1 0x40000000 /* Data toggle one */
191 #define PID_SETUP 0x20000000 /* setup bit */
192 #define SETUP_STATUS 0x10000000 /* setup status bit */
193 #define SETADDR_STATUS 0x08000000 /* setupup address status bit */
194 #define NO_REQ 0x04000000 /* Frame without request */
195 #define HOST_DATA 0x02000000 /* Host data frame */
196 #define FIRST_PACKET_IN_FRAME 0x01000000 /* first packet in the frame */
197 #define TOKEN_FRAME 0x00800000 /* Host token frame */
198 #define ZLP 0x00400000 /* Zero length packet */
199 #define IN_TOKEN_FRAME 0x00200000 /* In token package */
200 #define OUT_TOKEN_FRAME 0x00100000 /* Out token package */
201 #define SETUP_TOKEN_FRAME 0x00080000 /* Setup token package */
202 #define STALL_FRAME 0x00040000 /* Stall handshake */
203 #define NACK_FRAME 0x00020000 /* Nack handshake */
204 #define NO_PID 0x00010000 /* No send PID */
205 #define NO_CRC 0x00008000 /* No send CRC */
206 #define HOST_COMMAND 0x00004000 /* Host command frame */
207
208 /* Frame status field */
209 /* Receive side */
210 #define FRAME_OK 0x00000000 /* Frame tranmitted or received OK */
211 #define FRAME_ERROR 0x80000000 /* Error occured on frame */
212 #define START_FRAME_LOST 0x40000000 /* START_FRAME_LOST */
213 #define END_FRAME_LOST 0x20000000 /* END_FRAME_LOST */
214 #define RX_ER_NONOCT 0x10000000 /* Rx Non Octet Aligned Packet */
215 #define RX_ER_BITSTUFF 0x08000000 /* Frame Aborted --Received packet
216 with bit stuff error */
217 #define RX_ER_CRC 0x04000000 /* Received packet with CRC error */
218 #define RX_ER_OVERUN 0x02000000 /* Over-run occured on reception */
219 #define RX_ER_PID 0x01000000 /* Wrong PID received */
220 /* Tranmit side */
221 #define TX_ER_NAK 0x00800000 /* Received NAK handshake */
222 #define TX_ER_STALL 0x00400000 /* Received STALL handshake */
223 #define TX_ER_TIMEOUT 0x00200000 /* Transmit time out */
224 #define TX_ER_UNDERUN 0x00100000 /* Transmit underrun */
225 #define FRAME_INPROGRESS 0x00080000 /* Frame is being transmitted */
226 #define ER_DATA_UNDERUN 0x00040000 /* Frame is shorter then expected */
227 #define ER_DATA_OVERUN 0x00020000 /* Frame is longer then expected */
228
229 /* QE USB frame operation functions */
230 #define frame_get_length(frm) (frm->len)
231 #define frame_set_length(frm, leng) (frm->len = leng)
232 #define frame_get_data(frm) (frm->data)
233 #define frame_set_data(frm, dat) (frm->data = dat)
234 #define frame_get_info(frm) (frm->info)
235 #define frame_set_info(frm, inf) (frm->info = inf)
236 #define frame_get_status(frm) (frm->status)
237 #define frame_set_status(frm, stat) (frm->status = stat)
238 #define frame_get_privdata(frm) (frm->privdata)
239 #define frame_set_privdata(frm, dat) (frm->privdata = dat)
240
241 static inline void qe_frame_clean(struct qe_frame *frm)
242 {
243 frame_set_data(frm, NULL);
244 frame_set_length(frm, 0);
245 frame_set_status(frm, FRAME_OK);
246 frame_set_info(frm, 0);
247 frame_set_privdata(frm, NULL);
248 }
249
250 static inline void qe_frame_init(struct qe_frame *frm)
251 {
252 qe_frame_clean(frm);
253 INIT_LIST_HEAD(&(frm->node));
254 }
255
256 struct qe_req {
257 struct usb_request req;
258 struct list_head queue;
259 /* ep_queue() func will add
260 a request->queue into a udc_ep->queue 'd tail */
261 struct qe_ep *ep;
262 unsigned mapped:1;
263 };
264
265 struct qe_ep {
266 struct usb_ep ep;
267 struct list_head queue;
268 struct qe_udc *udc;
269 const struct usb_endpoint_descriptor *desc;
270 struct usb_gadget *gadget;
271
272 u8 state;
273
274 struct qe_bd __iomem *rxbase;
275 struct qe_bd __iomem *n_rxbd;
276 struct qe_bd __iomem *e_rxbd;
277
278 struct qe_bd __iomem *txbase;
279 struct qe_bd __iomem *n_txbd;
280 struct qe_bd __iomem *c_txbd;
281
282 struct qe_frame *rxframe;
283 u8 *rxbuffer;
284 dma_addr_t rxbuf_d;
285 u8 rxbufmap;
286 unsigned char localnack;
287 int has_data;
288
289 struct qe_frame *txframe;
290 struct qe_req *tx_req;
291 int sent; /*data already sent */
292 int last; /*data sent in the last time*/
293
294 u8 dir;
295 u8 epnum;
296 u8 tm; /* transfer mode */
297 u8 data01;
298 u8 init;
299
300 u8 already_seen;
301 u8 enable_tasklet;
302 u8 setup_stage;
303 u32 last_io; /* timestamp */
304
305 char name[14];
306
307 unsigned double_buf:1;
308 unsigned stopped:1;
309 unsigned fnf:1;
310 unsigned has_dma:1;
311
312 u8 ackwait;
313 u8 dma_channel;
314 u16 dma_counter;
315 int lch;
316
317 struct timer_list timer;
318 };
319
320 struct qe_udc {
321 struct usb_gadget gadget;
322 struct usb_gadget_driver *driver;
323 struct device *dev;
324 struct qe_ep eps[USB_MAX_ENDPOINTS];
325 struct usb_ctrlrequest local_setup_buff;
326 spinlock_t lock; /* lock for set/config qe_udc */
327 unsigned long soc_type; /* QE or CPM soc */
328
329 struct qe_req *status_req; /* ep0 status request */
330
331 /* USB and EP Parameter Block pointer */
332 struct usb_device_para __iomem *usb_param;
333 struct usb_ep_para __iomem *ep_param[4];
334
335 u32 max_pipes; /* Device max pipes */
336 u32 max_use_endpts; /* Max endpointes to be used */
337 u32 bus_reset; /* Device is bus reseting */
338 u32 resume_state; /* USB state to resume*/
339 u32 usb_state; /* USB current state */
340 u32 usb_next_state; /* USB next state */
341 u32 ep0_state; /* Enpoint zero state */
342 u32 ep0_dir; /* Enpoint zero direction: can be
343 USB_DIR_IN or USB_DIR_OUT*/
344 u32 usb_sof_count; /* SOF count */
345 u32 errors; /* USB ERRORs count */
346
347 u8 *tmpbuf;
348 u32 c_start;
349 u32 c_end;
350
351 u8 *nullbuf;
352 u8 *statusbuf;
353 dma_addr_t nullp;
354 u8 nullmap;
355 u8 device_address; /* Device USB address */
356
357 unsigned int usb_clock;
358 unsigned int usb_irq;
359 struct usb_ctlr __iomem *usb_regs;
360
361 struct tasklet_struct rx_tasklet;
362
363 struct completion *done; /* to make sure release() is done */
364 };
365
366 #define EP_STATE_IDLE 0
367 #define EP_STATE_NACK 1
368 #define EP_STATE_STALL 2
369
370 /*
371 * transmit BD's status
372 */
373 #define T_R 0x80000000 /* ready bit */
374 #define T_W 0x20000000 /* wrap bit */
375 #define T_I 0x10000000 /* interrupt on completion */
376 #define T_L 0x08000000 /* last */
377 #define T_TC 0x04000000 /* transmit CRC */
378 #define T_CNF 0x02000000 /* wait for transmit confirm */
379 #define T_LSP 0x01000000 /* Low-speed transaction */
380 #define T_PID 0x00c00000 /* packet id */
381 #define T_NAK 0x00100000 /* No ack. */
382 #define T_STAL 0x00080000 /* Stall recieved */
383 #define T_TO 0x00040000 /* time out */
384 #define T_UN 0x00020000 /* underrun */
385
386 #define DEVICE_T_ERROR (T_UN | T_TO)
387 #define HOST_T_ERROR (T_UN | T_TO | T_NAK | T_STAL)
388 #define DEVICE_T_BD_MASK DEVICE_T_ERROR
389 #define HOST_T_BD_MASK HOST_T_ERROR
390
391 #define T_PID_SHIFT 6
392 #define T_PID_DATA0 0x00800000 /* Data 0 toggle */
393 #define T_PID_DATA1 0x00c00000 /* Data 1 toggle */
394
395 /*
396 * receive BD's status
397 */
398 #define R_E 0x80000000 /* buffer empty */
399 #define R_W 0x20000000 /* wrap bit */
400 #define R_I 0x10000000 /* interrupt on reception */
401 #define R_L 0x08000000 /* last */
402 #define R_F 0x04000000 /* first */
403 #define R_PID 0x00c00000 /* packet id */
404 #define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */
405 #define R_AB 0x00080000 /* Frame Aborted */
406 #define R_CR 0x00040000 /* CRC Error */
407 #define R_OV 0x00020000 /* Overrun */
408
409 #define R_ERROR (R_NO | R_AB | R_CR | R_OV)
410 #define R_BD_MASK R_ERROR
411
412 #define R_PID_DATA0 0x00000000
413 #define R_PID_DATA1 0x00400000
414 #define R_PID_SETUP 0x00800000
415
416 #define CPM_USB_STOP_TX 0x2e600000
417 #define CPM_USB_RESTART_TX 0x2e600000
418 #define CPM_USB_STOP_TX_OPCODE 0x0a
419 #define CPM_USB_RESTART_TX_OPCODE 0x0b
420 #define CPM_USB_EP_SHIFT 5
421
422 #ifndef CONFIG_CPM
423 inline int cpm_command(u32 command, u8 opcode)
424 {
425 return -EOPNOTSUPP;
426 }
427 #endif
428
429 #ifndef CONFIG_QUICC_ENGINE
430 inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
431 u32 cmd_input)
432 {
433 return -EOPNOTSUPP;
434 }
435 #endif
436
437 #endif /* __FSL_QE_UDC_H */
438
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