1 /*
2 * amd5536.h -- header for AMD 5536 UDC high/full speed USB device controller
3 *
4 * Copyright (C) 2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #ifndef AMD5536UDC_H
23 #define AMD5536UDC_H
24
25 /* various constants */
26 #define UDC_RDE_TIMER_SECONDS 1
27 #define UDC_RDE_TIMER_DIV 10
28 #define UDC_POLLSTALL_TIMER_USECONDS 500
29
30 /* Hs AMD5536 chip rev. */
31 #define UDC_HSA0_REV 1
32 #define UDC_HSB1_REV 2
33
34 /*
35 * SETUP usb commands
36 * needed, because some SETUP's are handled in hw, but must be passed to
37 * gadget driver above
38 * SET_CONFIG
39 */
40 #define UDC_SETCONFIG_DWORD0 0x00000900
41 #define UDC_SETCONFIG_DWORD0_VALUE_MASK 0xffff0000
42 #define UDC_SETCONFIG_DWORD0_VALUE_OFS 16
43
44 #define UDC_SETCONFIG_DWORD1 0x00000000
45
46 /* SET_INTERFACE */
47 #define UDC_SETINTF_DWORD0 0x00000b00
48 #define UDC_SETINTF_DWORD0_ALT_MASK 0xffff0000
49 #define UDC_SETINTF_DWORD0_ALT_OFS 16
50
51 #define UDC_SETINTF_DWORD1 0x00000000
52 #define UDC_SETINTF_DWORD1_INTF_MASK 0x0000ffff
53 #define UDC_SETINTF_DWORD1_INTF_OFS 0
54
55 /* Mass storage reset */
56 #define UDC_MSCRES_DWORD0 0x0000ff21
57 #define UDC_MSCRES_DWORD1 0x00000000
58
59 /* Global CSR's -------------------------------------------------------------*/
60 #define UDC_CSR_ADDR 0x500
61
62 /* EP NE bits */
63 /* EP number */
64 #define UDC_CSR_NE_NUM_MASK 0x0000000f
65 #define UDC_CSR_NE_NUM_OFS 0
66 /* EP direction */
67 #define UDC_CSR_NE_DIR_MASK 0x00000010
68 #define UDC_CSR_NE_DIR_OFS 4
69 /* EP type */
70 #define UDC_CSR_NE_TYPE_MASK 0x00000060
71 #define UDC_CSR_NE_TYPE_OFS 5
72 /* EP config number */
73 #define UDC_CSR_NE_CFG_MASK 0x00000780
74 #define UDC_CSR_NE_CFG_OFS 7
75 /* EP interface number */
76 #define UDC_CSR_NE_INTF_MASK 0x00007800
77 #define UDC_CSR_NE_INTF_OFS 11
78 /* EP alt setting */
79 #define UDC_CSR_NE_ALT_MASK 0x00078000
80 #define UDC_CSR_NE_ALT_OFS 15
81
82 /* max pkt */
83 #define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000
84 #define UDC_CSR_NE_MAX_PKT_OFS 19
85
86 /* Device Config Register ---------------------------------------------------*/
87 #define UDC_DEVCFG_ADDR 0x400
88
89 #define UDC_DEVCFG_SOFTRESET 31
90 #define UDC_DEVCFG_HNPSFEN 30
91 #define UDC_DEVCFG_DMARST 29
92 #define UDC_DEVCFG_SET_DESC 18
93 #define UDC_DEVCFG_CSR_PRG 17
94 #define UDC_DEVCFG_STATUS 7
95 #define UDC_DEVCFG_DIR 6
96 #define UDC_DEVCFG_PI 5
97 #define UDC_DEVCFG_SS 4
98 #define UDC_DEVCFG_SP 3
99 #define UDC_DEVCFG_RWKP 2
100
101 #define UDC_DEVCFG_SPD_MASK 0x3
102 #define UDC_DEVCFG_SPD_OFS 0
103 #define UDC_DEVCFG_SPD_HS 0x0
104 #define UDC_DEVCFG_SPD_FS 0x1
105 #define UDC_DEVCFG_SPD_LS 0x2
106 /*#define UDC_DEVCFG_SPD_FS 0x3*/
107
108
109 /* Device Control Register --------------------------------------------------*/
110 #define UDC_DEVCTL_ADDR 0x404
111
112 #define UDC_DEVCTL_THLEN_MASK 0xff000000
113 #define UDC_DEVCTL_THLEN_OFS 24
114
115 #define UDC_DEVCTL_BRLEN_MASK 0x00ff0000
116 #define UDC_DEVCTL_BRLEN_OFS 16
117
118 #define UDC_DEVCTL_CSR_DONE 13
119 #define UDC_DEVCTL_DEVNAK 12
120 #define UDC_DEVCTL_SD 10
121 #define UDC_DEVCTL_MODE 9
122 #define UDC_DEVCTL_BREN 8
123 #define UDC_DEVCTL_THE 7
124 #define UDC_DEVCTL_BF 6
125 #define UDC_DEVCTL_BE 5
126 #define UDC_DEVCTL_DU 4
127 #define UDC_DEVCTL_TDE 3
128 #define UDC_DEVCTL_RDE 2
129 #define UDC_DEVCTL_RES 0
130
131
132 /* Device Status Register ---------------------------------------------------*/
133 #define UDC_DEVSTS_ADDR 0x408
134
135 #define UDC_DEVSTS_TS_MASK 0xfffc0000
136 #define UDC_DEVSTS_TS_OFS 18
137
138 #define UDC_DEVSTS_SESSVLD 17
139 #define UDC_DEVSTS_PHY_ERROR 16
140 #define UDC_DEVSTS_RXFIFO_EMPTY 15
141
142 #define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000
143 #define UDC_DEVSTS_ENUM_SPEED_OFS 13
144 #define UDC_DEVSTS_ENUM_SPEED_FULL 1
145 #define UDC_DEVSTS_ENUM_SPEED_HIGH 0
146
147 #define UDC_DEVSTS_SUSP 12
148
149 #define UDC_DEVSTS_ALT_MASK 0x00000f00
150 #define UDC_DEVSTS_ALT_OFS 8
151
152 #define UDC_DEVSTS_INTF_MASK 0x000000f0
153 #define UDC_DEVSTS_INTF_OFS 4
154
155 #define UDC_DEVSTS_CFG_MASK 0x0000000f
156 #define UDC_DEVSTS_CFG_OFS 0
157
158
159 /* Device Interrupt Register ------------------------------------------------*/
160 #define UDC_DEVINT_ADDR 0x40c
161
162 #define UDC_DEVINT_SVC 7
163 #define UDC_DEVINT_ENUM 6
164 #define UDC_DEVINT_SOF 5
165 #define UDC_DEVINT_US 4
166 #define UDC_DEVINT_UR 3
167 #define UDC_DEVINT_ES 2
168 #define UDC_DEVINT_SI 1
169 #define UDC_DEVINT_SC 0
170
171 /* Device Interrupt Mask Register -------------------------------------------*/
172 #define UDC_DEVINT_MSK_ADDR 0x410
173
174 #define UDC_DEVINT_MSK 0x7f
175
176 /* Endpoint Interrupt Register ----------------------------------------------*/
177 #define UDC_EPINT_ADDR 0x414
178
179 #define UDC_EPINT_OUT_MASK 0xffff0000
180 #define UDC_EPINT_OUT_OFS 16
181 #define UDC_EPINT_IN_MASK 0x0000ffff
182 #define UDC_EPINT_IN_OFS 0
183
184 #define UDC_EPINT_IN_EP0 0
185 #define UDC_EPINT_IN_EP1 1
186 #define UDC_EPINT_IN_EP2 2
187 #define UDC_EPINT_IN_EP3 3
188 #define UDC_EPINT_OUT_EP0 16
189 #define UDC_EPINT_OUT_EP1 17
190 #define UDC_EPINT_OUT_EP2 18
191 #define UDC_EPINT_OUT_EP3 19
192
193 #define UDC_EPINT_EP0_ENABLE_MSK 0x001e001e
194
195 /* Endpoint Interrupt Mask Register -----------------------------------------*/
196 #define UDC_EPINT_MSK_ADDR 0x418
197
198 #define UDC_EPINT_OUT_MSK_MASK 0xffff0000
199 #define UDC_EPINT_OUT_MSK_OFS 16
200 #define UDC_EPINT_IN_MSK_MASK 0x0000ffff
201 #define UDC_EPINT_IN_MSK_OFS 0
202
203 #define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff
204 /* mask non-EP0 endpoints */
205 #define UDC_EPDATAINT_MSK_DISABLE 0xfffefffe
206 /* mask all dev interrupts */
207 #define UDC_DEV_MSK_DISABLE 0x7f
208
209 /* Endpoint-specific CSR's --------------------------------------------------*/
210 #define UDC_EPREGS_ADDR 0x0
211 #define UDC_EPIN_REGS_ADDR 0x0
212 #define UDC_EPOUT_REGS_ADDR 0x200
213
214 #define UDC_EPCTL_ADDR 0x0
215
216 #define UDC_EPCTL_RRDY 9
217 #define UDC_EPCTL_CNAK 8
218 #define UDC_EPCTL_SNAK 7
219 #define UDC_EPCTL_NAK 6
220
221 #define UDC_EPCTL_ET_MASK 0x00000030
222 #define UDC_EPCTL_ET_OFS 4
223 #define UDC_EPCTL_ET_CONTROL 0
224 #define UDC_EPCTL_ET_ISO 1
225 #define UDC_EPCTL_ET_BULK 2
226 #define UDC_EPCTL_ET_INTERRUPT 3
227
228 #define UDC_EPCTL_P 3
229 #define UDC_EPCTL_SN 2
230 #define UDC_EPCTL_F 1
231 #define UDC_EPCTL_S 0
232
233 /* Endpoint Status Registers ------------------------------------------------*/
234 #define UDC_EPSTS_ADDR 0x4
235
236 #define UDC_EPSTS_RX_PKT_SIZE_MASK 0x007ff800
237 #define UDC_EPSTS_RX_PKT_SIZE_OFS 11
238
239 #define UDC_EPSTS_TDC 10
240 #define UDC_EPSTS_HE 9
241 #define UDC_EPSTS_BNA 7
242 #define UDC_EPSTS_IN 6
243
244 #define UDC_EPSTS_OUT_MASK 0x00000030
245 #define UDC_EPSTS_OUT_OFS 4
246 #define UDC_EPSTS_OUT_DATA 1
247 #define UDC_EPSTS_OUT_DATA_CLEAR 0x10
248 #define UDC_EPSTS_OUT_SETUP 2
249 #define UDC_EPSTS_OUT_SETUP_CLEAR 0x20
250 #define UDC_EPSTS_OUT_CLEAR 0x30
251
252 /* Endpoint Buffer Size IN/ Receive Packet Frame Number OUT Registers ------*/
253 #define UDC_EPIN_BUFF_SIZE_ADDR 0x8
254 #define UDC_EPOUT_FRAME_NUMBER_ADDR 0x8
255
256 #define UDC_EPIN_BUFF_SIZE_MASK 0x0000ffff
257 #define UDC_EPIN_BUFF_SIZE_OFS 0
258 /* EP0in txfifo = 128 bytes*/
259 #define UDC_EPIN0_BUFF_SIZE 32
260 /* EP0in fullspeed txfifo = 128 bytes*/
261 #define UDC_FS_EPIN0_BUFF_SIZE 32
262
263 /* fifo size mult = fifo size / max packet */
264 #define UDC_EPIN_BUFF_SIZE_MULT 2
265
266 /* EPin data fifo size = 1024 bytes DOUBLE BUFFERING */
267 #define UDC_EPIN_BUFF_SIZE 256
268 /* EPin small INT data fifo size = 128 bytes */
269 #define UDC_EPIN_SMALLINT_BUFF_SIZE 32
270
271 /* EPin fullspeed data fifo size = 128 bytes DOUBLE BUFFERING */
272 #define UDC_FS_EPIN_BUFF_SIZE 32
273
274 #define UDC_EPOUT_FRAME_NUMBER_MASK 0x0000ffff
275 #define UDC_EPOUT_FRAME_NUMBER_OFS 0
276
277 /* Endpoint Buffer Size OUT/Max Packet Size Registers -----------------------*/
278 #define UDC_EPOUT_BUFF_SIZE_ADDR 0x0c
279 #define UDC_EP_MAX_PKT_SIZE_ADDR 0x0c
280
281 #define UDC_EPOUT_BUFF_SIZE_MASK 0xffff0000
282 #define UDC_EPOUT_BUFF_SIZE_OFS 16
283 #define UDC_EP_MAX_PKT_SIZE_MASK 0x0000ffff
284 #define UDC_EP_MAX_PKT_SIZE_OFS 0
285 /* EP0in max packet size = 64 bytes */
286 #define UDC_EP0IN_MAX_PKT_SIZE 64
287 /* EP0out max packet size = 64 bytes */
288 #define UDC_EP0OUT_MAX_PKT_SIZE 64
289 /* EP0in fullspeed max packet size = 64 bytes */
290 #define UDC_FS_EP0IN_MAX_PKT_SIZE 64
291 /* EP0out fullspeed max packet size = 64 bytes */
292 #define UDC_FS_EP0OUT_MAX_PKT_SIZE 64
293
294 /*
295 * Endpoint dma descriptors ------------------------------------------------
296 *
297 * Setup data, Status dword
298 */
299 #define UDC_DMA_STP_STS_CFG_MASK 0x0fff0000
300 #define UDC_DMA_STP_STS_CFG_OFS 16
301 #define UDC_DMA_STP_STS_CFG_ALT_MASK 0x000f0000
302 #define UDC_DMA_STP_STS_CFG_ALT_OFS 16
303 #define UDC_DMA_STP_STS_CFG_INTF_MASK 0x00f00000
304 #define UDC_DMA_STP_STS_CFG_INTF_OFS 20
305 #define UDC_DMA_STP_STS_CFG_NUM_MASK 0x0f000000
306 #define UDC_DMA_STP_STS_CFG_NUM_OFS 24
307 #define UDC_DMA_STP_STS_RX_MASK 0x30000000
308 #define UDC_DMA_STP_STS_RX_OFS 28
309 #define UDC_DMA_STP_STS_BS_MASK 0xc0000000
310 #define UDC_DMA_STP_STS_BS_OFS 30
311 #define UDC_DMA_STP_STS_BS_HOST_READY 0
312 #define UDC_DMA_STP_STS_BS_DMA_BUSY 1
313 #define UDC_DMA_STP_STS_BS_DMA_DONE 2
314 #define UDC_DMA_STP_STS_BS_HOST_BUSY 3
315 /* IN data, Status dword */
316 #define UDC_DMA_IN_STS_TXBYTES_MASK 0x0000ffff
317 #define UDC_DMA_IN_STS_TXBYTES_OFS 0
318 #define UDC_DMA_IN_STS_FRAMENUM_MASK 0x07ff0000
319 #define UDC_DMA_IN_STS_FRAMENUM_OFS 0
320 #define UDC_DMA_IN_STS_L 27
321 #define UDC_DMA_IN_STS_TX_MASK 0x30000000
322 #define UDC_DMA_IN_STS_TX_OFS 28
323 #define UDC_DMA_IN_STS_BS_MASK 0xc0000000
324 #define UDC_DMA_IN_STS_BS_OFS 30
325 #define UDC_DMA_IN_STS_BS_HOST_READY 0
326 #define UDC_DMA_IN_STS_BS_DMA_BUSY 1
327 #define UDC_DMA_IN_STS_BS_DMA_DONE 2
328 #define UDC_DMA_IN_STS_BS_HOST_BUSY 3
329 /* OUT data, Status dword */
330 #define UDC_DMA_OUT_STS_RXBYTES_MASK 0x0000ffff
331 #define UDC_DMA_OUT_STS_RXBYTES_OFS 0
332 #define UDC_DMA_OUT_STS_FRAMENUM_MASK 0x07ff0000
333 #define UDC_DMA_OUT_STS_FRAMENUM_OFS 0
334 #define UDC_DMA_OUT_STS_L 27
335 #define UDC_DMA_OUT_STS_RX_MASK 0x30000000
336 #define UDC_DMA_OUT_STS_RX_OFS 28
337 #define UDC_DMA_OUT_STS_BS_MASK 0xc0000000
338 #define UDC_DMA_OUT_STS_BS_OFS 30
339 #define UDC_DMA_OUT_STS_BS_HOST_READY 0
340 #define UDC_DMA_OUT_STS_BS_DMA_BUSY 1
341 #define UDC_DMA_OUT_STS_BS_DMA_DONE 2
342 #define UDC_DMA_OUT_STS_BS_HOST_BUSY 3
343 /* max ep0in packet */
344 #define UDC_EP0IN_MAXPACKET 1000
345 /* max dma packet */
346 #define UDC_DMA_MAXPACKET 65536
347
348 /* un-usable DMA address */
349 #define DMA_DONT_USE (~(dma_addr_t) 0 )
350
351 /* other Endpoint register addresses and values-----------------------------*/
352 #define UDC_EP_SUBPTR_ADDR 0x10
353 #define UDC_EP_DESPTR_ADDR 0x14
354 #define UDC_EP_WRITE_CONFIRM_ADDR 0x1c
355
356 /* EP number as layouted in AHB space */
357 #define UDC_EP_NUM 32
358 #define UDC_EPIN_NUM 16
359 #define UDC_EPIN_NUM_USED 5
360 #define UDC_EPOUT_NUM 16
361 /* EP number of EP's really used = EP0 + 8 data EP's */
362 #define UDC_USED_EP_NUM 9
363 /* UDC CSR regs are aligned but AHB regs not - offset for OUT EP's */
364 #define UDC_CSR_EP_OUT_IX_OFS 12
365
366 #define UDC_EP0OUT_IX 16
367 #define UDC_EP0IN_IX 0
368
369 /* Rx fifo address and size = 1k -------------------------------------------*/
370 #define UDC_RXFIFO_ADDR 0x800
371 #define UDC_RXFIFO_SIZE 0x400
372
373 /* Tx fifo address and size = 1.5k -----------------------------------------*/
374 #define UDC_TXFIFO_ADDR 0xc00
375 #define UDC_TXFIFO_SIZE 0x600
376
377 /* default data endpoints --------------------------------------------------*/
378 #define UDC_EPIN_STATUS_IX 1
379 #define UDC_EPIN_IX 2
380 #define UDC_EPOUT_IX 18
381
382 /* general constants -------------------------------------------------------*/
383 #define UDC_DWORD_BYTES 4
384 #define UDC_BITS_PER_BYTE_SHIFT 3
385 #define UDC_BYTE_MASK 0xff
386 #define UDC_BITS_PER_BYTE 8
387
388 /*---------------------------------------------------------------------------*/
389 /* UDC CSR's */
390 struct udc_csrs {
391
392 /* sca - setup command address */
393 u32 sca;
394
395 /* ep ne's */
396 u32 ne[UDC_USED_EP_NUM];
397 } __attribute__ ((packed));
398
399 /* AHB subsystem CSR registers */
400 struct udc_regs {
401
402 /* device configuration */
403 u32 cfg;
404
405 /* device control */
406 u32 ctl;
407
408 /* device status */
409 u32 sts;
410
411 /* device interrupt */
412 u32 irqsts;
413
414 /* device interrupt mask */
415 u32 irqmsk;
416
417 /* endpoint interrupt */
418 u32 ep_irqsts;
419
420 /* endpoint interrupt mask */
421 u32 ep_irqmsk;
422 } __attribute__ ((packed));
423
424 /* endpoint specific registers */
425 struct udc_ep_regs {
426
427 /* endpoint control */
428 u32 ctl;
429
430 /* endpoint status */
431 u32 sts;
432
433 /* endpoint buffer size in/ receive packet frame number out */
434 u32 bufin_framenum;
435
436 /* endpoint buffer size out/max packet size */
437 u32 bufout_maxpkt;
438
439 /* endpoint setup buffer pointer */
440 u32 subptr;
441
442 /* endpoint data descriptor pointer */
443 u32 desptr;
444
445 /* reserverd */
446 u32 reserved;
447
448 /* write/read confirmation */
449 u32 confirm;
450
451 } __attribute__ ((packed));
452
453 /* control data DMA desc */
454 struct udc_stp_dma {
455 /* status quadlet */
456 u32 status;
457 /* reserved */
458 u32 _reserved;
459 /* first setup word */
460 u32 data12;
461 /* second setup word */
462 u32 data34;
463 } __attribute__ ((aligned (16)));
464
465 /* normal data DMA desc */
466 struct udc_data_dma {
467 /* status quadlet */
468 u32 status;
469 /* reserved */
470 u32 _reserved;
471 /* buffer pointer */
472 u32 bufptr;
473 /* next descriptor pointer */
474 u32 next;
475 } __attribute__ ((aligned (16)));
476
477 /* request packet */
478 struct udc_request {
479 /* embedded gadget ep */
480 struct usb_request req;
481
482 /* flags */
483 unsigned dma_going : 1,
484 dma_mapping : 1,
485 dma_done : 1;
486 /* phys. address */
487 dma_addr_t td_phys;
488 /* first dma desc. of chain */
489 struct udc_data_dma *td_data;
490 /* last dma desc. of chain */
491 struct udc_data_dma *td_data_last;
492 struct list_head queue;
493
494 /* chain length */
495 unsigned chain_len;
496
497 };
498
499 /* UDC specific endpoint parameters */
500 struct udc_ep {
501 struct usb_ep ep;
502 struct udc_ep_regs __iomem *regs;
503 u32 __iomem *txfifo;
504 u32 __iomem *dma;
505 dma_addr_t td_phys;
506 dma_addr_t td_stp_dma;
507 struct udc_stp_dma *td_stp;
508 struct udc_data_dma *td;
509 /* temp request */
510 struct udc_request *req;
511 unsigned req_used;
512 unsigned req_completed;
513 /* dummy DMA desc for BNA dummy */
514 struct udc_request *bna_dummy_req;
515 unsigned bna_occurred;
516
517 /* NAK state */
518 unsigned naking;
519
520 struct udc *dev;
521
522 /* queue for requests */
523 struct list_head queue;
524 const struct usb_endpoint_descriptor *desc;
525 unsigned halted;
526 unsigned cancel_transfer;
527 unsigned num : 5,
528 fifo_depth : 14,
529 in : 1;
530 };
531
532 /* device struct */
533 struct udc {
534 struct usb_gadget gadget;
535 spinlock_t lock; /* protects all state */
536 /* all endpoints */
537 struct udc_ep ep[UDC_EP_NUM];
538 struct usb_gadget_driver *driver;
539 /* operational flags */
540 unsigned active : 1,
541 stall_ep0in : 1,
542 waiting_zlp_ack_ep0in : 1,
543 set_cfg_not_acked : 1,
544 irq_registered : 1,
545 data_ep_enabled : 1,
546 data_ep_queued : 1,
547 mem_region : 1,
548 sys_suspended : 1,
549 connected;
550
551 u16 chiprev;
552
553 /* registers */
554 struct pci_dev *pdev;
555 struct udc_csrs __iomem *csr;
556 struct udc_regs __iomem *regs;
557 struct udc_ep_regs __iomem *ep_regs;
558 u32 __iomem *rxfifo;
559 u32 __iomem *txfifo;
560
561 /* DMA desc pools */
562 struct pci_pool *data_requests;
563 struct pci_pool *stp_requests;
564
565 /* device data */
566 unsigned long phys_addr;
567 void __iomem *virt_addr;
568 unsigned irq;
569
570 /* states */
571 u16 cur_config;
572 u16 cur_intf;
573 u16 cur_alt;
574 };
575
576 /* setup request data */
577 union udc_setup_data {
578 u32 data[2];
579 struct usb_ctrlrequest request;
580 };
581
582 /*
583 *---------------------------------------------------------------------------
584 * SET and GET bitfields in u32 values
585 * via constants for mask/offset:
586 * <bit_field_stub_name> is the text between
587 * UDC_ and _MASK|_OFS of appropiate
588 * constant
589 *
590 * set bitfield value in u32 u32Val
591 */
592 #define AMD_ADDBITS(u32Val, bitfield_val, bitfield_stub_name) \
593 (((u32Val) & (((u32) ~((u32) bitfield_stub_name##_MASK)))) \
594 | (((bitfield_val) << ((u32) bitfield_stub_name##_OFS)) \
595 & ((u32) bitfield_stub_name##_MASK)))
596
597 /*
598 * set bitfield value in zero-initialized u32 u32Val
599 * => bitfield bits in u32Val are all zero
600 */
601 #define AMD_INIT_SETBITS(u32Val, bitfield_val, bitfield_stub_name) \
602 ((u32Val) \
603 | (((bitfield_val) << ((u32) bitfield_stub_name##_OFS)) \
604 & ((u32) bitfield_stub_name##_MASK)))
605
606 /* get bitfield value from u32 u32Val */
607 #define AMD_GETBITS(u32Val, bitfield_stub_name) \
608 ((u32Val & ((u32) bitfield_stub_name##_MASK)) \
609 >> ((u32) bitfield_stub_name##_OFS))
610
611 /* SET and GET bits in u32 values ------------------------------------------*/
612 #define AMD_BIT(bit_stub_name) (1 << bit_stub_name)
613 #define AMD_UNMASK_BIT(bit_stub_name) (~AMD_BIT(bit_stub_name))
614 #define AMD_CLEAR_BIT(bit_stub_name) (~AMD_BIT(bit_stub_name))
615
616 /* debug macros ------------------------------------------------------------*/
617
618 #define DBG(udc , args...) dev_dbg(&(udc)->pdev->dev, args)
619
620 #ifdef UDC_VERBOSE
621 #define VDBG DBG
622 #else
623 #define VDBG(udc , args...) do {} while (0)
624 #endif
625
626 #endif /* #ifdef AMD5536UDC_H */
627
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