1 /*
2 * drivers/tc/zs.h: Definitions for the DECstation Z85C30 serial driver.
3 *
4 * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras.
5 * Adapted from drivers/macintosh/macserial.h by Harald Koerfgen.
6 *
7 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
8 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
9 * Copyright (C) 2004 Maciej W. Rozycki
10 */
11 #ifndef _DECSERIAL_H
12 #define _DECSERIAL_H
13
14 #include <asm/dec/serial.h>
15
16 #define NUM_ZSREGS 16
17
18 struct serial_struct {
19 int type;
20 int line;
21 int port;
22 int irq;
23 int flags;
24 int xmit_fifo_size;
25 int custom_divisor;
26 int baud_base;
27 unsigned short close_delay;
28 char reserved_char[2];
29 int hub6;
30 unsigned short closing_wait; /* time to wait before closing */
31 unsigned short closing_wait2; /* no longer used... */
32 int reserved[4];
33 };
34
35 /*
36 * For the close wait times, 0 means wait forever for serial port to
37 * flush its output. 65535 means don't wait at all.
38 */
39 #define ZILOG_CLOSING_WAIT_INF 0
40 #define ZILOG_CLOSING_WAIT_NONE 65535
41
42 /*
43 * Definitions for ZILOG_struct (and serial_struct) flags field
44 */
45 #define ZILOG_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes
46 on the callout port */
47 #define ZILOG_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */
48 #define ZILOG_SAK 0x0004 /* Secure Attention Key (Orange book) */
49 #define ZILOG_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */
50
51 #define ZILOG_SPD_MASK 0x0030
52 #define ZILOG_SPD_HI 0x0010 /* Use 56000 instead of 38400 bps */
53
54 #define ZILOG_SPD_VHI 0x0020 /* Use 115200 instead of 38400 bps */
55 #define ZILOG_SPD_CUST 0x0030 /* Use user-specified divisor */
56
57 #define ZILOG_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */
58 #define ZILOG_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */
59 #define ZILOG_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */
60 #define ZILOG_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */
61 #define ZILOG_CALLOUT_NOHUP 0x0400 /* Don't do hangups for cua device */
62
63 #define ZILOG_FLAGS 0x0FFF /* Possible legal ZILOG flags */
64 #define ZILOG_USR_MASK 0x0430 /* Legal flags that non-privileged
65 * users can set or reset */
66
67 /* Internal flags used only by kernel/chr_drv/serial.c */
68 #define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */
69 #define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */
70 #define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */
71 #define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */
72 #define ZILOG_CLOSING 0x08000000 /* Serial port is closing */
73 #define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */
74 #define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */
75
76 /* Software state per channel */
77
78 #ifdef __KERNEL__
79 /*
80 * This is our internal structure for each serial port's state.
81 *
82 * Many fields are paralleled by the structure used by the serial_struct
83 * structure.
84 *
85 * For definitions of the flags field, see tty.h
86 */
87
88 struct dec_zschannel {
89 volatile unsigned char *control;
90 volatile unsigned char *data;
91
92 /* Current write register values */
93 unsigned char curregs[NUM_ZSREGS];
94 };
95
96 struct dec_serial {
97 struct dec_serial *zs_next; /* For IRQ servicing chain. */
98 struct dec_zschannel *zs_channel; /* Channel registers. */
99 struct dec_zschannel *zs_chan_a; /* A side registers. */
100 unsigned char read_reg_zero;
101
102 struct dec_serial_hook *hook; /* Hook on this channel. */
103 int tty_break; /* Set on BREAK condition. */
104 int is_cons; /* Is this our console. */
105 int tx_active; /* Char is being xmitted. */
106 int tx_stopped; /* Output is suspended. */
107
108 /*
109 * We need to know the current clock divisor
110 * to read the bps rate the chip has currently loaded.
111 */
112 int clk_divisor; /* May be 1, 16, 32, or 64. */
113 int zs_baud;
114
115 char change_needed;
116
117 int magic;
118 int baud_base;
119 int port;
120 int irq;
121 int flags; /* Defined in tty.h. */
122 int type; /* UART type. */
123 struct tty_struct *tty;
124 int read_status_mask;
125 int ignore_status_mask;
126 int timeout;
127 int xmit_fifo_size;
128 int custom_divisor;
129 int x_char; /* XON/XOFF character. */
130 int close_delay;
131 unsigned short closing_wait;
132 unsigned short closing_wait2;
133 unsigned long event;
134 unsigned long last_active;
135 int line;
136 int count; /* # of fds on device. */
137 int blocked_open; /* # of blocked opens. */
138 unsigned char *xmit_buf;
139 int xmit_head;
140 int xmit_tail;
141 int xmit_cnt;
142 struct tq_struct tqueue;
143 struct tq_struct tqueue_hangup;
144 wait_queue_head_t open_wait;
145 wait_queue_head_t close_wait;
146 };
147
148
149 #define SERIAL_MAGIC 0x5301
150
151 /*
152 * The size of the serial xmit buffer is 1 page, or 4096 bytes
153 */
154 #define SERIAL_XMIT_SIZE 4096
155
156 /*
157 * Events are used to schedule things to happen at timer-interrupt
158 * time, instead of at rs interrupt time.
159 */
160 #define RS_EVENT_WRITE_WAKEUP 0
161
162 #endif /* __KERNEL__ */
163
164 /* Conversion routines to/from brg time constants from/to bits
165 * per second.
166 */
167 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
168 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
169
170 /* The Zilog register set */
171
172 #define FLAG 0x7e
173
174 /* Write Register 0 */
175 #define R0 0 /* Register selects */
176 #define R1 1
177 #define R2 2
178 #define R3 3
179 #define R4 4
180 #define R5 5
181 #define R6 6
182 #define R7 7
183 #define R8 8
184 #define R9 9
185 #define R10 10
186 #define R11 11
187 #define R12 12
188 #define R13 13
189 #define R14 14
190 #define R15 15
191
192 #define NULLCODE 0 /* Null Code */
193 #define POINT_HIGH 0x8 /* Select upper half of registers */
194 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
195 #define SEND_ABORT 0x18 /* HDLC Abort */
196 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
197 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
198 #define ERR_RES 0x30 /* Error Reset */
199 #define RES_H_IUS 0x38 /* Reset highest IUS */
200
201 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
202 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
203 #define RES_EOM_L 0xC0 /* Reset EOM latch */
204
205 /* Write Register 1 */
206
207 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
208 #define TxINT_ENAB 0x2 /* Tx Int Enable */
209 #define PAR_SPEC 0x4 /* Parity is special condition */
210
211 #define RxINT_DISAB 0 /* Rx Int Disable */
212 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
213 #define RxINT_ALL 0x10 /* Int on all Rx Characters or error */
214 #define RxINT_ERR 0x18 /* Int on error only */
215 #define RxINT_MASK 0x18
216
217 #define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
218 #define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
219 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
220
221 /* Write Register #2 (Interrupt Vector) */
222
223 /* Write Register 3 */
224
225 #define RxENABLE 0x1 /* Rx Enable */
226 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
227 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
228 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
229 #define ENT_HM 0x10 /* Enter Hunt Mode */
230 #define AUTO_ENAB 0x20 /* Auto Enables */
231 #define Rx5 0x0 /* Rx 5 Bits/Character */
232 #define Rx7 0x40 /* Rx 7 Bits/Character */
233 #define Rx6 0x80 /* Rx 6 Bits/Character */
234 #define Rx8 0xc0 /* Rx 8 Bits/Character */
235 #define RxNBITS_MASK 0xc0
236
237 /* Write Register 4 */
238
239 #define PAR_ENA 0x1 /* Parity Enable */
240 #define PAR_EVEN 0x2 /* Parity Even/Odd* */
241
242 #define SYNC_ENAB 0 /* Sync Modes Enable */
243 #define SB1 0x4 /* 1 stop bit/char */
244 #define SB15 0x8 /* 1.5 stop bits/char */
245 #define SB2 0xc /* 2 stop bits/char */
246 #define SB_MASK 0xc
247
248 #define MONSYNC 0 /* 8 Bit Sync character */
249 #define BISYNC 0x10 /* 16 bit sync character */
250 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
251 #define EXTSYNC 0x30 /* External Sync Mode */
252
253 #define X1CLK 0x0 /* x1 clock mode */
254 #define X16CLK 0x40 /* x16 clock mode */
255 #define X32CLK 0x80 /* x32 clock mode */
256 #define X64CLK 0xC0 /* x64 clock mode */
257 #define XCLK_MASK 0xC0
258
259 /* Write Register 5 */
260
261 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
262 #define RTS 0x2 /* RTS */
263 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
264 #define TxENAB 0x8 /* Tx Enable */
265 #define SND_BRK 0x10 /* Send Break */
266 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
267 #define Tx7 0x20 /* Tx 7 bits/character */
268 #define Tx6 0x40 /* Tx 6 bits/character */
269 #define Tx8 0x60 /* Tx 8 bits/character */
270 #define TxNBITS_MASK 0x60
271 #define DTR 0x80 /* DTR */
272
273 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
274
275 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
276
277 /* Write Register 8 (transmit buffer) */
278
279 /* Write Register 9 (Master interrupt control) */
280 #define VIS 1 /* Vector Includes Status */
281 #define NV 2 /* No Vector */
282 #define DLC 4 /* Disable Lower Chain */
283 #define MIE 8 /* Master Interrupt Enable */
284 #define STATHI 0x10 /* Status high */
285 #define SOFTACK 0x20 /* Software Interrupt Acknowledge */
286 #define NORESET 0 /* No reset on write to R9 */
287 #define CHRB 0x40 /* Reset channel B */
288 #define CHRA 0x80 /* Reset channel A */
289 #define FHWRES 0xc0 /* Force hardware reset */
290
291 /* Write Register 10 (misc control bits) */
292 #define BIT6 1 /* 6 bit/8bit sync */
293 #define LOOPMODE 2 /* SDLC Loop mode */
294 #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
295 #define MARKIDLE 8 /* Mark/flag on idle */
296 #define GAOP 0x10 /* Go active on poll */
297 #define NRZ 0 /* NRZ mode */
298 #define NRZI 0x20 /* NRZI mode */
299 #define FM1 0x40 /* FM1 (transition = 1) */
300 #define FM0 0x60 /* FM0 (transition = 0) */
301 #define CRCPS 0x80 /* CRC Preset I/O */
302
303 /* Write Register 11 (Clock Mode control) */
304 #define TRxCXT 0 /* TRxC = Xtal output */
305 #define TRxCTC 1 /* TRxC = Transmit clock */
306 #define TRxCBR 2 /* TRxC = BR Generator Output */
307 #define TRxCDP 3 /* TRxC = DPLL output */
308 #define TRxCOI 4 /* TRxC O/I */
309 #define TCRTxCP 0 /* Transmit clock = RTxC pin */
310 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
311 #define TCBR 0x10 /* Transmit clock = BR Generator output */
312 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
313 #define RCRTxCP 0 /* Receive clock = RTxC pin */
314 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
315 #define RCBR 0x40 /* Receive clock = BR Generator output */
316 #define RCDPLL 0x60 /* Receive clock = DPLL output */
317 #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
318
319 /* Write Register 12 (lower byte of baud rate generator time constant) */
320
321 /* Write Register 13 (upper byte of baud rate generator time constant) */
322
323 /* Write Register 14 (Misc control bits) */
324 #define BRENABL 1 /* Baud rate generator enable */
325 #define BRSRC 2 /* Baud rate generator source */
326 #define DTRREQ 4 /* DTR/Request function */
327 #define AUTOECHO 8 /* Auto Echo */
328 #define LOOPBAK 0x10 /* Local loopback */
329 #define SEARCH 0x20 /* Enter search mode */
330 #define RMC 0x40 /* Reset missing clock */
331 #define DISDPLL 0x60 /* Disable DPLL */
332 #define SSBR 0x80 /* Set DPLL source = BR generator */
333 #define SSRTxC 0xa0 /* Set DPLL source = RTxC */
334 #define SFMM 0xc0 /* Set FM mode */
335 #define SNRZI 0xe0 /* Set NRZI mode */
336
337 /* Write Register 15 (external/status interrupt control) */
338 #define ZCIE 2 /* Zero count IE */
339 #define DCDIE 8 /* DCD IE */
340 #define SYNCIE 0x10 /* Sync/hunt IE */
341 #define CTSIE 0x20 /* CTS IE */
342 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
343 #define BRKIE 0x80 /* Break/Abort IE */
344
345
346 /* Read Register 0 */
347 #define Rx_CH_AV 0x1 /* Rx Character Available */
348 #define ZCOUNT 0x2 /* Zero count */
349 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
350 #define DCD 0x8 /* DCD */
351 #define SYNC_HUNT 0x10 /* Sync/hunt */
352 #define CTS 0x20 /* CTS */
353 #define TxEOM 0x40 /* Tx underrun */
354 #define BRK_ABRT 0x80 /* Break/Abort */
355
356 /* Read Register 1 */
357 #define ALL_SNT 0x1 /* All sent */
358 /* Residue Data for 8 Rx bits/char programmed */
359 #define RES3 0x8 /* 0/3 */
360 #define RES4 0x4 /* 0/4 */
361 #define RES5 0xc /* 0/5 */
362 #define RES6 0x2 /* 0/6 */
363 #define RES7 0xa /* 0/7 */
364 #define RES8 0x6 /* 0/8 */
365 #define RES18 0xe /* 1/8 */
366 #define RES28 0x0 /* 2/8 */
367 /* Special Rx Condition Interrupts */
368 #define PAR_ERR 0x10 /* Parity error */
369 #define Rx_OVR 0x20 /* Rx Overrun Error */
370 #define FRM_ERR 0x40 /* CRC/Framing Error */
371 #define END_FR 0x80 /* End of Frame (SDLC) */
372
373 /* Read Register 2 (channel b only) - Interrupt vector */
374
375 /* Read Register 3 (interrupt pending register) ch a only */
376 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
377 #define CHBTxIP 0x2 /* Channel B Tx IP */
378 #define CHBRxIP 0x4 /* Channel B Rx IP */
379 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
380 #define CHATxIP 0x10 /* Channel A Tx IP */
381 #define CHARxIP 0x20 /* Channel A Rx IP */
382
383 /* Read Register 8 (receive data register) */
384
385 /* Read Register 10 (misc status bits) */
386 #define ONLOOP 2 /* On loop */
387 #define LOOPSEND 0x10 /* Loop sending */
388 #define CLK2MIS 0x40 /* Two clocks missing */
389 #define CLK1MIS 0x80 /* One clock missing */
390
391 /* Read Register 12 (lower byte of baud rate generator constant) */
392
393 /* Read Register 13 (upper byte of baud rate generator constant) */
394
395 /* Read Register 15 (value of WR 15) */
396
397 /* Misc macros */
398 #define ZS_CLEARERR(channel) (write_zsreg(channel, 0, ERR_RES))
399 #define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \
400 garbage = read_zsdata(channel); \
401 garbage = read_zsdata(channel); \
402 garbage = read_zsdata(channel); \
403 } while(0)
404
405 #endif /* !(_DECSERIAL_H) */
406
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