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Version: [ 2.6.11.8 ] [ 2.6.25 ] [ 2.6.25.8 ] [ 2.6.31.13 ] Architecture: [ i386 ]
  1 /*****************************************************************************
  2  *      Copyright(c) 2007,  RealTEK Technology Inc. All Right Reserved.
  3  *
  4  * Module:              Hal819xUsbDM.h  (RTL8192  Header H File)
  5  *
  6  *
  7  * Note:                For dynamic control definition constant structure.
  8  *
  9  *
 10  * Export:
 11  *
 12  * Abbrev:
 13  *
 14  * History:
 15  *      Data            Who             Remark
 16  *      10/04/2007  MHC         Create initial version.
 17  *
 18  *****************************************************************************/
 19  /* Check to see if the file has been included already.  */
 20 #ifndef __R8192UDM_H__
 21 #define __R8192UDM_H__
 22 
 23 
 24 /*--------------------------Define Parameters-------------------------------*/
 25 #define         DM_DIG_THRESH_HIGH                                      40
 26 #define         DM_DIG_THRESH_LOW                                       35
 27 
 28 #define         DM_DIG_HIGH_PWR_THRESH_HIGH             75
 29 #define         DM_DIG_HIGH_PWR_THRESH_LOW              70
 30 
 31 #define         BW_AUTO_SWITCH_HIGH_LOW                 25
 32 #define         BW_AUTO_SWITCH_LOW_HIGH                 30
 33 
 34 #define         DM_check_fsync_time_interval                            500
 35 
 36 
 37 #define         DM_DIG_BACKOFF                          12
 38 #define         DM_DIG_MAX                                      0x36
 39 #define         DM_DIG_MIN                                      0x1c
 40 #define         DM_DIG_MIN_Netcore                      0x12
 41 
 42 #define         RxPathSelection_SS_TH_low               30
 43 #define         RxPathSelection_diff_TH                 18
 44 
 45 #define         RateAdaptiveTH_High                     50
 46 #define         RateAdaptiveTH_Low_20M          30
 47 #define         RateAdaptiveTH_Low_40M          10
 48 #define         VeryLowRSSI                                     15
 49 #define         CTSToSelfTHVal                                  30
 50 
 51 //defined by vivi, for tx power track
 52 #define         E_FOR_TX_POWER_TRACK               300
 53 //Dynamic Tx Power Control Threshold
 54 #define         TX_POWER_NEAR_FIELD_THRESH_HIGH         68
 55 #define         TX_POWER_NEAR_FIELD_THRESH_LOW          62
 56 //added by amy for atheros AP
 57 #define         TX_POWER_ATHEROAP_THRESH_HIGH           78
 58 #define         TX_POWER_ATHEROAP_THRESH_LOW            72
 59 
 60 //defined by vivi, for showing on UI
 61 #define                 Current_Tx_Rate_Reg         0x1b8
 62 #define                 Initial_Tx_Rate_Reg               0x1b9
 63 #define                 Tx_Retry_Count_Reg         0x1ac
 64 #define         RegC38_TH                                20
 65 #if 0
 66 //----------------------------------------------------------------------------
 67 //       8190 Rate Adaptive Table Register      (offset 0x320, 4 byte)
 68 //----------------------------------------------------------------------------
 69 
 70 //CCK
 71 #define RATR_1M                                 0x00000001
 72 #define RATR_2M                                 0x00000002
 73 #define RATR_55M                                        0x00000004
 74 #define RATR_11M                                        0x00000008
 75 //OFDM
 76 #define RATR_6M                                 0x00000010
 77 #define RATR_9M                                 0x00000020
 78 #define RATR_12M                                        0x00000040
 79 #define RATR_18M                                        0x00000080
 80 #define RATR_24M                                        0x00000100
 81 #define RATR_36M                                        0x00000200
 82 #define RATR_48M                                        0x00000400
 83 #define RATR_54M                                        0x00000800
 84 //MCS 1 Spatial Stream
 85 #define RATR_MCS0                                       0x00001000
 86 #define RATR_MCS1                                       0x00002000
 87 #define RATR_MCS2                                       0x00004000
 88 #define RATR_MCS3                                       0x00008000
 89 #define RATR_MCS4                                       0x00010000
 90 #define RATR_MCS5                                       0x00020000
 91 #define RATR_MCS6                                       0x00040000
 92 #define RATR_MCS7                                       0x00080000
 93 //MCS 2 Spatial Stream
 94 #define RATR_MCS8                                       0x00100000
 95 #define RATR_MCS9                                       0x00200000
 96 #define RATR_MCS10                                      0x00400000
 97 #define RATR_MCS11                                      0x00800000
 98 #define RATR_MCS12                                      0x01000000
 99 #define RATR_MCS13                                      0x02000000
100 #define RATR_MCS14                                      0x04000000
101 #define RATR_MCS15                                      0x08000000
102 // ALL CCK Rate
103 #define RATE_ALL_CCK                            RATR_1M|RATR_2M|RATR_55M|RATR_11M
104 #define RATE_ALL_OFDM_AG                        RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\
105                                                                         |RATR_36M|RATR_48M|RATR_54M
106 #define RATE_ALL_OFDM_2SS                       RATR_MCS8|RATR_MCS9     |RATR_MCS10|RATR_MCS11| \
107                                                                         RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
108 #endif
109 /*--------------------------Define Parameters-------------------------------*/
110 
111 
112 /*------------------------------Define structure----------------------------*/
113 /* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */
114 typedef struct _dynamic_initial_gain_threshold_
115 {
116         u8              dig_enable_flag;
117         u8              dig_algorithm;
118         u8              dbg_mode;
119         u8              dig_algorithm_switch;
120 
121         long            rssi_low_thresh;
122         long            rssi_high_thresh;
123 
124         long            rssi_high_power_lowthresh;
125         long            rssi_high_power_highthresh;
126 
127         u8              dig_state;
128         u8              dig_highpwr_state;
129         u8              cur_connect_state;
130         u8              pre_connect_state;
131 
132         u8              curpd_thstate;
133         u8              prepd_thstate;
134         u8              curcs_ratio_state;
135         u8              precs_ratio_state;
136 
137         u32             pre_ig_value;
138         u32             cur_ig_value;
139 
140         u8              backoff_val;
141         u8              rx_gain_range_max;
142         u8              rx_gain_range_min;
143         bool            initialgain_lowerbound_state;
144 
145         long            rssi_val;
146 }dig_t;
147 
148 typedef enum tag_dynamic_init_gain_state_definition
149 {
150         DM_STA_DIG_OFF = 0,
151         DM_STA_DIG_ON,
152         DM_STA_DIG_MAX
153 }dm_dig_sta_e;
154 
155 
156 /* 2007/10/08 MH Define RATR state. */
157 typedef enum tag_dynamic_ratr_state_definition
158 {
159         DM_RATR_STA_HIGH = 0,
160         DM_RATR_STA_MIDDLE = 1,
161         DM_RATR_STA_LOW = 2,
162         DM_RATR_STA_MAX
163 }dm_ratr_sta_e;
164 
165 /* 2007/10/11 MH Define DIG operation type. */
166 typedef enum tag_dynamic_init_gain_operation_type_definition
167 {
168         DIG_TYPE_THRESH_HIGH    = 0,
169         DIG_TYPE_THRESH_LOW     = 1,
170         DIG_TYPE_THRESH_HIGHPWR_HIGH    = 2,
171         DIG_TYPE_THRESH_HIGHPWR_LOW     = 3,
172         DIG_TYPE_DBG_MODE                               = 4,
173         DIG_TYPE_RSSI                                           = 5,
174         DIG_TYPE_ALGORITHM                              = 6,
175         DIG_TYPE_BACKOFF                                        = 7,
176         DIG_TYPE_PWDB_FACTOR                    = 8,
177         DIG_TYPE_RX_GAIN_MIN                            = 9,
178         DIG_TYPE_RX_GAIN_MAX                            = 10,
179         DIG_TYPE_ENABLE                 = 20,
180         DIG_TYPE_DISABLE                = 30,
181         DIG_OP_TYPE_MAX
182 }dm_dig_op_e;
183 
184 typedef enum tag_dig_algorithm_definition
185 {
186         DIG_ALGO_BY_FALSE_ALARM = 0,
187         DIG_ALGO_BY_RSSI        = 1,
188         DIG_ALGO_MAX
189 }dm_dig_alg_e;
190 
191 typedef enum tag_dig_dbgmode_definition
192 {
193         DIG_DBG_OFF = 0,
194         DIG_DBG_ON = 1,
195         DIG_DBG_MAX
196 }dm_dig_dbg_e;
197 
198 typedef enum tag_dig_connect_definition
199 {
200         DIG_DISCONNECT = 0,
201         DIG_CONNECT = 1,
202         DIG_CONNECT_MAX
203 }dm_dig_connect_e;
204 
205 typedef enum tag_dig_packetdetection_threshold_definition
206 {
207         DIG_PD_AT_LOW_POWER = 0,
208         DIG_PD_AT_NORMAL_POWER = 1,
209         DIG_PD_AT_HIGH_POWER = 2,
210         DIG_PD_MAX
211 }dm_dig_pd_th_e;
212 
213 typedef enum tag_dig_cck_cs_ratio_state_definition
214 {
215         DIG_CS_RATIO_LOWER = 0,
216         DIG_CS_RATIO_HIGHER = 1,
217         DIG_CS_MAX
218 }dm_dig_cs_ratio_e;
219 typedef struct _Dynamic_Rx_Path_Selection_
220 {
221         u8              Enable;
222         u8              DbgMode;
223         u8              cck_method;
224         u8              cck_Rx_path;
225 
226         u8              SS_TH_low;
227         u8              diff_TH;
228         u8              disabledRF;
229         u8              reserved;
230 
231         u8              rf_rssi[4];
232         u8              rf_enable_rssi_th[4];
233         long            cck_pwdb_sta[4];
234 }DRxPathSel;
235 
236 typedef enum tag_CCK_Rx_Path_Method_Definition
237 {
238         CCK_Rx_Version_1 = 0,
239         CCK_Rx_Version_2= 1,
240         CCK_Rx_Version_MAX
241 }DM_CCK_Rx_Path_Method;
242 
243 typedef enum tag_DM_DbgMode_Definition
244 {
245         DM_DBG_OFF = 0,
246         DM_DBG_ON = 1,
247         DM_DBG_MAX
248 }DM_DBG_E;
249 
250 typedef struct tag_Tx_Config_Cmd_Format
251 {
252         u32     Op;                                                                             /* Command packet type. */
253         u32     Length;                                                                 /* Command packet length. */
254         u32     Value;
255 }DCMD_TXCMD_T, *PDCMD_TXCMD_T;
256 /*------------------------------Define structure----------------------------*/
257 
258 
259 /*------------------------Export global variable----------------------------*/
260 extern  dig_t   dm_digtable;
261 extern  u8              dm_shadow[16][256];
262 extern DRxPathSel      DM_RxPathSelTable;
263 /*------------------------Export global variable----------------------------*/
264 
265 
266 /*------------------------Export Marco Definition---------------------------*/
267 
268 /*------------------------Export Marco Definition---------------------------*/
269 
270 
271 /*--------------------------Exported Function prototype---------------------*/
272 extern  void    init_hal_dm(struct net_device *dev);
273 extern  void deinit_hal_dm(struct net_device *dev);
274 
275 extern void hal_dm_watchdog(struct net_device *dev);
276 
277 extern  void    init_rate_adaptive(struct net_device *dev);
278 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
279 extern  void    dm_txpower_trackingcallback(struct work_struct *work);
280 #else
281 extern  void    dm_txpower_trackingcallback(struct net_device *dev);
282 #endif
283 extern  void    dm_restore_dynamic_mechanism_state(struct net_device *dev);
284 extern  void    dm_backup_dynamic_mechanism_state(struct net_device *dev);
285 extern  void    dm_change_dynamic_initgain_thresh(struct net_device *dev,
286                                                                 u32 dm_type, u32 dm_value);
287 extern  void    dm_force_tx_fw_info(struct net_device *dev,u32 force_type, u32 force_value);
288 extern  void    dm_init_edca_turbo(struct net_device *dev);
289 extern  void    dm_rf_operation_test_callback(unsigned long data);
290 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
291 extern  void    dm_rf_pathcheck_workitemcallback(struct work_struct *work);
292 #else
293 extern  void    dm_rf_pathcheck_workitemcallback(struct net_device *dev);
294 #endif
295 extern  void dm_fsync_timer_callback(unsigned long data);
296 extern  void    dm_cck_txpower_adjust(struct net_device *dev,bool  binch14);
297 #if 0
298 extern  char    dm_check_lbus_status(IN PADAPTER        Adapter);
299 #endif
300 extern  void    dm_shadow_init(struct net_device *dev);
301 extern void dm_initialize_txpower_tracking(struct net_device *dev);
302 /*--------------------------Exported Function prototype---------------------*/
303 
304 
305 #endif  /*__R8192UDM_H__ */
306 
307 
308 /* End of r8192U_dm.h */
309 
310 
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