1 #ifndef __INC_FIRMWARE_H
2 #define __INC_FIRMWARE_H
3
4
5 //#define RTL8190_CPU_START_OFFSET 0x80
6 /* TODO: this definition is TBD */
7 //#define USB_HWDESC_HEADER_LEN 0
8
9 /* It should be double word alignment */
10 //#if DEV_BUS_TYPE==PCI_INTERFACE
11 //#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8
12 //#else
13 //#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN)
14 //#endif
15
16 //typedef enum _firmware_init_step{
17 // FW_INIT_STEP0_BOOT = 0,
18 // FW_INIT_STEP1_MAIN = 1,
19 // FW_INIT_STEP2_DATA = 2,
20 //}firmware_init_step_e;
21
22 //typedef enum _DESC_PACKET_TYPE{
23 // DESC_PACKET_TYPE_INIT = 0,
24 // DESC_PACKET_TYPE_NORMAL = 1,
25 //}DESC_PACKET_TYPE;
26 #define RTL8192S_FW_PKT_FRAG_SIZE 0xFF00 // 64K
27
28
29 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
30 #define MAX_FIRMWARE_CODE_SIZE 0xFF00 // Firmware Local buffer size.
31 #define RTL8190_CPU_START_OFFSET 0x80
32
33 #ifdef RTL8192SE
34 //It should be double word alignment
35 #define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8
36 #else
37 #define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN)
38 #endif
39
40 //typedef enum _DESC_PACKET_TYPE{
41 // DESC_PACKET_TYPE_INIT = 0,
42 // DESC_PACKET_TYPE_NORMAL = 1,
43 //}DESC_PACKET_TYPE;
44
45 // Forward declaration.
46 //typedef struct _ADAPTER ADAPTER, *PADAPTER;
47 #ifdef RTL8192S
48 typedef enum _firmware_init_step{
49 FW_INIT_STEP0_IMEM = 0,
50 FW_INIT_STEP1_MAIN = 1,
51 FW_INIT_STEP2_DATA = 2,
52 }firmware_init_step_e;
53 #else
54 typedef enum _firmware_init_step{
55 FW_INIT_STEP0_BOOT = 0,
56 FW_INIT_STEP1_MAIN = 1,
57 FW_INIT_STEP2_DATA = 2,
58 }firmware_init_step_e;
59 #endif
60
61 /* due to rtl8192 firmware */
62 typedef enum _desc_packet_type_e{
63 DESC_PACKET_TYPE_INIT = 0,
64 DESC_PACKET_TYPE_NORMAL = 1,
65 }desc_packet_type_e;
66
67 typedef enum _firmware_source{
68 FW_SOURCE_IMG_FILE = 0,
69 FW_SOURCE_HEADER_FILE = 1,
70 }firmware_source_e, *pfirmware_source_e;
71
72
73 typedef enum _opt_rst_type{
74 OPT_SYSTEM_RESET = 0,
75 OPT_FIRMWARE_RESET = 1,
76 }opt_rst_type_e;
77
78 /*typedef enum _FIRMWARE_STATUS{
79 FW_STATUS_0_INIT = 0,
80 FW_STATUS_1_MOVE_BOOT_CODE = 1,
81 FW_STATUS_2_MOVE_MAIN_CODE = 2,
82 FW_STATUS_3_TURNON_CPU = 3,
83 FW_STATUS_4_MOVE_DATA_CODE = 4,
84 FW_STATUS_5_READY = 5,
85 }FIRMWARE_STATUS;
86 */
87 //--------------------------------------------------------------------------------
88 // RTL8192S Firmware related, Revised by Roger, 2008.12.18.
89 //--------------------------------------------------------------------------------
90 typedef struct _RT_8192S_FIRMWARE_PRIV { //8-bytes alignment required
91
92 //--- long word 0 ----
93 u8 signature_0; //0x12: CE product, 0x92: IT product
94 u8 signature_1; //0x87: CE product, 0x81: IT product
95 u8 hci_sel; //0x81: PCI-AP, 01:PCIe, 02: 92S-U, 0x82: USB-AP, 0x12: 72S-U, 03:SDIO
96 u8 chip_version; //the same value as reigster value
97 u8 customer_ID_0; //customer ID low byte
98 u8 customer_ID_1; //customer ID high byte
99 u8 rf_config; //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R
100 u8 usb_ep_num; // 4: 4EP, 6: 6EP, 11: 11EP
101
102 //--- long word 1 ----
103 u8 regulatory_class_0; //regulatory class bit map 0
104 u8 regulatory_class_1; //regulatory class bit map 1
105 u8 regulatory_class_2; //regulatory class bit map 2
106 u8 regulatory_class_3; //regulatory class bit map 3
107 u8 rfintfs; // 0:SWSI, 1:HWSI, 2:HWPI
108 u8 def_nettype;
109 u8 rsvd010;
110 u8 rsvd011;
111
112
113 //--- long word 2 ----
114 u8 lbk_mode; //0x00: normal, 0x03: MACLBK, 0x01: PHYLBK
115 u8 mp_mode; // 1: for MP use, 0: for normal driver (to be discussed)
116 u8 rsvd020;
117 u8 rsvd021;
118 u8 rsvd022;
119 u8 rsvd023;
120 u8 rsvd024;
121 u8 rsvd025;
122
123 //--- long word 3 ----
124 u8 qos_en; // QoS enable
125 u8 bw_40MHz_en; // 40MHz BW enable
126 u8 AMSDU2AMPDU_en; // 4181 convert AMSDU to AMPDU, 0: disable
127 u8 AMPDU_en; // 11n AMPDU enable
128 u8 rate_control_offload;//FW offloads, 0: driver handles
129 u8 aggregation_offload; // FW offloads, 0: driver handles
130 u8 rsvd030;
131 u8 rsvd031;
132
133
134 //--- long word 4 ----
135 unsigned char beacon_offload; // 1. FW offloads, 0: driver handles
136 unsigned char MLME_offload; // 2. FW offloads, 0: driver handles
137 unsigned char hwpc_offload; // 3. FW offloads, 0: driver handles
138 unsigned char tcp_checksum_offload; // 4. FW offloads, 0: driver handles
139 unsigned char tcp_offload; // 5. FW offloads, 0: driver handles
140 unsigned char ps_control_offload; // 6. FW offloads, 0: driver handles
141 unsigned char WWLAN_offload; // 7. FW offloads, 0: driver handles
142 unsigned char rsvd040;
143
144 //--- long word 5 ----
145 u8 tcp_tx_frame_len_L; //tcp tx packet length low byte
146 u8 tcp_tx_frame_len_H; //tcp tx packet length high byte
147 u8 tcp_rx_frame_len_L; //tcp rx packet length low byte
148 u8 tcp_rx_frame_len_H; //tcp rx packet length high byte
149 u8 rsvd050;
150 u8 rsvd051;
151 u8 rsvd052;
152 u8 rsvd053;
153 }RT_8192S_FIRMWARE_PRIV, *PRT_8192S_FIRMWARE_PRIV;
154
155 typedef struct _RT_8192S_FIRMWARE_HDR {//8-byte alinment required
156
157 //--- LONG WORD 0 ----
158 u16 Signature;
159 u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version,
160 u32 DMEMSize; //define the size of boot loader
161
162
163 //--- LONG WORD 1 ----
164 u32 IMG_IMEM_SIZE; //define the size of FW in IMEM
165 u32 IMG_SRAM_SIZE; //define the size of FW in SRAM
166
167 //--- LONG WORD 2 ----
168 u32 FW_PRIV_SIZE; //define the size of DMEM variable
169 u32 Rsvd0;
170
171 //--- LONG WORD 3 ----
172 u32 Rsvd1;
173 u32 Rsvd2;
174
175 RT_8192S_FIRMWARE_PRIV FWPriv;
176
177 }RT_8192S_FIRMWARE_HDR, *PRT_8192S_FIRMWARE_HDR;
178
179 #define RT_8192S_FIRMWARE_HDR_SIZE 80
180 #define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32
181
182 typedef enum _FIRMWARE_8192S_STATUS{
183 FW_STATUS_INIT = 0,
184 FW_STATUS_LOAD_IMEM = 1,
185 FW_STATUS_LOAD_EMEM = 2,
186 FW_STATUS_LOAD_DMEM = 3,
187 FW_STATUS_READY = 4,
188 }FIRMWARE_8192S_STATUS;
189
190 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
191
192 typedef struct _rt_firmware{
193 firmware_source_e eFWSource;
194 PRT_8192S_FIRMWARE_HDR pFwHeader;
195 FIRMWARE_8192S_STATUS FWStatus;
196 u16 FirmwareVersion;
197 u8 FwIMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE];
198 u8 FwEMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE];
199 u32 FwIMEMLen;
200 u32 FwEMEMLen;
201 u8 szFwTmpBuffer[164000];
202 u32 szFwTmpBufferLen;
203 u16 CmdPacketFragThresold;
204 }rt_firmware, *prt_firmware;
205
206 //typedef struct _RT_FIRMWARE_INFO_8192SU{
207 // u8 szInfo[16];
208 //}RT_FIRMWARE_INFO_8192SU, *PRT_FIRMWARE_INFO_8192SU;
209 bool FirmwareDownload92S(struct net_device *dev);
210
211 #endif
212
213
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