1 /**
2 * @file meplx_reg.h
3 *
4 * @brief PLX 9052 PCI bridge register definitions.
5 * @note Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
6 * @author Guenter Gebhardt
7 */
8
9 /*
10 * Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
11 *
12 * This file is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #ifndef _MEPLX_REG_H_
28 #define _MEPLX_REG_H_
29
30 #ifdef __KERNEL__
31
32 #define PLX_INTCSR 0x4C /**< Interrupt control and status register. */
33 #define PLX_INTCSR_LOCAL_INT1_EN 0x01 /**< If set, local interrupt 1 is enabled (r/w). */
34 #define PLX_INTCSR_LOCAL_INT1_POL 0x02 /**< If set, local interrupt 1 polarity is active high (r/w). */
35 #define PLX_INTCSR_LOCAL_INT1_STATE 0x04 /**< If set, local interrupt 1 is active (r/_). */
36 #define PLX_INTCSR_LOCAL_INT2_EN 0x08 /**< If set, local interrupt 2 is enabled (r/w). */
37 #define PLX_INTCSR_LOCAL_INT2_POL 0x10 /**< If set, local interrupt 2 polarity is active high (r/w). */
38 #define PLX_INTCSR_LOCAL_INT2_STATE 0x20 /**< If set, local interrupt 2 is active (r/_). */
39 #define PLX_INTCSR_PCI_INT_EN 0x40 /**< If set, PCI interrupt is enabled (r/w). */
40 #define PLX_INTCSR_SOFT_INT 0x80 /**< If set, a software interrupt is generated (r/w). */
41
42 #define PLX_ICR 0x50 /**< Initialization control register. */
43 #define PLX_ICR_BIT_EEPROM_CLOCK_SET 0x01000000
44 #define PLX_ICR_BIT_EEPROM_CHIP_SELECT 0x02000000
45 #define PLX_ICR_BIT_EEPROM_WRITE 0x04000000
46 #define PLX_ICR_BIT_EEPROM_READ 0x08000000
47 #define PLX_ICR_BIT_EEPROM_VALID 0x10000000
48
49 #define PLX_ICR_MASK_EEPROM 0x1F000000
50 #define EEPROM_DELAY 1
51
52 #endif
53 #endif
54
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