1 /*
2 * xilinx_spi.c
3 *
4 * Xilinx SPI controller driver (master mode only)
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is licensed
11 * "as is" without any warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/platform_device.h>
18
19 #include <linux/of_platform.h>
20 #include <linux/of_device.h>
21 #include <linux/of_spi.h>
22
23 #include <linux/spi/spi.h>
24 #include <linux/spi/spi_bitbang.h>
25 #include <linux/io.h>
26
27 #define XILINX_SPI_NAME "xilinx_spi"
28
29 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
30 * Product Specification", DS464
31 */
32 #define XSPI_CR_OFFSET 0x62 /* 16-bit Control Register */
33
34 #define XSPI_CR_ENABLE 0x02
35 #define XSPI_CR_MASTER_MODE 0x04
36 #define XSPI_CR_CPOL 0x08
37 #define XSPI_CR_CPHA 0x10
38 #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL)
39 #define XSPI_CR_TXFIFO_RESET 0x20
40 #define XSPI_CR_RXFIFO_RESET 0x40
41 #define XSPI_CR_MANUAL_SSELECT 0x80
42 #define XSPI_CR_TRANS_INHIBIT 0x100
43
44 #define XSPI_SR_OFFSET 0x67 /* 8-bit Status Register */
45
46 #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
47 #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
48 #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
49 #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
50 #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
51
52 #define XSPI_TXD_OFFSET 0x6b /* 8-bit Data Transmit Register */
53 #define XSPI_RXD_OFFSET 0x6f /* 8-bit Data Receive Register */
54
55 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
56
57 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
58 * IPIF registers are 32 bit
59 */
60 #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
61 #define XIPIF_V123B_GINTR_ENABLE 0x80000000
62
63 #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
64 #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
65
66 #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
67 #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
68 * disabled */
69 #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
70 #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
71 #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
72 #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
73
74 #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
75 #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
76
77 struct xilinx_spi {
78 /* bitbang has to be first */
79 struct spi_bitbang bitbang;
80 struct completion done;
81
82 void __iomem *regs; /* virt. address of the control registers */
83
84 u32 irq;
85
86 u32 speed_hz; /* SCK has a fixed frequency of speed_hz Hz */
87
88 u8 *rx_ptr; /* pointer in the Tx buffer */
89 const u8 *tx_ptr; /* pointer in the Rx buffer */
90 int remaining_bytes; /* the number of bytes left to transfer */
91 };
92
93 static void xspi_init_hw(void __iomem *regs_base)
94 {
95 /* Reset the SPI device */
96 out_be32(regs_base + XIPIF_V123B_RESETR_OFFSET,
97 XIPIF_V123B_RESET_MASK);
98 /* Disable all the interrupts just in case */
99 out_be32(regs_base + XIPIF_V123B_IIER_OFFSET, 0);
100 /* Enable the global IPIF interrupt */
101 out_be32(regs_base + XIPIF_V123B_DGIER_OFFSET,
102 XIPIF_V123B_GINTR_ENABLE);
103 /* Deselect the slave on the SPI bus */
104 out_be32(regs_base + XSPI_SSR_OFFSET, 0xffff);
105 /* Disable the transmitter, enable Manual Slave Select Assertion,
106 * put SPI controller into master mode, and enable it */
107 out_be16(regs_base + XSPI_CR_OFFSET,
108 XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT
109 | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE);
110 }
111
112 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
113 {
114 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
115
116 if (is_on == BITBANG_CS_INACTIVE) {
117 /* Deselect the slave on the SPI bus */
118 out_be32(xspi->regs + XSPI_SSR_OFFSET, 0xffff);
119 } else if (is_on == BITBANG_CS_ACTIVE) {
120 /* Set the SPI clock phase and polarity */
121 u16 cr = in_be16(xspi->regs + XSPI_CR_OFFSET)
122 & ~XSPI_CR_MODE_MASK;
123 if (spi->mode & SPI_CPHA)
124 cr |= XSPI_CR_CPHA;
125 if (spi->mode & SPI_CPOL)
126 cr |= XSPI_CR_CPOL;
127 out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
128
129 /* We do not check spi->max_speed_hz here as the SPI clock
130 * frequency is not software programmable (the IP block design
131 * parameter)
132 */
133
134 /* Activate the chip select */
135 out_be32(xspi->regs + XSPI_SSR_OFFSET,
136 ~(0x0001 << spi->chip_select));
137 }
138 }
139
140 /* spi_bitbang requires custom setup_transfer() to be defined if there is a
141 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
142 * supports just 8 bits per word, and SPI clock can't be changed in software.
143 * Check for 8 bits per word. Chip select delay calculations could be
144 * added here as soon as bitbang_work() can be made aware of the delay value.
145 */
146 static int xilinx_spi_setup_transfer(struct spi_device *spi,
147 struct spi_transfer *t)
148 {
149 u8 bits_per_word;
150
151 bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
152 if (bits_per_word != 8) {
153 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
154 __func__, bits_per_word);
155 return -EINVAL;
156 }
157
158 return 0;
159 }
160
161 static int xilinx_spi_setup(struct spi_device *spi)
162 {
163 struct spi_bitbang *bitbang;
164 struct xilinx_spi *xspi;
165 int retval;
166
167 xspi = spi_master_get_devdata(spi->master);
168 bitbang = &xspi->bitbang;
169
170 retval = xilinx_spi_setup_transfer(spi, NULL);
171 if (retval < 0)
172 return retval;
173
174 return 0;
175 }
176
177 static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
178 {
179 u8 sr;
180
181 /* Fill the Tx FIFO with as many bytes as possible */
182 sr = in_8(xspi->regs + XSPI_SR_OFFSET);
183 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
184 if (xspi->tx_ptr) {
185 out_8(xspi->regs + XSPI_TXD_OFFSET, *xspi->tx_ptr++);
186 } else {
187 out_8(xspi->regs + XSPI_TXD_OFFSET, 0);
188 }
189 xspi->remaining_bytes--;
190 sr = in_8(xspi->regs + XSPI_SR_OFFSET);
191 }
192 }
193
194 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
195 {
196 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
197 u32 ipif_ier;
198 u16 cr;
199
200 /* We get here with transmitter inhibited */
201
202 xspi->tx_ptr = t->tx_buf;
203 xspi->rx_ptr = t->rx_buf;
204 xspi->remaining_bytes = t->len;
205 INIT_COMPLETION(xspi->done);
206
207 xilinx_spi_fill_tx_fifo(xspi);
208
209 /* Enable the transmit empty interrupt, which we use to determine
210 * progress on the transmission.
211 */
212 ipif_ier = in_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET);
213 out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET,
214 ipif_ier | XSPI_INTR_TX_EMPTY);
215
216 /* Start the transfer by not inhibiting the transmitter any longer */
217 cr = in_be16(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_TRANS_INHIBIT;
218 out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
219
220 wait_for_completion(&xspi->done);
221
222 /* Disable the transmit empty interrupt */
223 out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET, ipif_ier);
224
225 return t->len - xspi->remaining_bytes;
226 }
227
228
229 /* This driver supports single master mode only. Hence Tx FIFO Empty
230 * is the only interrupt we care about.
231 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
232 * Fault are not to happen.
233 */
234 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
235 {
236 struct xilinx_spi *xspi = dev_id;
237 u32 ipif_isr;
238
239 /* Get the IPIF interrupts, and clear them immediately */
240 ipif_isr = in_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET);
241 out_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET, ipif_isr);
242
243 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
244 u16 cr;
245 u8 sr;
246
247 /* A transmit has just completed. Process received data and
248 * check for more data to transmit. Always inhibit the
249 * transmitter while the Isr refills the transmit register/FIFO,
250 * or make sure it is stopped if we're done.
251 */
252 cr = in_be16(xspi->regs + XSPI_CR_OFFSET);
253 out_be16(xspi->regs + XSPI_CR_OFFSET,
254 cr | XSPI_CR_TRANS_INHIBIT);
255
256 /* Read out all the data from the Rx FIFO */
257 sr = in_8(xspi->regs + XSPI_SR_OFFSET);
258 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
259 u8 data;
260
261 data = in_8(xspi->regs + XSPI_RXD_OFFSET);
262 if (xspi->rx_ptr) {
263 *xspi->rx_ptr++ = data;
264 }
265 sr = in_8(xspi->regs + XSPI_SR_OFFSET);
266 }
267
268 /* See if there is more data to send */
269 if (xspi->remaining_bytes > 0) {
270 xilinx_spi_fill_tx_fifo(xspi);
271 /* Start the transfer by not inhibiting the
272 * transmitter any longer
273 */
274 out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
275 } else {
276 /* No more data to send.
277 * Indicate the transfer is completed.
278 */
279 complete(&xspi->done);
280 }
281 }
282
283 return IRQ_HANDLED;
284 }
285
286 static int __init xilinx_spi_of_probe(struct of_device *ofdev,
287 const struct of_device_id *match)
288 {
289 struct spi_master *master;
290 struct xilinx_spi *xspi;
291 struct resource r_irq_struct;
292 struct resource r_mem_struct;
293
294 struct resource *r_irq = &r_irq_struct;
295 struct resource *r_mem = &r_mem_struct;
296 int rc = 0;
297 const u32 *prop;
298 int len;
299
300 /* Get resources(memory, IRQ) associated with the device */
301 master = spi_alloc_master(&ofdev->dev, sizeof(struct xilinx_spi));
302
303 if (master == NULL) {
304 return -ENOMEM;
305 }
306
307 dev_set_drvdata(&ofdev->dev, master);
308
309 rc = of_address_to_resource(ofdev->node, 0, r_mem);
310 if (rc) {
311 dev_warn(&ofdev->dev, "invalid address\n");
312 goto put_master;
313 }
314
315 rc = of_irq_to_resource(ofdev->node, 0, r_irq);
316 if (rc == NO_IRQ) {
317 dev_warn(&ofdev->dev, "no IRQ found\n");
318 goto put_master;
319 }
320
321 /* the spi->mode bits understood by this driver: */
322 master->mode_bits = SPI_CPOL | SPI_CPHA;
323
324 xspi = spi_master_get_devdata(master);
325 xspi->bitbang.master = spi_master_get(master);
326 xspi->bitbang.chipselect = xilinx_spi_chipselect;
327 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
328 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
329 xspi->bitbang.master->setup = xilinx_spi_setup;
330 init_completion(&xspi->done);
331
332 xspi->irq = r_irq->start;
333
334 if (!request_mem_region(r_mem->start,
335 r_mem->end - r_mem->start + 1, XILINX_SPI_NAME)) {
336 rc = -ENXIO;
337 dev_warn(&ofdev->dev, "memory request failure\n");
338 goto put_master;
339 }
340
341 xspi->regs = ioremap(r_mem->start, r_mem->end - r_mem->start + 1);
342 if (xspi->regs == NULL) {
343 rc = -ENOMEM;
344 dev_warn(&ofdev->dev, "ioremap failure\n");
345 goto release_mem;
346 }
347 xspi->irq = r_irq->start;
348
349 /* dynamic bus assignment */
350 master->bus_num = -1;
351
352 /* number of slave select bits is required */
353 prop = of_get_property(ofdev->node, "xlnx,num-ss-bits", &len);
354 if (!prop || len < sizeof(*prop)) {
355 dev_warn(&ofdev->dev, "no 'xlnx,num-ss-bits' property\n");
356 goto unmap_io;
357 }
358 master->num_chipselect = *prop;
359
360 /* SPI controller initializations */
361 xspi_init_hw(xspi->regs);
362
363 /* Register for SPI Interrupt */
364 rc = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
365 if (rc != 0) {
366 dev_warn(&ofdev->dev, "irq request failure: %d\n", xspi->irq);
367 goto unmap_io;
368 }
369
370 rc = spi_bitbang_start(&xspi->bitbang);
371 if (rc != 0) {
372 dev_err(&ofdev->dev, "spi_bitbang_start FAILED\n");
373 goto free_irq;
374 }
375
376 dev_info(&ofdev->dev, "at 0x%08X mapped to 0x%08X, irq=%d\n",
377 (unsigned int)r_mem->start, (u32)xspi->regs, xspi->irq);
378
379 /* Add any subnodes on the SPI bus */
380 of_register_spi_devices(master, ofdev->node);
381
382 return rc;
383
384 free_irq:
385 free_irq(xspi->irq, xspi);
386 unmap_io:
387 iounmap(xspi->regs);
388 release_mem:
389 release_mem_region(r_mem->start, resource_size(r_mem));
390 put_master:
391 spi_master_put(master);
392 return rc;
393 }
394
395 static int __devexit xilinx_spi_remove(struct of_device *ofdev)
396 {
397 struct xilinx_spi *xspi;
398 struct spi_master *master;
399 struct resource r_mem;
400
401 master = platform_get_drvdata(ofdev);
402 xspi = spi_master_get_devdata(master);
403
404 spi_bitbang_stop(&xspi->bitbang);
405 free_irq(xspi->irq, xspi);
406 iounmap(xspi->regs);
407 if (!of_address_to_resource(ofdev->node, 0, &r_mem))
408 release_mem_region(r_mem.start, resource_size(&r_mem));
409 dev_set_drvdata(&ofdev->dev, 0);
410 spi_master_put(xspi->bitbang.master);
411
412 return 0;
413 }
414
415 /* work with hotplug and coldplug */
416 MODULE_ALIAS("platform:" XILINX_SPI_NAME);
417
418 static int __exit xilinx_spi_of_remove(struct of_device *op)
419 {
420 return xilinx_spi_remove(op);
421 }
422
423 static struct of_device_id xilinx_spi_of_match[] = {
424 { .compatible = "xlnx,xps-spi-2.00.a", },
425 { .compatible = "xlnx,xps-spi-2.00.b", },
426 {}
427 };
428
429 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
430
431 static struct of_platform_driver xilinx_spi_of_driver = {
432 .owner = THIS_MODULE,
433 .name = "xilinx-xps-spi",
434 .match_table = xilinx_spi_of_match,
435 .probe = xilinx_spi_of_probe,
436 .remove = __exit_p(xilinx_spi_of_remove),
437 .driver = {
438 .name = "xilinx-xps-spi",
439 .owner = THIS_MODULE,
440 },
441 };
442
443 static int __init xilinx_spi_init(void)
444 {
445 return of_register_platform_driver(&xilinx_spi_of_driver);
446 }
447 module_init(xilinx_spi_init);
448
449 static void __exit xilinx_spi_exit(void)
450 {
451 of_unregister_platform_driver(&xilinx_spi_of_driver);
452 }
453 module_exit(xilinx_spi_exit);
454 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
455 MODULE_DESCRIPTION("Xilinx SPI driver");
456 MODULE_LICENSE("GPL");
457
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