1 /*
2 * omap_uwire.c -- MicroWire interface driver for OMAP
3 *
4 * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
5 *
6 * Ported to 2.6 OMAP uwire interface.
7 * Copyright (C) 2004 Texas Instruments.
8 *
9 * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
10 *
11 * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
12 * Copyright (C) 2006 Nokia
13 *
14 * Many updates by Imre Deak <imre.deak@nokia.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */
36 #include <linux/kernel.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/platform_device.h>
40 #include <linux/workqueue.h>
41 #include <linux/interrupt.h>
42 #include <linux/err.h>
43 #include <linux/clk.h>
44
45 #include <linux/spi/spi.h>
46 #include <linux/spi/spi_bitbang.h>
47
48 #include <asm/system.h>
49 #include <asm/irq.h>
50 #include <mach/hardware.h>
51 #include <asm/io.h>
52 #include <asm/mach-types.h>
53
54 #include <mach/mux.h>
55 #include <mach/omap730.h> /* OMAP730_IO_CONF registers */
56
57
58 /* FIXME address is now a platform device resource,
59 * and irqs should show there too...
60 */
61 #define UWIRE_BASE_PHYS 0xFFFB3000
62
63 /* uWire Registers: */
64 #define UWIRE_IO_SIZE 0x20
65 #define UWIRE_TDR 0x00
66 #define UWIRE_RDR 0x00
67 #define UWIRE_CSR 0x01
68 #define UWIRE_SR1 0x02
69 #define UWIRE_SR2 0x03
70 #define UWIRE_SR3 0x04
71 #define UWIRE_SR4 0x05
72 #define UWIRE_SR5 0x06
73
74 /* CSR bits */
75 #define RDRB (1 << 15)
76 #define CSRB (1 << 14)
77 #define START (1 << 13)
78 #define CS_CMD (1 << 12)
79
80 /* SR1 or SR2 bits */
81 #define UWIRE_READ_FALLING_EDGE 0x0001
82 #define UWIRE_READ_RISING_EDGE 0x0000
83 #define UWIRE_WRITE_FALLING_EDGE 0x0000
84 #define UWIRE_WRITE_RISING_EDGE 0x0002
85 #define UWIRE_CS_ACTIVE_LOW 0x0000
86 #define UWIRE_CS_ACTIVE_HIGH 0x0004
87 #define UWIRE_FREQ_DIV_2 0x0000
88 #define UWIRE_FREQ_DIV_4 0x0008
89 #define UWIRE_FREQ_DIV_8 0x0010
90 #define UWIRE_CHK_READY 0x0020
91 #define UWIRE_CLK_INVERTED 0x0040
92
93
94 struct uwire_spi {
95 struct spi_bitbang bitbang;
96 struct clk *ck;
97 };
98
99 struct uwire_state {
100 unsigned bits_per_word;
101 unsigned div1_idx;
102 };
103
104 /* REVISIT compile time constant for idx_shift? */
105 /*
106 * Or, put it in a structure which is used throughout the driver;
107 * that avoids having to issue two loads for each bit of static data.
108 */
109 static unsigned int uwire_idx_shift;
110 static void __iomem *uwire_base;
111
112 static inline void uwire_write_reg(int idx, u16 val)
113 {
114 __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
115 }
116
117 static inline u16 uwire_read_reg(int idx)
118 {
119 return __raw_readw(uwire_base + (idx << uwire_idx_shift));
120 }
121
122 static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
123 {
124 u16 w, val = 0;
125 int shift, reg;
126
127 if (flags & UWIRE_CLK_INVERTED)
128 val ^= 0x03;
129 val = flags & 0x3f;
130 if (cs & 1)
131 shift = 6;
132 else
133 shift = 0;
134 if (cs <= 1)
135 reg = UWIRE_SR1;
136 else
137 reg = UWIRE_SR2;
138
139 w = uwire_read_reg(reg);
140 w &= ~(0x3f << shift);
141 w |= val << shift;
142 uwire_write_reg(reg, w);
143 }
144
145 static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
146 {
147 u16 w;
148 int c = 0;
149 unsigned long max_jiffies = jiffies + HZ;
150
151 for (;;) {
152 w = uwire_read_reg(UWIRE_CSR);
153 if ((w & mask) == val)
154 break;
155 if (time_after(jiffies, max_jiffies)) {
156 printk(KERN_ERR "%s: timeout. reg=%#06x "
157 "mask=%#06x val=%#06x\n",
158 __func__, w, mask, val);
159 return -1;
160 }
161 c++;
162 if (might_not_catch && c > 64)
163 break;
164 }
165 return 0;
166 }
167
168 static void uwire_set_clk1_div(int div1_idx)
169 {
170 u16 w;
171
172 w = uwire_read_reg(UWIRE_SR3);
173 w &= ~(0x03 << 1);
174 w |= div1_idx << 1;
175 uwire_write_reg(UWIRE_SR3, w);
176 }
177
178 static void uwire_chipselect(struct spi_device *spi, int value)
179 {
180 struct uwire_state *ust = spi->controller_state;
181 u16 w;
182 int old_cs;
183
184
185 BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
186
187 w = uwire_read_reg(UWIRE_CSR);
188 old_cs = (w >> 10) & 0x03;
189 if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
190 /* Deselect this CS, or the previous CS */
191 w &= ~CS_CMD;
192 uwire_write_reg(UWIRE_CSR, w);
193 }
194 /* activate specfied chipselect */
195 if (value == BITBANG_CS_ACTIVE) {
196 uwire_set_clk1_div(ust->div1_idx);
197 /* invert clock? */
198 if (spi->mode & SPI_CPOL)
199 uwire_write_reg(UWIRE_SR4, 1);
200 else
201 uwire_write_reg(UWIRE_SR4, 0);
202
203 w = spi->chip_select << 10;
204 w |= CS_CMD;
205 uwire_write_reg(UWIRE_CSR, w);
206 }
207 }
208
209 static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
210 {
211 struct uwire_state *ust = spi->controller_state;
212 unsigned len = t->len;
213 unsigned bits = ust->bits_per_word;
214 unsigned bytes;
215 u16 val, w;
216 int status = 0;;
217
218 if (!t->tx_buf && !t->rx_buf)
219 return 0;
220
221 /* Microwire doesn't read and write concurrently */
222 if (t->tx_buf && t->rx_buf)
223 return -EPERM;
224
225 w = spi->chip_select << 10;
226 w |= CS_CMD;
227
228 if (t->tx_buf) {
229 const u8 *buf = t->tx_buf;
230
231 /* NOTE: DMA could be used for TX transfers */
232
233 /* write one or two bytes at a time */
234 while (len >= 1) {
235 /* tx bit 15 is first sent; we byteswap multibyte words
236 * (msb-first) on the way out from memory.
237 */
238 val = *buf++;
239 if (bits > 8) {
240 bytes = 2;
241 val |= *buf++ << 8;
242 } else
243 bytes = 1;
244 val <<= 16 - bits;
245
246 #ifdef VERBOSE
247 pr_debug("%s: write-%d =%04x\n",
248 dev_name(&spi->dev), bits, val);
249 #endif
250 if (wait_uwire_csr_flag(CSRB, 0, 0))
251 goto eio;
252
253 uwire_write_reg(UWIRE_TDR, val);
254
255 /* start write */
256 val = START | w | (bits << 5);
257
258 uwire_write_reg(UWIRE_CSR, val);
259 len -= bytes;
260
261 /* Wait till write actually starts.
262 * This is needed with MPU clock 60+ MHz.
263 * REVISIT: we may not have time to catch it...
264 */
265 if (wait_uwire_csr_flag(CSRB, CSRB, 1))
266 goto eio;
267
268 status += bytes;
269 }
270
271 /* REVISIT: save this for later to get more i/o overlap */
272 if (wait_uwire_csr_flag(CSRB, 0, 0))
273 goto eio;
274
275 } else if (t->rx_buf) {
276 u8 *buf = t->rx_buf;
277
278 /* read one or two bytes at a time */
279 while (len) {
280 if (bits > 8) {
281 bytes = 2;
282 } else
283 bytes = 1;
284
285 /* start read */
286 val = START | w | (bits << 0);
287 uwire_write_reg(UWIRE_CSR, val);
288 len -= bytes;
289
290 /* Wait till read actually starts */
291 (void) wait_uwire_csr_flag(CSRB, CSRB, 1);
292
293 if (wait_uwire_csr_flag(RDRB | CSRB,
294 RDRB, 0))
295 goto eio;
296
297 /* rx bit 0 is last received; multibyte words will
298 * be properly byteswapped on the way to memory.
299 */
300 val = uwire_read_reg(UWIRE_RDR);
301 val &= (1 << bits) - 1;
302 *buf++ = (u8) val;
303 if (bytes == 2)
304 *buf++ = val >> 8;
305 status += bytes;
306 #ifdef VERBOSE
307 pr_debug("%s: read-%d =%04x\n",
308 dev_name(&spi->dev), bits, val);
309 #endif
310
311 }
312 }
313 return status;
314 eio:
315 return -EIO;
316 }
317
318 static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
319 {
320 struct uwire_state *ust = spi->controller_state;
321 struct uwire_spi *uwire;
322 unsigned flags = 0;
323 unsigned bits;
324 unsigned hz;
325 unsigned long rate;
326 int div1_idx;
327 int div1;
328 int div2;
329 int status;
330
331 uwire = spi_master_get_devdata(spi->master);
332
333 if (spi->chip_select > 3) {
334 pr_debug("%s: cs%d?\n", dev_name(&spi->dev), spi->chip_select);
335 status = -ENODEV;
336 goto done;
337 }
338
339 bits = spi->bits_per_word;
340 if (t != NULL && t->bits_per_word)
341 bits = t->bits_per_word;
342
343 if (bits > 16) {
344 pr_debug("%s: wordsize %d?\n", dev_name(&spi->dev), bits);
345 status = -ENODEV;
346 goto done;
347 }
348 ust->bits_per_word = bits;
349
350 /* mode 0..3, clock inverted separately;
351 * standard nCS signaling;
352 * don't treat DI=high as "not ready"
353 */
354 if (spi->mode & SPI_CS_HIGH)
355 flags |= UWIRE_CS_ACTIVE_HIGH;
356
357 if (spi->mode & SPI_CPOL)
358 flags |= UWIRE_CLK_INVERTED;
359
360 switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
361 case SPI_MODE_0:
362 case SPI_MODE_3:
363 flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
364 break;
365 case SPI_MODE_1:
366 case SPI_MODE_2:
367 flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
368 break;
369 }
370
371 /* assume it's already enabled */
372 rate = clk_get_rate(uwire->ck);
373
374 hz = spi->max_speed_hz;
375 if (t != NULL && t->speed_hz)
376 hz = t->speed_hz;
377
378 if (!hz) {
379 pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
380 status = -EINVAL;
381 goto done;
382 }
383
384 /* F_INT = mpu_xor_clk / DIV1 */
385 for (div1_idx = 0; div1_idx < 4; div1_idx++) {
386 switch (div1_idx) {
387 case 0:
388 div1 = 2;
389 break;
390 case 1:
391 div1 = 4;
392 break;
393 case 2:
394 div1 = 7;
395 break;
396 default:
397 case 3:
398 div1 = 10;
399 break;
400 }
401 div2 = (rate / div1 + hz - 1) / hz;
402 if (div2 <= 8)
403 break;
404 }
405 if (div1_idx == 4) {
406 pr_debug("%s: lowest clock %ld, need %d\n",
407 dev_name(&spi->dev), rate / 10 / 8, hz);
408 status = -EDOM;
409 goto done;
410 }
411
412 /* we have to cache this and reset in uwire_chipselect as this is a
413 * global parameter and another uwire device can change it under
414 * us */
415 ust->div1_idx = div1_idx;
416 uwire_set_clk1_div(div1_idx);
417
418 rate /= div1;
419
420 switch (div2) {
421 case 0:
422 case 1:
423 case 2:
424 flags |= UWIRE_FREQ_DIV_2;
425 rate /= 2;
426 break;
427 case 3:
428 case 4:
429 flags |= UWIRE_FREQ_DIV_4;
430 rate /= 4;
431 break;
432 case 5:
433 case 6:
434 case 7:
435 case 8:
436 flags |= UWIRE_FREQ_DIV_8;
437 rate /= 8;
438 break;
439 }
440 omap_uwire_configure_mode(spi->chip_select, flags);
441 pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
442 __func__, flags,
443 clk_get_rate(uwire->ck) / 1000,
444 rate / 1000);
445 status = 0;
446 done:
447 return status;
448 }
449
450 static int uwire_setup(struct spi_device *spi)
451 {
452 struct uwire_state *ust = spi->controller_state;
453
454 if (ust == NULL) {
455 ust = kzalloc(sizeof(*ust), GFP_KERNEL);
456 if (ust == NULL)
457 return -ENOMEM;
458 spi->controller_state = ust;
459 }
460
461 return uwire_setup_transfer(spi, NULL);
462 }
463
464 static void uwire_cleanup(struct spi_device *spi)
465 {
466 kfree(spi->controller_state);
467 }
468
469 static void uwire_off(struct uwire_spi *uwire)
470 {
471 uwire_write_reg(UWIRE_SR3, 0);
472 clk_disable(uwire->ck);
473 clk_put(uwire->ck);
474 spi_master_put(uwire->bitbang.master);
475 }
476
477 static int __init uwire_probe(struct platform_device *pdev)
478 {
479 struct spi_master *master;
480 struct uwire_spi *uwire;
481 int status;
482
483 master = spi_alloc_master(&pdev->dev, sizeof *uwire);
484 if (!master)
485 return -ENODEV;
486
487 uwire = spi_master_get_devdata(master);
488
489 uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
490 if (!uwire_base) {
491 dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
492 spi_master_put(master);
493 return -ENOMEM;
494 }
495
496 dev_set_drvdata(&pdev->dev, uwire);
497
498 uwire->ck = clk_get(&pdev->dev, "fck");
499 if (IS_ERR(uwire->ck)) {
500 status = PTR_ERR(uwire->ck);
501 dev_dbg(&pdev->dev, "no functional clock?\n");
502 spi_master_put(master);
503 return status;
504 }
505 clk_enable(uwire->ck);
506
507 if (cpu_is_omap730())
508 uwire_idx_shift = 1;
509 else
510 uwire_idx_shift = 2;
511
512 uwire_write_reg(UWIRE_SR3, 1);
513
514 /* the spi->mode bits understood by this driver: */
515 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
516
517 master->flags = SPI_MASTER_HALF_DUPLEX;
518
519 master->bus_num = 2; /* "official" */
520 master->num_chipselect = 4;
521 master->setup = uwire_setup;
522 master->cleanup = uwire_cleanup;
523
524 uwire->bitbang.master = master;
525 uwire->bitbang.chipselect = uwire_chipselect;
526 uwire->bitbang.setup_transfer = uwire_setup_transfer;
527 uwire->bitbang.txrx_bufs = uwire_txrx;
528
529 status = spi_bitbang_start(&uwire->bitbang);
530 if (status < 0) {
531 uwire_off(uwire);
532 iounmap(uwire_base);
533 }
534 return status;
535 }
536
537 static int __exit uwire_remove(struct platform_device *pdev)
538 {
539 struct uwire_spi *uwire = dev_get_drvdata(&pdev->dev);
540 int status;
541
542 // FIXME remove all child devices, somewhere ...
543
544 status = spi_bitbang_stop(&uwire->bitbang);
545 uwire_off(uwire);
546 iounmap(uwire_base);
547 return status;
548 }
549
550 /* work with hotplug and coldplug */
551 MODULE_ALIAS("platform:omap_uwire");
552
553 static struct platform_driver uwire_driver = {
554 .driver = {
555 .name = "omap_uwire",
556 .owner = THIS_MODULE,
557 },
558 .remove = __exit_p(uwire_remove),
559 // suspend ... unuse ck
560 // resume ... use ck
561 };
562
563 static int __init omap_uwire_init(void)
564 {
565 /* FIXME move these into the relevant board init code. also, include
566 * H3 support; it uses tsc2101 like H2 (on a different chipselect).
567 */
568
569 if (machine_is_omap_h2()) {
570 /* defaults: W21 SDO, U18 SDI, V19 SCL */
571 omap_cfg_reg(N14_1610_UWIRE_CS0);
572 omap_cfg_reg(N15_1610_UWIRE_CS1);
573 }
574 if (machine_is_omap_perseus2()) {
575 /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
576 int val = omap_readl(OMAP730_IO_CONF_9) & ~0x00EEE000;
577 omap_writel(val | 0x00AAA000, OMAP730_IO_CONF_9);
578 }
579
580 return platform_driver_probe(&uwire_driver, uwire_probe);
581 }
582
583 static void __exit omap_uwire_exit(void)
584 {
585 platform_driver_unregister(&uwire_driver);
586 }
587
588 subsys_initcall(omap_uwire_init);
589 module_exit(omap_uwire_exit);
590
591 MODULE_LICENSE("GPL");
592
593
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