1 /*
2 * linux/drivers/serial/s3c2410.c
3 *
4 * Driver for onboard UARTs on the Samsung S3C24XX
5 *
6 * Based on drivers/char/serial.c and drivers/char/21285.c
7 *
8 * Ben Dooks, (c) 2003 Simtec Electronics
9 *
10 * Changelog:
11 *
12 * 22-Jul-2004 BJD Finished off device rewrite
13 *
14 * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
15 * problems with baud rate and loss of IR settings. Update
16 * to add configuration via platform_device structure
17 *
18 * 28-Sep-2004 BJD Re-write for the following items
19 * - S3C2410 and S3C2440 serial support
20 * - Power Management support
21 * - Fix console via IrDA devices
22 * - SysReq (Herbert Pötzl)
23 * - Break character handling (Herbert Pötzl)
24 * - spin-lock initialisation (Dimitry Andric)
25 * - added clock control
26 * - updated init code to use platform_device info
27 */
28
29 /* Hote on 2410 error handling
30 *
31 * The s3c2410 manual has a love/hate affair with the contents of the
32 * UERSTAT register in the UART blocks, and keeps marking some of the
33 * error bits as reserved. Having checked with the s3c2410x01,
34 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
35 * feature from the latter versions of the manual.
36 *
37 * If it becomes aparrent that latter versions of the 2410 remove these
38 * bits, then action will have to be taken to differentiate the versions
39 * and change the policy on BREAK
40 *
41 * BJD, 04-Nov-2004
42 */
43
44 #include <linux/config.h>
45
46 #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
47 #define SUPPORT_SYSRQ
48 #endif
49
50 #include <linux/module.h>
51 #include <linux/ioport.h>
52 #include <linux/device.h>
53 #include <linux/init.h>
54 #include <linux/sysrq.h>
55 #include <linux/console.h>
56 #include <linux/tty.h>
57 #include <linux/tty_flip.h>
58 #include <linux/serial_core.h>
59 #include <linux/serial.h>
60 #include <linux/delay.h>
61
62 #include <asm/io.h>
63 #include <asm/irq.h>
64
65 #include <asm/hardware.h>
66 #include <asm/hardware/clock.h>
67
68 #include <asm/arch/regs-serial.h>
69 #include <asm/arch/regs-gpio.h>
70
71 #include <asm/mach-types.h>
72
73 /* structures */
74
75 struct s3c24xx_uart_info {
76 char *name;
77 unsigned int type;
78 unsigned int fifosize;
79 unsigned long rx_fifomask;
80 unsigned long rx_fifoshift;
81 unsigned long rx_fifofull;
82 unsigned long tx_fifomask;
83 unsigned long tx_fifoshift;
84 unsigned long tx_fifofull;
85
86 /* clock source control */
87
88 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
89 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
90 };
91
92 struct s3c24xx_uart_port {
93 unsigned char rx_claimed;
94 unsigned char tx_claimed;
95
96 struct s3c24xx_uart_info *info;
97 struct s3c24xx_uart_clksrc *clksrc;
98 struct clk *clk;
99 struct clk *baudclk;
100 struct uart_port port;
101 };
102
103
104 /* configuration defines */
105
106 #if 0
107 #if 1
108 /* send debug to the low-level output routines */
109
110 extern void printascii(const char *);
111
112 static void
113 s3c24xx_serial_dbg(const char *fmt, ...)
114 {
115 va_list va;
116 char buff[256];
117
118 va_start(va, fmt);
119 vsprintf(buff, fmt, va);
120 va_end(va);
121
122 printascii(buff);
123 }
124
125 #define dbg(x...) s3c24xx_serial_dbg(x)
126
127 #else
128 #define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
129 #endif
130 #else /* no debug */
131 #define dbg(x...) do {} while(0)
132 #endif
133
134 /* UART name and device definitions */
135
136 #define S3C24XX_SERIAL_NAME "ttySAC"
137 #define S3C24XX_SERIAL_DEVFS "tts/"
138 #define S3C24XX_SERIAL_MAJOR 204
139 #define S3C24XX_SERIAL_MINOR 64
140
141
142 /* conversion functions */
143
144 #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
145 #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
146
147 /* we can support 3 uarts, but not always use them */
148
149 #define NR_PORTS (3)
150
151 /* port irq numbers */
152
153 #define TX_IRQ(port) ((port)->irq + 1)
154 #define RX_IRQ(port) ((port)->irq)
155
156 /* register access controls */
157
158 #define portaddr(port, reg) ((port)->membase + (reg))
159
160 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
161 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
162
163 #define wr_regb(port, reg, val) \
164 do { __raw_writeb(val, portaddr(port, reg)); } while(0)
165
166 #define wr_regl(port, reg, val) \
167 do { __raw_writel(val, portaddr(port, reg)); } while(0)
168
169 /* macros to change one thing to another */
170
171 #define tx_enabled(port) ((port)->unused[0])
172 #define rx_enabled(port) ((port)->unused[1])
173
174 /* flag to ignore all characters comming in */
175 #define RXSTAT_DUMMY_READ (0x10000000)
176
177 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
178 {
179 return container_of(port, struct s3c24xx_uart_port, port);
180 }
181
182 /* translate a port to the device name */
183
184 static inline char *s3c24xx_serial_portname(struct uart_port *port)
185 {
186 return to_platform_device(port->dev)->name;
187 }
188
189 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
190 {
191 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
192 }
193
194 static void s3c24xx_serial_rx_enable(struct uart_port *port)
195 {
196 unsigned long flags;
197 unsigned int ucon, ufcon;
198 int count = 10000;
199
200 spin_lock_irqsave(&port->lock, flags);
201
202 while (--count && !s3c24xx_serial_txempty_nofifo(port))
203 udelay(100);
204
205 ufcon = rd_regl(port, S3C2410_UFCON);
206 ufcon |= S3C2410_UFCON_RESETRX;
207 wr_regl(port, S3C2410_UFCON, ufcon);
208
209 ucon = rd_regl(port, S3C2410_UCON);
210 ucon |= S3C2410_UCON_RXIRQMODE;
211 wr_regl(port, S3C2410_UCON, ucon);
212
213 rx_enabled(port) = 1;
214 spin_unlock_irqrestore(&port->lock, flags);
215 }
216
217 static void s3c24xx_serial_rx_disable(struct uart_port *port)
218 {
219 unsigned long flags;
220 unsigned int ucon;
221
222 spin_lock_irqsave(&port->lock, flags);
223
224 ucon = rd_regl(port, S3C2410_UCON);
225 ucon &= ~S3C2410_UCON_RXIRQMODE;
226 wr_regl(port, S3C2410_UCON, ucon);
227
228 rx_enabled(port) = 0;
229 spin_unlock_irqrestore(&port->lock, flags);
230 }
231
232 static void
233 s3c24xx_serial_stop_tx(struct uart_port *port, unsigned int tty_stop)
234 {
235 if (tx_enabled(port)) {
236 disable_irq(TX_IRQ(port));
237 tx_enabled(port) = 0;
238 if (port->flags & UPF_CONS_FLOW)
239 s3c24xx_serial_rx_enable(port);
240 }
241 }
242
243 static void
244 s3c24xx_serial_start_tx(struct uart_port *port, unsigned int tty_start)
245 {
246 if (!tx_enabled(port)) {
247 if (port->flags & UPF_CONS_FLOW)
248 s3c24xx_serial_rx_disable(port);
249
250 enable_irq(TX_IRQ(port));
251 tx_enabled(port) = 1;
252 }
253 }
254
255
256 static void s3c24xx_serial_stop_rx(struct uart_port *port)
257 {
258 if (rx_enabled(port)) {
259 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
260 disable_irq(RX_IRQ(port));
261 rx_enabled(port) = 0;
262 }
263 }
264
265 static void s3c24xx_serial_enable_ms(struct uart_port *port)
266 {
267 }
268
269 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
270 {
271 return to_ourport(port)->info;
272 }
273
274 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
275 {
276 if (port->dev == NULL)
277 return NULL;
278
279 return (struct s3c2410_uartcfg *)port->dev->platform_data;
280 }
281
282 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
283 unsigned long ufstat)
284 {
285 struct s3c24xx_uart_info *info = ourport->info;
286
287 if (ufstat & info->rx_fifofull)
288 return info->fifosize;
289
290 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
291 }
292
293
294 /* ? - where has parity gone?? */
295 #define S3C2410_UERSTAT_PARITY (0x1000)
296
297 static irqreturn_t
298 s3c24xx_serial_rx_chars(int irq, void *dev_id, struct pt_regs *regs)
299 {
300 struct s3c24xx_uart_port *ourport = dev_id;
301 struct uart_port *port = &ourport->port;
302 struct tty_struct *tty = port->info->tty;
303 unsigned int ufcon, ch, flag, ufstat, uerstat;
304 int max_count = 64;
305
306 while (max_count-- > 0) {
307 ufcon = rd_regl(port, S3C2410_UFCON);
308 ufstat = rd_regl(port, S3C2410_UFSTAT);
309
310 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
311 break;
312
313 if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
314 if (tty->low_latency)
315 tty_flip_buffer_push(tty);
316
317 /*
318 * If this failed then we will throw away the
319 * bytes but must do so to clear interrupts
320 */
321 }
322
323 uerstat = rd_regl(port, S3C2410_UERSTAT);
324 ch = rd_regb(port, S3C2410_URXH);
325
326 if (port->flags & UPF_CONS_FLOW) {
327 int txe = s3c24xx_serial_txempty_nofifo(port);
328
329 if (rx_enabled(port)) {
330 if (!txe) {
331 rx_enabled(port) = 0;
332 continue;
333 }
334 } else {
335 if (txe) {
336 ufcon |= S3C2410_UFCON_RESETRX;
337 wr_regl(port, S3C2410_UFCON, ufcon);
338 rx_enabled(port) = 1;
339 goto out;
340 }
341 continue;
342 }
343 }
344
345 /* insert the character into the buffer */
346
347 flag = TTY_NORMAL;
348 port->icount.rx++;
349
350 if (uerstat & S3C2410_UERSTAT_ANY) {
351 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
352 ch, uerstat);
353
354 /* check for break */
355 if (uerstat & S3C2410_UERSTAT_BREAK) {
356 dbg("break!\n");
357 port->icount.brk++;
358 if (uart_handle_break(port))
359 goto ignore_char;
360 }
361
362 if (uerstat & S3C2410_UERSTAT_FRAME)
363 port->icount.frame++;
364 if (uerstat & S3C2410_UERSTAT_OVERRUN)
365 port->icount.overrun++;
366
367 uerstat &= port->read_status_mask;
368
369 if (uerstat & S3C2410_UERSTAT_BREAK)
370 flag = TTY_BREAK;
371 else if (uerstat & S3C2410_UERSTAT_PARITY)
372 flag = TTY_PARITY;
373 else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
374 flag = TTY_FRAME;
375 }
376
377 if (uart_handle_sysrq_char(port, ch, regs))
378 goto ignore_char;
379
380 if ((uerstat & port->ignore_status_mask) == 0) {
381 tty_insert_flip_char(tty, ch, flag);
382 }
383
384 if ((uerstat & S3C2410_UERSTAT_OVERRUN) &&
385 tty->flip.count < TTY_FLIPBUF_SIZE) {
386 /*
387 * Overrun is special, since it's reported
388 * immediately, and doesn't affect the current
389 * character.
390 */
391
392 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
393 }
394
395 ignore_char:
396 continue;
397 }
398 tty_flip_buffer_push(tty);
399
400 out:
401 return IRQ_HANDLED;
402 }
403
404 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id, struct pt_regs *regs)
405 {
406 struct s3c24xx_uart_port *ourport = id;
407 struct uart_port *port = &ourport->port;
408 struct circ_buf *xmit = &port->info->xmit;
409 int count = 256;
410
411 if (port->x_char) {
412 wr_regb(port, S3C2410_UTXH, port->x_char);
413 port->icount.tx++;
414 port->x_char = 0;
415 goto out;
416 }
417
418 /* if there isnt anything more to transmit, or the uart is now
419 * stopped, disable the uart and exit
420 */
421
422 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
423 s3c24xx_serial_stop_tx(port, 0);
424 goto out;
425 }
426
427 /* try and drain the buffer... */
428
429 while (!uart_circ_empty(xmit) && count-- > 0) {
430 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
431 break;
432
433 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
434 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
435 port->icount.tx++;
436 }
437
438 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
439 uart_write_wakeup(port);
440
441 if (uart_circ_empty(xmit))
442 s3c24xx_serial_stop_tx(port, 0);
443
444 out:
445 return IRQ_HANDLED;
446 }
447
448 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
449 {
450 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
451 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
452 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
453
454 if (ufcon & S3C2410_UFCON_FIFOMODE) {
455 if ((ufstat & info->tx_fifomask) != 0 ||
456 (ufstat & info->tx_fifofull))
457 return 0;
458
459 return 1;
460 }
461
462 return s3c24xx_serial_txempty_nofifo(port);
463 }
464
465 /* no modem control lines */
466 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
467 {
468 unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
469
470 if (umstat & S3C2410_UMSTAT_CTS)
471 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
472 else
473 return TIOCM_CAR | TIOCM_DSR;
474 }
475
476 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
477 {
478 /* todo - possibly remove AFC and do manual CTS */
479 }
480
481 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
482 {
483 unsigned long flags;
484 unsigned int ucon;
485
486 spin_lock_irqsave(&port->lock, flags);
487
488 ucon = rd_regl(port, S3C2410_UCON);
489
490 if (break_state)
491 ucon |= S3C2410_UCON_SBREAK;
492 else
493 ucon &= ~S3C2410_UCON_SBREAK;
494
495 wr_regl(port, S3C2410_UCON, ucon);
496
497 spin_unlock_irqrestore(&port->lock, flags);
498 }
499
500 static void s3c24xx_serial_shutdown(struct uart_port *port)
501 {
502 struct s3c24xx_uart_port *ourport = to_ourport(port);
503
504 if (ourport->tx_claimed) {
505 free_irq(TX_IRQ(port), ourport);
506 tx_enabled(port) = 0;
507 ourport->tx_claimed = 0;
508 }
509
510 if (ourport->rx_claimed) {
511 free_irq(RX_IRQ(port), ourport);
512 ourport->rx_claimed = 0;
513 rx_enabled(port) = 0;
514 }
515 }
516
517
518 static int s3c24xx_serial_startup(struct uart_port *port)
519 {
520 struct s3c24xx_uart_port *ourport = to_ourport(port);
521 unsigned long flags;
522 int ret;
523
524 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
525 port->mapbase, port->membase);
526
527 local_irq_save(flags);
528
529 rx_enabled(port) = 1;
530
531 ret = request_irq(RX_IRQ(port),
532 s3c24xx_serial_rx_chars, 0,
533 s3c24xx_serial_portname(port), ourport);
534
535 if (ret != 0) {
536 printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
537 return ret;
538 }
539
540 ourport->rx_claimed = 1;
541
542 dbg("requesting tx irq...\n");
543
544 tx_enabled(port) = 1;
545
546 ret = request_irq(TX_IRQ(port),
547 s3c24xx_serial_tx_chars, 0,
548 s3c24xx_serial_portname(port), ourport);
549
550 if (ret) {
551 printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
552 goto err;
553 }
554
555 ourport->tx_claimed = 1;
556
557 dbg("s3c24xx_serial_startup ok\n");
558
559 /* the port reset code should have done the correct
560 * register setup for the port controls */
561
562 local_irq_restore(flags);
563 return ret;
564
565 err:
566 s3c24xx_serial_shutdown(port);
567 local_irq_restore(flags);
568 return ret;
569 }
570
571 /* power power management control */
572
573 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
574 unsigned int old)
575 {
576 struct s3c24xx_uart_port *ourport = to_ourport(port);
577
578 switch (level) {
579 case 3:
580 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
581 clk_disable(ourport->baudclk);
582
583 clk_disable(ourport->clk);
584 break;
585
586 case 0:
587 clk_enable(ourport->clk);
588
589 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
590 clk_enable(ourport->baudclk);
591
592 break;
593 default:
594 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
595 }
596 }
597
598 /* baud rate calculation
599 *
600 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
601 * of different sources, including the peripheral clock ("pclk") and an
602 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
603 * with a programmable extra divisor.
604 *
605 * The following code goes through the clock sources, and calculates the
606 * baud clocks (and the resultant actual baud rates) and then tries to
607 * pick the closest one and select that.
608 *
609 * NOTES:
610 * 1) there is no current code to properly select/deselect FCLK on
611 * the s3c2440, so only specify FCLK or non-FCLK in the clock
612 * sources for the UART
613 *
614 */
615
616
617 #define MAX_CLKS (8)
618
619 static struct s3c24xx_uart_clksrc tmp_clksrc = {
620 .name = "pclk",
621 .min_baud = 0,
622 .max_baud = 0,
623 .divisor = 1,
624 };
625
626 static inline int
627 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
628 {
629 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
630
631 return (info->get_clksrc)(port, c);
632 }
633
634 static inline int
635 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
636 {
637 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
638
639 return (info->set_clksrc)(port, c);
640 }
641
642 struct baud_calc {
643 struct s3c24xx_uart_clksrc *clksrc;
644 unsigned int calc;
645 unsigned int quot;
646 struct clk *src;
647 };
648
649 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
650 struct uart_port *port,
651 struct s3c24xx_uart_clksrc *clksrc,
652 unsigned int baud)
653 {
654 unsigned long rate;
655
656 calc->src = clk_get(port->dev, clksrc->name);
657 if (calc->src == NULL || IS_ERR(calc->src))
658 return 0;
659
660 rate = clk_get_rate(calc->src);
661
662 calc->clksrc = clksrc;
663 calc->quot = (rate + (8 * baud)) / (16 * baud);
664 calc->calc = (rate / (calc->quot * 16));
665
666 calc->quot--;
667 return 1;
668 }
669
670 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
671 struct s3c24xx_uart_clksrc **clksrc,
672 struct clk **clk,
673 unsigned int baud)
674 {
675 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
676 struct s3c24xx_uart_clksrc *clkp;
677 struct baud_calc res[MAX_CLKS];
678 struct baud_calc *resptr, *best, *sptr;
679 int i;
680
681 clkp = cfg->clocks;
682 best = NULL;
683
684 if (cfg->clocks_size < 2) {
685 if (cfg->clocks_size == 0)
686 clkp = &tmp_clksrc;
687
688 s3c24xx_serial_calcbaud(res, port, clkp, baud);
689 best = res;
690 resptr = best + 1;
691 } else {
692 resptr = res;
693
694 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
695 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
696 resptr++;
697 }
698 }
699
700 /* ok, we now need to select the best clock we found */
701
702 if (!best) {
703 unsigned int deviation = (1<<30)|((1<<30)-1);
704 int calc_deviation;
705
706 for (sptr = res; sptr < resptr; sptr++) {
707 printk(KERN_DEBUG
708 "found clk %p (%s) quot %d, calc %d\n",
709 sptr->clksrc, sptr->clksrc->name,
710 sptr->quot, sptr->calc);
711
712 calc_deviation = baud - sptr->calc;
713 if (calc_deviation < 0)
714 calc_deviation = -calc_deviation;
715
716 if (calc_deviation < deviation) {
717 best = sptr;
718 deviation = calc_deviation;
719 }
720 }
721
722 printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
723 }
724
725 printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
726 best->clksrc, best->clksrc->name, best->quot, best->calc);
727
728 /* store results to pass back */
729
730 *clksrc = best->clksrc;
731 *clk = best->src;
732
733 return best->quot;
734 }
735
736 static void s3c24xx_serial_set_termios(struct uart_port *port,
737 struct termios *termios,
738 struct termios *old)
739 {
740 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
741 struct s3c24xx_uart_port *ourport = to_ourport(port);
742 struct s3c24xx_uart_clksrc *clksrc;
743 struct clk *clk;
744 unsigned long flags;
745 unsigned int baud, quot;
746 unsigned int ulcon;
747 unsigned int umcon;
748
749 /*
750 * We don't support modem control lines.
751 */
752 termios->c_cflag &= ~(HUPCL | CMSPAR);
753 termios->c_cflag |= CLOCAL;
754
755 /*
756 * Ask the core to calculate the divisor for us.
757 */
758
759 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
760
761 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
762 quot = port->custom_divisor;
763 else
764 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
765
766 /* check to see if we need to change clock source */
767
768 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
769 s3c24xx_serial_setsource(port, clksrc);
770
771 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
772 clk_disable(ourport->baudclk);
773 clk_unuse(ourport->baudclk);
774 ourport->baudclk = NULL;
775 }
776
777 clk_use(clk);
778 clk_enable(clk);
779
780 ourport->clksrc = clksrc;
781 ourport->baudclk = clk;
782 }
783
784 switch (termios->c_cflag & CSIZE) {
785 case CS5:
786 dbg("config: 5bits/char\n");
787 ulcon = S3C2410_LCON_CS5;
788 break;
789 case CS6:
790 dbg("config: 6bits/char\n");
791 ulcon = S3C2410_LCON_CS6;
792 break;
793 case CS7:
794 dbg("config: 7bits/char\n");
795 ulcon = S3C2410_LCON_CS7;
796 break;
797 case CS8:
798 default:
799 dbg("config: 8bits/char\n");
800 ulcon = S3C2410_LCON_CS8;
801 break;
802 }
803
804 /* preserve original lcon IR settings */
805 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
806
807 if (termios->c_cflag & CSTOPB)
808 ulcon |= S3C2410_LCON_STOPB;
809
810 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
811
812 if (termios->c_cflag & PARENB) {
813 if (termios->c_cflag & PARODD)
814 ulcon |= S3C2410_LCON_PODD;
815 else
816 ulcon |= S3C2410_LCON_PEVEN;
817 } else {
818 ulcon |= S3C2410_LCON_PNONE;
819 }
820
821 spin_lock_irqsave(&port->lock, flags);
822
823 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
824
825 wr_regl(port, S3C2410_ULCON, ulcon);
826 wr_regl(port, S3C2410_UBRDIV, quot);
827 wr_regl(port, S3C2410_UMCON, umcon);
828
829 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
830 rd_regl(port, S3C2410_ULCON),
831 rd_regl(port, S3C2410_UCON),
832 rd_regl(port, S3C2410_UFCON));
833
834 /*
835 * Update the per-port timeout.
836 */
837 uart_update_timeout(port, termios->c_cflag, baud);
838
839 /*
840 * Which character status flags are we interested in?
841 */
842 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
843 if (termios->c_iflag & INPCK)
844 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
845
846 /*
847 * Which character status flags should we ignore?
848 */
849 port->ignore_status_mask = 0;
850 if (termios->c_iflag & IGNPAR)
851 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
852 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
853 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
854
855 /*
856 * Ignore all characters if CREAD is not set.
857 */
858 if ((termios->c_cflag & CREAD) == 0)
859 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
860
861 spin_unlock_irqrestore(&port->lock, flags);
862 }
863
864 static const char *s3c24xx_serial_type(struct uart_port *port)
865 {
866 switch (port->type) {
867 case PORT_S3C2410:
868 return "S3C2410";
869 case PORT_S3C2440:
870 return "S3C2440";
871 default:
872 return NULL;
873 }
874 }
875
876 #define MAP_SIZE (0x100)
877
878 static void s3c24xx_serial_release_port(struct uart_port *port)
879 {
880 release_mem_region(port->mapbase, MAP_SIZE);
881 }
882
883 static int s3c24xx_serial_request_port(struct uart_port *port)
884 {
885 char *name = s3c24xx_serial_portname(port);
886 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
887 }
888
889 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
890 {
891 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
892
893 if (flags & UART_CONFIG_TYPE &&
894 s3c24xx_serial_request_port(port) == 0)
895 port->type = info->type;
896 }
897
898 /*
899 * verify the new serial_struct (for TIOCSSERIAL).
900 */
901 static int
902 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
903 {
904 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
905
906 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
907 return -EINVAL;
908
909 return 0;
910 }
911
912
913 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
914
915 static struct console s3c24xx_serial_console;
916
917 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
918 #else
919 #define S3C24XX_SERIAL_CONSOLE NULL
920 #endif
921
922 static struct uart_ops s3c24xx_serial_ops = {
923 .pm = s3c24xx_serial_pm,
924 .tx_empty = s3c24xx_serial_tx_empty,
925 .get_mctrl = s3c24xx_serial_get_mctrl,
926 .set_mctrl = s3c24xx_serial_set_mctrl,
927 .stop_tx = s3c24xx_serial_stop_tx,
928 .start_tx = s3c24xx_serial_start_tx,
929 .stop_rx = s3c24xx_serial_stop_rx,
930 .enable_ms = s3c24xx_serial_enable_ms,
931 .break_ctl = s3c24xx_serial_break_ctl,
932 .startup = s3c24xx_serial_startup,
933 .shutdown = s3c24xx_serial_shutdown,
934 .set_termios = s3c24xx_serial_set_termios,
935 .type = s3c24xx_serial_type,
936 .release_port = s3c24xx_serial_release_port,
937 .request_port = s3c24xx_serial_request_port,
938 .config_port = s3c24xx_serial_config_port,
939 .verify_port = s3c24xx_serial_verify_port,
940 };
941
942
943 static struct uart_driver s3c24xx_uart_drv = {
944 .owner = THIS_MODULE,
945 .dev_name = "s3c2410_serial",
946 .nr = 3,
947 .cons = S3C24XX_SERIAL_CONSOLE,
948 .driver_name = S3C24XX_SERIAL_NAME,
949 .devfs_name = S3C24XX_SERIAL_DEVFS,
950 .major = S3C24XX_SERIAL_MAJOR,
951 .minor = S3C24XX_SERIAL_MINOR,
952 };
953
954 static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
955 [0] = {
956 .port = {
957 .lock = SPIN_LOCK_UNLOCKED,
958 .membase = 0,
959 .mapbase = 0,
960 .iotype = UPIO_MEM,
961 .irq = IRQ_S3CUART_RX0,
962 .uartclk = 0,
963 .fifosize = 16,
964 .ops = &s3c24xx_serial_ops,
965 .flags = UPF_BOOT_AUTOCONF,
966 .line = 0,
967 }
968 },
969 [1] = {
970 .port = {
971 .lock = SPIN_LOCK_UNLOCKED,
972 .membase = 0,
973 .mapbase = 0,
974 .iotype = UPIO_MEM,
975 .irq = IRQ_S3CUART_RX1,
976 .uartclk = 0,
977 .fifosize = 16,
978 .ops = &s3c24xx_serial_ops,
979 .flags = UPF_BOOT_AUTOCONF,
980 .line = 1,
981 }
982 },
983 #if NR_PORTS > 2
984
985 [2] = {
986 .port = {
987 .lock = SPIN_LOCK_UNLOCKED,
988 .membase = 0,
989 .mapbase = 0,
990 .iotype = UPIO_MEM,
991 .irq = IRQ_S3CUART_RX2,
992 .uartclk = 0,
993 .fifosize = 16,
994 .ops = &s3c24xx_serial_ops,
995 .flags = UPF_BOOT_AUTOCONF,
996 .line = 2,
997 }
998 }
999 #endif
1000 };
1001
1002
1003 static int s3c24xx_serial_resetport(struct uart_port *port,
1004 struct s3c2410_uartcfg *cfg)
1005 {
1006 /* ensure registers are setup */
1007
1008 dbg("s3c24xx_serial_resetport: port=%p (%08lx), cfg=%p\n",
1009 port, port->mapbase, cfg);
1010
1011 wr_regl(port, S3C2410_UCON, cfg->ucon);
1012 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1013
1014 /* reset both fifos */
1015
1016 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1017 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1018
1019 return 0;
1020 }
1021
1022 /* s3c24xx_serial_init_port
1023 *
1024 * initialise a single serial port from the platform device given
1025 */
1026
1027 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1028 struct s3c24xx_uart_info *info,
1029 struct platform_device *platdev)
1030 {
1031 struct uart_port *port = &ourport->port;
1032 struct s3c2410_uartcfg *cfg;
1033 struct resource *res;
1034
1035 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1036
1037 if (platdev == NULL)
1038 return -ENODEV;
1039
1040 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1041
1042 if (port->mapbase != 0)
1043 return 0;
1044
1045 if (cfg->hwport > 3)
1046 return -EINVAL;
1047
1048 /* setup info for port */
1049 port->dev = &platdev->dev;
1050 ourport->info = info;
1051
1052 /* copy the info in from provided structure */
1053 ourport->port.fifosize = info->fifosize;
1054
1055 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1056
1057 port->uartclk = 1;
1058
1059 if (cfg->uart_flags & UPF_CONS_FLOW) {
1060 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1061 port->flags |= UPF_CONS_FLOW;
1062 }
1063
1064 /* sort our the physical and virtual addresses for each UART */
1065
1066 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1067 if (res == NULL) {
1068 printk(KERN_ERR "failed to find memory resource for uart\n");
1069 return -EINVAL;
1070 }
1071
1072 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1073
1074 port->mapbase = res->start;
1075 port->membase = (void __iomem *)(res->start - S3C2410_PA_UART);
1076 port->membase += S3C2410_VA_UART;
1077 port->irq = platform_get_irq(platdev, 0);
1078
1079 ourport->clk = clk_get(&platdev->dev, "uart");
1080
1081 if (ourport->clk != NULL && !IS_ERR(ourport->clk))
1082 clk_use(ourport->clk);
1083
1084 dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
1085 port->mapbase, port->membase, port->irq, port->uartclk);
1086
1087 /* reset the fifos (and setup the uart) */
1088 s3c24xx_serial_resetport(port, cfg);
1089 return 0;
1090 }
1091
1092 /* Device driver serial port probe */
1093
1094 static int probe_index = 0;
1095
1096 int s3c24xx_serial_probe(struct device *_dev,
1097 struct s3c24xx_uart_info *info)
1098 {
1099 struct s3c24xx_uart_port *ourport;
1100 struct platform_device *dev = to_platform_device(_dev);
1101 int ret;
1102
1103 dbg("s3c24xx_serial_probe(%p, %p) %d\n", _dev, info, probe_index);
1104
1105 ourport = &s3c24xx_serial_ports[probe_index];
1106 probe_index++;
1107
1108 dbg("%s: initialising port %p...\n", __FUNCTION__, ourport);
1109
1110 ret = s3c24xx_serial_init_port(ourport, info, dev);
1111 if (ret < 0)
1112 goto probe_err;
1113
1114 dbg("%s: adding port\n", __FUNCTION__);
1115 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1116 dev_set_drvdata(_dev, &ourport->port);
1117
1118 return 0;
1119
1120 probe_err:
1121 return ret;
1122 }
1123
1124 int s3c24xx_serial_remove(struct device *_dev)
1125 {
1126 struct uart_port *port = s3c24xx_dev_to_port(_dev);
1127
1128 if (port)
1129 uart_remove_one_port(&s3c24xx_uart_drv, port);
1130
1131 return 0;
1132 }
1133
1134 /* UART power management code */
1135
1136 #ifdef CONFIG_PM
1137
1138 int s3c24xx_serial_suspend(struct device *dev, u32 state, u32 level)
1139 {
1140 struct uart_port *port = s3c24xx_dev_to_port(dev);
1141
1142 if (port && level == SUSPEND_DISABLE)
1143 uart_suspend_port(&s3c24xx_uart_drv, port);
1144
1145 return 0;
1146 }
1147
1148 int s3c24xx_serial_resume(struct device *dev, u32 level)
1149 {
1150 struct uart_port *port = s3c24xx_dev_to_port(dev);
1151 struct s3c24xx_uart_port *ourport = to_ourport(port);
1152
1153 if (port && level == RESUME_ENABLE) {
1154 clk_enable(ourport->clk);
1155 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1156 clk_disable(ourport->clk);
1157
1158 uart_resume_port(&s3c24xx_uart_drv, port);
1159 }
1160
1161 return 0;
1162 }
1163
1164 #else
1165 #define s3c24xx_serial_suspend NULL
1166 #define s3c24xx_serial_resume NULL
1167 #endif
1168
1169 int s3c24xx_serial_init(struct device_driver *drv,
1170 struct s3c24xx_uart_info *info)
1171 {
1172 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1173 return driver_register(drv);
1174 }
1175
1176
1177 /* now comes the code to initialise either the s3c2410 or s3c2440 serial
1178 * port information
1179 */
1180
1181 /* cpu specific variations on the serial port support */
1182
1183 #ifdef CONFIG_CPU_S3C2410
1184
1185 static int s3c2410_serial_setsource(struct uart_port *port,
1186 struct s3c24xx_uart_clksrc *clk)
1187 {
1188 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1189
1190 if (strcmp(clk->name, "uclk") == 0)
1191 ucon |= S3C2410_UCON_UCLK;
1192 else
1193 ucon &= ~S3C2410_UCON_UCLK;
1194
1195 wr_regl(port, S3C2410_UCON, ucon);
1196 return 0;
1197 }
1198
1199 static int s3c2410_serial_getsource(struct uart_port *port,
1200 struct s3c24xx_uart_clksrc *clk)
1201 {
1202 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1203
1204 clk->divisor = 1;
1205 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1206
1207 return 0;
1208 }
1209
1210 static struct s3c24xx_uart_info s3c2410_uart_inf = {
1211 .name = "Samsung S3C2410 UART",
1212 .type = PORT_S3C2410,
1213 .fifosize = 16,
1214 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1215 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1216 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1217 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1218 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1219 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1220 .get_clksrc = s3c2410_serial_getsource,
1221 .set_clksrc = s3c2410_serial_setsource,
1222 };
1223
1224 /* device management */
1225
1226 static int s3c2410_serial_probe(struct device *dev)
1227 {
1228 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
1229 }
1230
1231 static struct device_driver s3c2410_serial_drv = {
1232 .name = "s3c2410-uart",
1233 .bus = &platform_bus_type,
1234 .probe = s3c2410_serial_probe,
1235 .remove = s3c24xx_serial_remove,
1236 .suspend = s3c24xx_serial_suspend,
1237 .resume = s3c24xx_serial_resume,
1238 };
1239
1240 static inline int s3c2410_serial_init(void)
1241 {
1242 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
1243 }
1244
1245 static inline void s3c2410_serial_exit(void)
1246 {
1247 driver_unregister(&s3c2410_serial_drv);
1248 }
1249
1250 #define s3c2410_uart_inf_at &s3c2410_uart_inf
1251 #else
1252
1253 static inline int s3c2410_serial_init(void)
1254 {
1255 return 0;
1256 }
1257
1258 static inline void s3c2410_serial_exit(void)
1259 {
1260 }
1261
1262 #define s3c2410_uart_inf_at NULL
1263
1264 #endif /* CONFIG_CPU_S3C2410 */
1265
1266 #ifdef CONFIG_CPU_S3C2440
1267
1268 static int s3c2440_serial_setsource(struct uart_port *port,
1269 struct s3c24xx_uart_clksrc *clk)
1270 {
1271 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1272
1273 // todo - proper fclk<>nonfclk switch //
1274
1275 ucon &= ~S3C2440_UCON_CLKMASK;
1276
1277 if (strcmp(clk->name, "uclk") == 0)
1278 ucon |= S3C2440_UCON_UCLK;
1279 else if (strcmp(clk->name, "pclk") == 0)
1280 ucon |= S3C2440_UCON_PCLK;
1281 else if (strcmp(clk->name, "fclk") == 0)
1282 ucon |= S3C2440_UCON_FCLK;
1283 else {
1284 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1285 return -EINVAL;
1286 }
1287
1288 wr_regl(port, S3C2410_UCON, ucon);
1289 return 0;
1290 }
1291
1292
1293 static int s3c2440_serial_getsource(struct uart_port *port,
1294 struct s3c24xx_uart_clksrc *clk)
1295 {
1296 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1297
1298 switch (ucon & S3C2440_UCON_CLKMASK) {
1299 case S3C2440_UCON_UCLK:
1300 clk->divisor = 1;
1301 clk->name = "uclk";
1302 break;
1303
1304 case S3C2440_UCON_PCLK:
1305 case S3C2440_UCON_PCLK2:
1306 clk->divisor = 1;
1307 clk->name = "pclk";
1308 break;
1309
1310 case S3C2440_UCON_FCLK:
1311 clk->divisor = 7; /* todo - work out divisor */
1312 clk->name = "fclk";
1313 break;
1314 }
1315
1316 return 0;
1317 }
1318
1319
1320 static struct s3c24xx_uart_info s3c2440_uart_inf = {
1321 .name = "Samsung S3C2440 UART",
1322 .type = PORT_S3C2440,
1323 .fifosize = 64,
1324 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1325 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1326 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1327 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1328 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1329 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1330 .get_clksrc = s3c2440_serial_getsource,
1331 .set_clksrc = s3c2440_serial_setsource
1332 };
1333
1334 /* device management */
1335
1336 static int s3c2440_serial_probe(struct device *dev)
1337 {
1338 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1339 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1340 }
1341
1342 static struct device_driver s3c2440_serial_drv = {
1343 .name = "s3c2440-uart",
1344 .bus = &platform_bus_type,
1345 .probe = s3c2440_serial_probe,
1346 .remove = s3c24xx_serial_remove,
1347 .suspend = s3c24xx_serial_suspend,
1348 .resume = s3c24xx_serial_resume,
1349 };
1350
1351
1352 static inline int s3c2440_serial_init(void)
1353 {
1354 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
1355 }
1356
1357 static inline void s3c2440_serial_exit(void)
1358 {
1359 driver_unregister(&s3c2440_serial_drv);
1360 }
1361
1362 #define s3c2440_uart_inf_at &s3c2440_uart_inf
1363 #else
1364
1365 static inline int s3c2440_serial_init(void)
1366 {
1367 return 0;
1368 }
1369
1370 static inline void s3c2440_serial_exit(void)
1371 {
1372 }
1373
1374 #define s3c2440_uart_inf_at NULL
1375 #endif /* CONFIG_CPU_S3C2440 */
1376
1377 /* module initialisation code */
1378
1379 static int __init s3c24xx_serial_modinit(void)
1380 {
1381 int ret;
1382
1383 ret = uart_register_driver(&s3c24xx_uart_drv);
1384 if (ret < 0) {
1385 printk(KERN_ERR "failed to register UART driver\n");
1386 return -1;
1387 }
1388
1389 s3c2410_serial_init();
1390 s3c2440_serial_init();
1391
1392 return 0;
1393 }
1394
1395 static void __exit s3c24xx_serial_modexit(void)
1396 {
1397 s3c2410_serial_exit();
1398 s3c2440_serial_exit();
1399
1400 uart_unregister_driver(&s3c24xx_uart_drv);
1401 }
1402
1403
1404 module_init(s3c24xx_serial_modinit);
1405 module_exit(s3c24xx_serial_modexit);
1406
1407 /* Console code */
1408
1409 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
1410
1411 static struct uart_port *cons_uart;
1412
1413 static int
1414 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1415 {
1416 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1417 unsigned long ufstat, utrstat;
1418
1419 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1420 /* fifo mode - check ammount of data in fifo registers... */
1421
1422 ufstat = rd_regl(port, S3C2410_UFSTAT);
1423 return (ufstat & info->tx_fifofull) ? 0 : 1;
1424 }
1425
1426 /* in non-fifo mode, we go and use the tx buffer empty */
1427
1428 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1429 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1430 }
1431
1432 static void
1433 s3c24xx_serial_console_write(struct console *co, const char *s,
1434 unsigned int count)
1435 {
1436 int i;
1437 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1438
1439 for (i = 0; i < count; i++) {
1440 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1441 barrier();
1442
1443 wr_regb(cons_uart, S3C2410_UTXH, s[i]);
1444
1445 if (s[i] == '\n') {
1446 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1447 barrier();
1448
1449 wr_regb(cons_uart, S3C2410_UTXH, '\r');
1450 }
1451 }
1452 }
1453
1454 static void __init
1455 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1456 int *parity, int *bits)
1457 {
1458 struct s3c24xx_uart_clksrc clksrc;
1459 struct clk *clk;
1460 unsigned int ulcon;
1461 unsigned int ucon;
1462 unsigned int ubrdiv;
1463 unsigned long rate;
1464
1465 ulcon = rd_regl(port, S3C2410_ULCON);
1466 ucon = rd_regl(port, S3C2410_UCON);
1467 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1468
1469 dbg("s3c24xx_serial_get_options: port=%p\n"
1470 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1471 port, ulcon, ucon, ubrdiv);
1472
1473 if ((ucon & 0xf) != 0) {
1474 /* consider the serial port configured if the tx/rx mode set */
1475
1476 switch (ulcon & S3C2410_LCON_CSMASK) {
1477 case S3C2410_LCON_CS5:
1478 *bits = 5;
1479 break;
1480 case S3C2410_LCON_CS6:
1481 *bits = 6;
1482 break;
1483 case S3C2410_LCON_CS7:
1484 *bits = 7;
1485 break;
1486 default:
1487 case S3C2410_LCON_CS8:
1488 *bits = 8;
1489 break;
1490 }
1491
1492 switch (ulcon & S3C2410_LCON_PMASK) {
1493 case S3C2410_LCON_PEVEN:
1494 *parity = 'e';
1495 break;
1496
1497 case S3C2410_LCON_PODD:
1498 *parity = 'o';
1499 break;
1500
1501 case S3C2410_LCON_PNONE:
1502 default:
1503 *parity = 'n';
1504 }
1505
1506 /* now calculate the baud rate */
1507
1508 s3c24xx_serial_getsource(port, &clksrc);
1509
1510 clk = clk_get(port->dev, clksrc.name);
1511 if (!IS_ERR(clk) && clk != NULL)
1512 rate = clk_get_rate(clk);
1513 else
1514 rate = 1;
1515
1516
1517 *baud = rate / ( 16 * (ubrdiv + 1));
1518 dbg("calculated baud %d\n", *baud);
1519 }
1520
1521 }
1522
1523 /* s3c24xx_serial_init_ports
1524 *
1525 * initialise the serial ports from the machine provided initialisation
1526 * data.
1527 */
1528
1529 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1530 {
1531 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1532 struct platform_device **platdev_ptr;
1533 int i;
1534
1535 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1536
1537 platdev_ptr = s3c24xx_uart_devs;
1538
1539 for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
1540 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1541 }
1542
1543 return 0;
1544 }
1545
1546 static int __init
1547 s3c24xx_serial_console_setup(struct console *co, char *options)
1548 {
1549 struct uart_port *port;
1550 int baud = 9600;
1551 int bits = 8;
1552 int parity = 'n';
1553 int flow = 'n';
1554
1555 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1556 co, co->index, options);
1557
1558 /* is this a valid port */
1559
1560 if (co->index == -1 || co->index >= NR_PORTS)
1561 co->index = 0;
1562
1563 port = &s3c24xx_serial_ports[co->index].port;
1564
1565 /* is the port configured? */
1566
1567 if (port->mapbase == 0x0) {
1568 co->index = 0;
1569 port = &s3c24xx_serial_ports[co->index].port;
1570 }
1571
1572 cons_uart = port;
1573
1574 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1575
1576 /*
1577 * Check whether an invalid uart number has been specified, and
1578 * if so, search for the first available port that does have
1579 * console support.
1580 */
1581 if (options)
1582 uart_parse_options(options, &baud, &parity, &bits, &flow);
1583 else
1584 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1585
1586 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1587
1588 return uart_set_options(port, co, baud, parity, bits, flow);
1589 }
1590
1591 /* s3c24xx_serial_initconsole
1592 *
1593 * initialise the console from one of the uart drivers
1594 */
1595
1596 static struct console s3c24xx_serial_console =
1597 {
1598 .name = S3C24XX_SERIAL_NAME,
1599 .device = uart_console_device,
1600 .flags = CON_PRINTBUFFER,
1601 .index = -1,
1602 .write = s3c24xx_serial_console_write,
1603 .setup = s3c24xx_serial_console_setup
1604 };
1605
1606
1607 static int s3c24xx_serial_initconsole(void)
1608 {
1609 struct s3c24xx_uart_info *info;
1610 struct platform_device *dev = s3c24xx_uart_devs[0];
1611
1612 dbg("s3c24xx_serial_initconsole\n");
1613
1614 /* select driver based on the cpu */
1615
1616 if (dev == NULL) {
1617 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1618 return 0;
1619 }
1620
1621 if (strcmp(dev->name, "s3c2410-uart") == 0) {
1622 info = s3c2410_uart_inf_at;
1623 } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
1624 info = s3c2440_uart_inf_at;
1625 } else {
1626 printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
1627 return 0;
1628 }
1629
1630 if (info == NULL) {
1631 printk(KERN_ERR "s3c24xx: no driver for console\n");
1632 return 0;
1633 }
1634
1635 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1636 s3c24xx_serial_init_ports(info);
1637
1638 register_console(&s3c24xx_serial_console);
1639 return 0;
1640 }
1641
1642 console_initcall(s3c24xx_serial_initconsole);
1643
1644 #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
1645
1646 MODULE_LICENSE("GPL");
1647 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1648 MODULE_DESCRIPTION("Samsung S3C2410/S3C2440 Serial port driver");
1649
|
This page was automatically generated by the
LXR engine.
|